1 /* 2 * Copyright 2012-14 Advanced Micro Devices, Inc. 3 * 4 * Permission is hereby granted, free of charge, to any person obtaining a 5 * copy of this software and associated documentation files (the "Software"), 6 * to deal in the Software without restriction, including without limitation 7 * the rights to use, copy, modify, merge, publish, distribute, sublicense, 8 * and/or sell copies of the Software, and to permit persons to whom the 9 * Software is furnished to do so, subject to the following conditions: 10 * 11 * The above copyright notice and this permission notice shall be included in 12 * all copies or substantial portions of the Software. 13 * 14 * THE SOFTWARE IS PROVIDED "AS IS", WITHOUT WARRANTY OF ANY KIND, EXPRESS OR 15 * IMPLIED, INCLUDING BUT NOT LIMITED TO THE WARRANTIES OF MERCHANTABILITY, 16 * FITNESS FOR A PARTICULAR PURPOSE AND NONINFRINGEMENT. IN NO EVENT SHALL 17 * THE COPYRIGHT HOLDER(S) OR AUTHOR(S) BE LIABLE FOR ANY CLAIM, DAMAGES OR 18 * OTHER LIABILITY, WHETHER IN AN ACTION OF CONTRACT, TORT OR OTHERWISE, 19 * ARISING FROM, OUT OF OR IN CONNECTION WITH THE SOFTWARE OR THE USE OR 20 * OTHER DEALINGS IN THE SOFTWARE. 21 * 22 * Authors: AMD 23 * 24 */ 25 26 #ifndef DC_INTERFACE_H_ 27 #define DC_INTERFACE_H_ 28 29 #include "dc_types.h" 30 #include "grph_object_defs.h" 31 #include "logger_types.h" 32 #include "gpio_types.h" 33 #include "link_service_types.h" 34 #include "grph_object_ctrl_defs.h" 35 #include <inc/hw/opp.h> 36 37 #include "inc/hw_sequencer.h" 38 #include "inc/compressor.h" 39 #include "inc/hw/dmcu.h" 40 #include "dml/display_mode_lib.h" 41 42 #define DC_VER "3.2.56" 43 44 #define MAX_SURFACES 3 45 #define MAX_PLANES 6 46 #define MAX_STREAMS 6 47 #define MAX_SINKS_PER_LINK 4 48 49 /******************************************************************************* 50 * Display Core Interfaces 51 ******************************************************************************/ 52 struct dc_versions { 53 const char *dc_ver; 54 struct dmcu_version dmcu_version; 55 }; 56 57 enum dc_plane_type { 58 DC_PLANE_TYPE_INVALID, 59 DC_PLANE_TYPE_DCE_RGB, 60 DC_PLANE_TYPE_DCE_UNDERLAY, 61 DC_PLANE_TYPE_DCN_UNIVERSAL, 62 }; 63 64 struct dc_plane_cap { 65 enum dc_plane_type type; 66 uint32_t blends_with_above : 1; 67 uint32_t blends_with_below : 1; 68 uint32_t per_pixel_alpha : 1; 69 struct { 70 uint32_t argb8888 : 1; 71 uint32_t nv12 : 1; 72 uint32_t fp16 : 1; 73 uint32_t p010 : 1; 74 uint32_t ayuv : 1; 75 } pixel_format_support; 76 // max upscaling factor x1000 77 // upscaling factors are always >= 1 78 // for example, 1080p -> 8K is 4.0, or 4000 raw value 79 struct { 80 uint32_t argb8888; 81 uint32_t nv12; 82 uint32_t fp16; 83 } max_upscale_factor; 84 // max downscale factor x1000 85 // downscale factors are always <= 1 86 // for example, 8K -> 1080p is 0.25, or 250 raw value 87 struct { 88 uint32_t argb8888; 89 uint32_t nv12; 90 uint32_t fp16; 91 } max_downscale_factor; 92 }; 93 94 struct dc_caps { 95 uint32_t max_streams; 96 uint32_t max_links; 97 uint32_t max_audios; 98 uint32_t max_slave_planes; 99 uint32_t max_planes; 100 uint32_t max_downscale_ratio; 101 uint32_t i2c_speed_in_khz; 102 uint32_t dmdata_alloc_size; 103 unsigned int max_cursor_size; 104 unsigned int max_video_width; 105 int linear_pitch_alignment; 106 bool dcc_const_color; 107 bool dynamic_audio; 108 bool is_apu; 109 bool dual_link_dvi; 110 bool post_blend_color_processing; 111 bool force_dp_tps4_for_cp2520; 112 bool disable_dp_clk_share; 113 bool psp_setup_panel_mode; 114 bool extended_aux_timeout_support; 115 #ifdef CONFIG_DRM_AMD_DC_DCN2_0 116 bool hw_3d_lut; 117 #endif 118 struct dc_plane_cap planes[MAX_PLANES]; 119 }; 120 121 struct dc_bug_wa { 122 #if defined(CONFIG_DRM_AMD_DC_DCN2_0) 123 bool no_connect_phy_config; 124 bool dedcn20_305_wa; 125 #endif 126 bool skip_clock_update; 127 }; 128 129 struct dc_dcc_surface_param { 130 struct dc_size surface_size; 131 enum surface_pixel_format format; 132 enum swizzle_mode_values swizzle_mode; 133 enum dc_scan_direction scan; 134 }; 135 136 struct dc_dcc_setting { 137 unsigned int max_compressed_blk_size; 138 unsigned int max_uncompressed_blk_size; 139 bool independent_64b_blks; 140 }; 141 142 struct dc_surface_dcc_cap { 143 union { 144 struct { 145 struct dc_dcc_setting rgb; 146 } grph; 147 148 struct { 149 struct dc_dcc_setting luma; 150 struct dc_dcc_setting chroma; 151 } video; 152 }; 153 154 bool capable; 155 bool const_color_support; 156 }; 157 158 struct dc_static_screen_events { 159 bool force_trigger; 160 bool cursor_update; 161 bool surface_update; 162 bool overlay_update; 163 }; 164 165 166 /* Surface update type is used by dc_update_surfaces_and_stream 167 * The update type is determined at the very beginning of the function based 168 * on parameters passed in and decides how much programming (or updating) is 169 * going to be done during the call. 170 * 171 * UPDATE_TYPE_FAST is used for really fast updates that do not require much 172 * logical calculations or hardware register programming. This update MUST be 173 * ISR safe on windows. Currently fast update will only be used to flip surface 174 * address. 175 * 176 * UPDATE_TYPE_MED is used for slower updates which require significant hw 177 * re-programming however do not affect bandwidth consumption or clock 178 * requirements. At present, this is the level at which front end updates 179 * that do not require us to run bw_calcs happen. These are in/out transfer func 180 * updates, viewport offset changes, recout size changes and pixel depth changes. 181 * This update can be done at ISR, but we want to minimize how often this happens. 182 * 183 * UPDATE_TYPE_FULL is slow. Really slow. This requires us to recalculate our 184 * bandwidth and clocks, possibly rearrange some pipes and reprogram anything front 185 * end related. Any time viewport dimensions, recout dimensions, scaling ratios or 186 * gamma need to be adjusted or pipe needs to be turned on (or disconnected) we do 187 * a full update. This cannot be done at ISR level and should be a rare event. 188 * Unless someone is stress testing mpo enter/exit, playing with colour or adjusting 189 * underscan we don't expect to see this call at all. 190 */ 191 192 enum surface_update_type { 193 UPDATE_TYPE_FAST, /* super fast, safe to execute in isr */ 194 UPDATE_TYPE_MED, /* ISR safe, most of programming needed, no bw/clk change*/ 195 UPDATE_TYPE_FULL, /* may need to shuffle resources */ 196 }; 197 198 /* Forward declaration*/ 199 struct dc; 200 struct dc_plane_state; 201 struct dc_state; 202 203 204 struct dc_cap_funcs { 205 bool (*get_dcc_compression_cap)(const struct dc *dc, 206 const struct dc_dcc_surface_param *input, 207 struct dc_surface_dcc_cap *output); 208 }; 209 210 struct link_training_settings; 211 212 213 /* Structure to hold configuration flags set by dm at dc creation. */ 214 struct dc_config { 215 bool gpu_vm_support; 216 bool disable_disp_pll_sharing; 217 bool fbc_support; 218 bool optimize_edp_link_rate; 219 bool disable_fractional_pwm; 220 bool allow_seamless_boot_optimization; 221 bool power_down_display_on_boot; 222 bool edp_not_connected; 223 bool force_enum_edp; 224 bool forced_clocks; 225 bool disable_extended_timeout_support; // Used to disable extended timeout and lttpr feature as well 226 bool multi_mon_pp_mclk_switch; 227 }; 228 229 enum visual_confirm { 230 VISUAL_CONFIRM_DISABLE = 0, 231 VISUAL_CONFIRM_SURFACE = 1, 232 VISUAL_CONFIRM_HDR = 2, 233 VISUAL_CONFIRM_MPCTREE = 4, 234 }; 235 236 enum dcc_option { 237 DCC_ENABLE = 0, 238 DCC_DISABLE = 1, 239 DCC_HALF_REQ_DISALBE = 2, 240 }; 241 242 enum pipe_split_policy { 243 MPC_SPLIT_DYNAMIC = 0, 244 MPC_SPLIT_AVOID = 1, 245 MPC_SPLIT_AVOID_MULT_DISP = 2, 246 }; 247 248 enum wm_report_mode { 249 WM_REPORT_DEFAULT = 0, 250 WM_REPORT_OVERRIDE = 1, 251 }; 252 enum dtm_pstate{ 253 dtm_level_p0 = 0,/*highest voltage*/ 254 dtm_level_p1, 255 dtm_level_p2, 256 dtm_level_p3, 257 dtm_level_p4,/*when active_display_count = 0*/ 258 }; 259 260 enum dcn_pwr_state { 261 DCN_PWR_STATE_UNKNOWN = -1, 262 DCN_PWR_STATE_MISSION_MODE = 0, 263 DCN_PWR_STATE_LOW_POWER = 3, 264 }; 265 266 /* 267 * For any clocks that may differ per pipe 268 * only the max is stored in this structure 269 */ 270 struct dc_clocks { 271 int dispclk_khz; 272 int dppclk_khz; 273 int dcfclk_khz; 274 int socclk_khz; 275 int dcfclk_deep_sleep_khz; 276 int fclk_khz; 277 int phyclk_khz; 278 int dramclk_khz; 279 bool p_state_change_support; 280 enum dcn_pwr_state pwr_state; 281 /* 282 * Elements below are not compared for the purposes of 283 * optimization required 284 */ 285 bool prev_p_state_change_support; 286 enum dtm_pstate dtm_level; 287 int max_supported_dppclk_khz; 288 int max_supported_dispclk_khz; 289 int bw_dppclk_khz; /*a copy of dppclk_khz*/ 290 int bw_dispclk_khz; 291 }; 292 293 struct dc_bw_validation_profile { 294 bool enable; 295 296 unsigned long long total_ticks; 297 unsigned long long voltage_level_ticks; 298 unsigned long long watermark_ticks; 299 unsigned long long rq_dlg_ticks; 300 301 unsigned long long total_count; 302 unsigned long long skip_fast_count; 303 unsigned long long skip_pass_count; 304 unsigned long long skip_fail_count; 305 }; 306 307 #define BW_VAL_TRACE_SETUP() \ 308 unsigned long long end_tick = 0; \ 309 unsigned long long voltage_level_tick = 0; \ 310 unsigned long long watermark_tick = 0; \ 311 unsigned long long start_tick = dc->debug.bw_val_profile.enable ? \ 312 dm_get_timestamp(dc->ctx) : 0 313 314 #define BW_VAL_TRACE_COUNT() \ 315 if (dc->debug.bw_val_profile.enable) \ 316 dc->debug.bw_val_profile.total_count++ 317 318 #define BW_VAL_TRACE_SKIP(status) \ 319 if (dc->debug.bw_val_profile.enable) { \ 320 if (!voltage_level_tick) \ 321 voltage_level_tick = dm_get_timestamp(dc->ctx); \ 322 dc->debug.bw_val_profile.skip_ ## status ## _count++; \ 323 } 324 325 #define BW_VAL_TRACE_END_VOLTAGE_LEVEL() \ 326 if (dc->debug.bw_val_profile.enable) \ 327 voltage_level_tick = dm_get_timestamp(dc->ctx) 328 329 #define BW_VAL_TRACE_END_WATERMARKS() \ 330 if (dc->debug.bw_val_profile.enable) \ 331 watermark_tick = dm_get_timestamp(dc->ctx) 332 333 #define BW_VAL_TRACE_FINISH() \ 334 if (dc->debug.bw_val_profile.enable) { \ 335 end_tick = dm_get_timestamp(dc->ctx); \ 336 dc->debug.bw_val_profile.total_ticks += end_tick - start_tick; \ 337 dc->debug.bw_val_profile.voltage_level_ticks += voltage_level_tick - start_tick; \ 338 if (watermark_tick) { \ 339 dc->debug.bw_val_profile.watermark_ticks += watermark_tick - voltage_level_tick; \ 340 dc->debug.bw_val_profile.rq_dlg_ticks += end_tick - watermark_tick; \ 341 } \ 342 } 343 344 struct dc_debug_options { 345 enum visual_confirm visual_confirm; 346 bool sanity_checks; 347 bool max_disp_clk; 348 bool surface_trace; 349 bool timing_trace; 350 bool clock_trace; 351 bool validation_trace; 352 bool bandwidth_calcs_trace; 353 int max_downscale_src_width; 354 355 /* stutter efficiency related */ 356 bool disable_stutter; 357 bool use_max_lb; 358 enum dcc_option disable_dcc; 359 enum pipe_split_policy pipe_split_policy; 360 bool force_single_disp_pipe_split; 361 bool voltage_align_fclk; 362 363 bool disable_dfs_bypass; 364 bool disable_dpp_power_gate; 365 bool disable_hubp_power_gate; 366 #ifdef CONFIG_DRM_AMD_DC_DSC_SUPPORT 367 bool disable_dsc_power_gate; 368 int dsc_min_slice_height_override; 369 #endif 370 bool disable_pplib_wm_range; 371 enum wm_report_mode pplib_wm_report_mode; 372 unsigned int min_disp_clk_khz; 373 unsigned int min_dpp_clk_khz; 374 int sr_exit_time_dpm0_ns; 375 int sr_enter_plus_exit_time_dpm0_ns; 376 int sr_exit_time_ns; 377 int sr_enter_plus_exit_time_ns; 378 int urgent_latency_ns; 379 uint32_t underflow_assert_delay_us; 380 int percent_of_ideal_drambw; 381 int dram_clock_change_latency_ns; 382 bool optimized_watermark; 383 int always_scale; 384 bool disable_pplib_clock_request; 385 bool disable_clock_gate; 386 bool disable_dmcu; 387 bool disable_psr; 388 bool force_abm_enable; 389 bool disable_stereo_support; 390 bool vsr_support; 391 bool performance_trace; 392 bool az_endpoint_mute_only; 393 bool always_use_regamma; 394 bool p010_mpo_support; 395 bool recovery_enabled; 396 bool avoid_vbios_exec_table; 397 bool scl_reset_length10; 398 bool hdmi20_disable; 399 bool skip_detection_link_training; 400 bool remove_disconnect_edp; 401 unsigned int force_odm_combine; //bit vector based on otg inst 402 unsigned int force_fclk_khz; 403 bool disable_tri_buf; 404 struct dc_bw_validation_profile bw_val_profile; 405 #ifdef CONFIG_DRM_AMD_DC_DSC_SUPPORT 406 bool disable_fec; 407 #endif 408 #ifdef CONFIG_DRM_AMD_DC_DCN2_1 409 bool disable_48mhz_pwrdwn; 410 #endif 411 /* This forces a hard min on the DCFCLK requested to SMU/PP 412 * watermarks are not affected. 413 */ 414 unsigned int force_min_dcfclk_mhz; 415 bool disable_timing_sync; 416 #if defined(CONFIG_DRM_AMD_DC_DCN2_0) 417 bool cm_in_bypass; 418 #endif 419 int force_clock_mode;/*every mode change.*/ 420 }; 421 422 struct dc_debug_data { 423 uint32_t ltFailCount; 424 uint32_t i2cErrorCount; 425 uint32_t auxErrorCount; 426 }; 427 428 #ifdef CONFIG_DRM_AMD_DC_DCN2_0 429 struct dc_phy_addr_space_config { 430 struct { 431 uint64_t start_addr; 432 uint64_t end_addr; 433 uint64_t fb_top; 434 uint64_t fb_offset; 435 uint64_t fb_base; 436 uint64_t agp_top; 437 uint64_t agp_bot; 438 uint64_t agp_base; 439 } system_aperture; 440 441 struct { 442 uint64_t page_table_start_addr; 443 uint64_t page_table_end_addr; 444 uint64_t page_table_base_addr; 445 } gart_config; 446 447 bool valid; 448 uint64_t page_table_default_page_addr; 449 }; 450 451 struct dc_virtual_addr_space_config { 452 uint64_t page_table_base_addr; 453 uint64_t page_table_start_addr; 454 uint64_t page_table_end_addr; 455 uint32_t page_table_block_size_in_bytes; 456 uint8_t page_table_depth; // 1 = 1 level, 2 = 2 level, etc. 0 = invalid 457 }; 458 #endif 459 460 struct dc_bounding_box_overrides { 461 int sr_exit_time_ns; 462 int sr_enter_plus_exit_time_ns; 463 int urgent_latency_ns; 464 int percent_of_ideal_drambw; 465 int dram_clock_change_latency_ns; 466 /* This forces a hard min on the DCFCLK we use 467 * for DML. Unlike the debug option for forcing 468 * DCFCLK, this override affects watermark calculations 469 */ 470 int min_dcfclk_mhz; 471 }; 472 473 struct dc_state; 474 struct resource_pool; 475 struct dce_hwseq; 476 struct gpu_info_soc_bounding_box_v1_0; 477 struct dc { 478 struct dc_versions versions; 479 struct dc_caps caps; 480 struct dc_cap_funcs cap_funcs; 481 struct dc_config config; 482 struct dc_debug_options debug; 483 struct dc_bounding_box_overrides bb_overrides; 484 struct dc_bug_wa work_arounds; 485 struct dc_context *ctx; 486 #ifdef CONFIG_DRM_AMD_DC_DCN2_0 487 struct dc_phy_addr_space_config vm_pa_config; 488 #endif 489 490 uint8_t link_count; 491 struct dc_link *links[MAX_PIPES * 2]; 492 493 struct dc_state *current_state; 494 struct resource_pool *res_pool; 495 496 struct clk_mgr *clk_mgr; 497 498 /* Display Engine Clock levels */ 499 struct dm_pp_clock_levels sclk_lvls; 500 501 /* Inputs into BW and WM calculations. */ 502 struct bw_calcs_dceip *bw_dceip; 503 struct bw_calcs_vbios *bw_vbios; 504 #ifdef CONFIG_DRM_AMD_DC_DCN1_0 505 struct dcn_soc_bounding_box *dcn_soc; 506 struct dcn_ip_params *dcn_ip; 507 struct display_mode_lib dml; 508 #endif 509 510 /* HW functions */ 511 struct hw_sequencer_funcs hwss; 512 struct dce_hwseq *hwseq; 513 514 /* Require to optimize clocks and bandwidth for added/removed planes */ 515 bool optimized_required; 516 517 /* Require to maintain clocks and bandwidth for UEFI enabled HW */ 518 bool optimize_seamless_boot; 519 520 /* FBC compressor */ 521 struct compressor *fbc_compressor; 522 523 struct dc_debug_data debug_data; 524 525 const char *build_id; 526 #ifdef CONFIG_DRM_AMD_DC_DCN2_0 527 struct vm_helper *vm_helper; 528 const struct gpu_info_soc_bounding_box_v1_0 *soc_bounding_box; 529 #endif 530 }; 531 532 enum frame_buffer_mode { 533 FRAME_BUFFER_MODE_LOCAL_ONLY = 0, 534 FRAME_BUFFER_MODE_ZFB_ONLY, 535 FRAME_BUFFER_MODE_MIXED_ZFB_AND_LOCAL, 536 } ; 537 538 struct dchub_init_data { 539 int64_t zfb_phys_addr_base; 540 int64_t zfb_mc_base_addr; 541 uint64_t zfb_size_in_byte; 542 enum frame_buffer_mode fb_mode; 543 bool dchub_initialzied; 544 bool dchub_info_valid; 545 }; 546 547 struct dc_init_data { 548 struct hw_asic_id asic_id; 549 void *driver; /* ctx */ 550 struct cgs_device *cgs_device; 551 struct dc_bounding_box_overrides bb_overrides; 552 553 int num_virtual_links; 554 /* 555 * If 'vbios_override' not NULL, it will be called instead 556 * of the real VBIOS. Intended use is Diagnostics on FPGA. 557 */ 558 struct dc_bios *vbios_override; 559 enum dce_environment dce_environment; 560 561 struct dc_config flags; 562 uint32_t log_mask; 563 #ifdef CONFIG_DRM_AMD_DC_DCN2_0 564 /** 565 * gpu_info FW provided soc bounding box struct or 0 if not 566 * available in FW 567 */ 568 const struct gpu_info_soc_bounding_box_v1_0 *soc_bounding_box; 569 #endif 570 }; 571 572 struct dc_callback_init { 573 #ifdef CONFIG_DRM_AMD_DC_HDCP 574 struct cp_psp cp_psp; 575 #else 576 uint8_t reserved; 577 #endif 578 }; 579 580 struct dc *dc_create(const struct dc_init_data *init_params); 581 void dc_hardware_init(struct dc *dc); 582 583 int dc_get_vmid_use_vector(struct dc *dc); 584 #ifdef CONFIG_DRM_AMD_DC_DCN2_0 585 void dc_setup_vm_context(struct dc *dc, struct dc_virtual_addr_space_config *va_config, int vmid); 586 /* Returns the number of vmids supported */ 587 int dc_setup_system_context(struct dc *dc, struct dc_phy_addr_space_config *pa_config); 588 #endif 589 void dc_init_callbacks(struct dc *dc, 590 const struct dc_callback_init *init_params); 591 void dc_deinit_callbacks(struct dc *dc); 592 void dc_destroy(struct dc **dc); 593 594 /******************************************************************************* 595 * Surface Interfaces 596 ******************************************************************************/ 597 598 enum { 599 TRANSFER_FUNC_POINTS = 1025 600 }; 601 602 struct dc_hdr_static_metadata { 603 /* display chromaticities and white point in units of 0.00001 */ 604 unsigned int chromaticity_green_x; 605 unsigned int chromaticity_green_y; 606 unsigned int chromaticity_blue_x; 607 unsigned int chromaticity_blue_y; 608 unsigned int chromaticity_red_x; 609 unsigned int chromaticity_red_y; 610 unsigned int chromaticity_white_point_x; 611 unsigned int chromaticity_white_point_y; 612 613 uint32_t min_luminance; 614 uint32_t max_luminance; 615 uint32_t maximum_content_light_level; 616 uint32_t maximum_frame_average_light_level; 617 }; 618 619 enum dc_transfer_func_type { 620 TF_TYPE_PREDEFINED, 621 TF_TYPE_DISTRIBUTED_POINTS, 622 TF_TYPE_BYPASS, 623 TF_TYPE_HWPWL 624 }; 625 626 struct dc_transfer_func_distributed_points { 627 struct fixed31_32 red[TRANSFER_FUNC_POINTS]; 628 struct fixed31_32 green[TRANSFER_FUNC_POINTS]; 629 struct fixed31_32 blue[TRANSFER_FUNC_POINTS]; 630 631 uint16_t end_exponent; 632 uint16_t x_point_at_y1_red; 633 uint16_t x_point_at_y1_green; 634 uint16_t x_point_at_y1_blue; 635 }; 636 637 enum dc_transfer_func_predefined { 638 TRANSFER_FUNCTION_SRGB, 639 TRANSFER_FUNCTION_BT709, 640 TRANSFER_FUNCTION_PQ, 641 TRANSFER_FUNCTION_LINEAR, 642 TRANSFER_FUNCTION_UNITY, 643 TRANSFER_FUNCTION_HLG, 644 TRANSFER_FUNCTION_HLG12, 645 TRANSFER_FUNCTION_GAMMA22, 646 TRANSFER_FUNCTION_GAMMA24, 647 TRANSFER_FUNCTION_GAMMA26 648 }; 649 650 651 struct dc_transfer_func { 652 struct kref refcount; 653 enum dc_transfer_func_type type; 654 enum dc_transfer_func_predefined tf; 655 /* FP16 1.0 reference level in nits, default is 80 nits, only for PQ*/ 656 uint32_t sdr_ref_white_level; 657 struct dc_context *ctx; 658 union { 659 struct pwl_params pwl; 660 struct dc_transfer_func_distributed_points tf_pts; 661 }; 662 }; 663 664 #if defined(CONFIG_DRM_AMD_DC_DCN2_0) 665 666 union dc_3dlut_state { 667 struct { 668 uint32_t initialized:1; /*if 3dlut is went through color module for initialization */ 669 uint32_t rmu_idx_valid:1; /*if mux settings are valid*/ 670 uint32_t rmu_mux_num:3; /*index of mux to use*/ 671 uint32_t mpc_rmu0_mux:4; /*select mpcc on mux, one of the following : mpcc0, mpcc1, mpcc2, mpcc3*/ 672 uint32_t mpc_rmu1_mux:4; 673 uint32_t mpc_rmu2_mux:4; 674 uint32_t reserved:15; 675 } bits; 676 uint32_t raw; 677 }; 678 679 680 struct dc_3dlut { 681 struct kref refcount; 682 struct tetrahedral_params lut_3d; 683 uint32_t hdr_multiplier; 684 bool initialized; /*remove after diag fix*/ 685 union dc_3dlut_state state; 686 struct dc_context *ctx; 687 }; 688 #endif 689 /* 690 * This structure is filled in by dc_surface_get_status and contains 691 * the last requested address and the currently active address so the called 692 * can determine if there are any outstanding flips 693 */ 694 struct dc_plane_status { 695 struct dc_plane_address requested_address; 696 struct dc_plane_address current_address; 697 bool is_flip_pending; 698 bool is_right_eye; 699 }; 700 701 union surface_update_flags { 702 703 struct { 704 uint32_t addr_update:1; 705 /* Medium updates */ 706 uint32_t dcc_change:1; 707 uint32_t color_space_change:1; 708 uint32_t horizontal_mirror_change:1; 709 uint32_t per_pixel_alpha_change:1; 710 uint32_t global_alpha_change:1; 711 uint32_t sdr_white_level:1; 712 uint32_t rotation_change:1; 713 uint32_t swizzle_change:1; 714 uint32_t scaling_change:1; 715 uint32_t position_change:1; 716 uint32_t in_transfer_func_change:1; 717 uint32_t input_csc_change:1; 718 uint32_t coeff_reduction_change:1; 719 uint32_t output_tf_change:1; 720 uint32_t pixel_format_change:1; 721 uint32_t plane_size_change:1; 722 723 /* Full updates */ 724 uint32_t new_plane:1; 725 uint32_t bpp_change:1; 726 uint32_t gamma_change:1; 727 uint32_t bandwidth_change:1; 728 uint32_t clock_change:1; 729 uint32_t stereo_format_change:1; 730 uint32_t full_update:1; 731 } bits; 732 733 uint32_t raw; 734 }; 735 736 struct dc_plane_state { 737 struct dc_plane_address address; 738 struct dc_plane_flip_time time; 739 #if defined(CONFIG_DRM_AMD_DC_DCN2_0) 740 bool triplebuffer_flips; 741 #endif 742 struct scaling_taps scaling_quality; 743 struct rect src_rect; 744 struct rect dst_rect; 745 struct rect clip_rect; 746 747 struct plane_size plane_size; 748 union dc_tiling_info tiling_info; 749 750 struct dc_plane_dcc_param dcc; 751 752 struct dc_gamma *gamma_correction; 753 struct dc_transfer_func *in_transfer_func; 754 struct dc_bias_and_scale *bias_and_scale; 755 struct dc_csc_transform input_csc_color_matrix; 756 struct fixed31_32 coeff_reduction_factor; 757 uint32_t sdr_white_level; 758 759 // TODO: No longer used, remove 760 struct dc_hdr_static_metadata hdr_static_ctx; 761 762 enum dc_color_space color_space; 763 764 #if defined(CONFIG_DRM_AMD_DC_DCN2_0) 765 struct dc_3dlut *lut3d_func; 766 struct dc_transfer_func *in_shaper_func; 767 struct dc_transfer_func *blend_tf; 768 #endif 769 770 enum surface_pixel_format format; 771 enum dc_rotation_angle rotation; 772 enum plane_stereo_format stereo_format; 773 774 bool is_tiling_rotated; 775 bool per_pixel_alpha; 776 bool global_alpha; 777 int global_alpha_value; 778 bool visible; 779 bool flip_immediate; 780 bool horizontal_mirror; 781 int layer_index; 782 783 union surface_update_flags update_flags; 784 /* private to DC core */ 785 struct dc_plane_status status; 786 struct dc_context *ctx; 787 788 /* HACK: Workaround for forcing full reprogramming under some conditions */ 789 bool force_full_update; 790 791 /* private to dc_surface.c */ 792 enum dc_irq_source irq_source; 793 struct kref refcount; 794 }; 795 796 struct dc_plane_info { 797 struct plane_size plane_size; 798 union dc_tiling_info tiling_info; 799 struct dc_plane_dcc_param dcc; 800 enum surface_pixel_format format; 801 enum dc_rotation_angle rotation; 802 enum plane_stereo_format stereo_format; 803 enum dc_color_space color_space; 804 unsigned int sdr_white_level; 805 bool horizontal_mirror; 806 bool visible; 807 bool per_pixel_alpha; 808 bool global_alpha; 809 int global_alpha_value; 810 bool input_csc_enabled; 811 int layer_index; 812 }; 813 814 struct dc_scaling_info { 815 struct rect src_rect; 816 struct rect dst_rect; 817 struct rect clip_rect; 818 struct scaling_taps scaling_quality; 819 }; 820 821 struct dc_surface_update { 822 struct dc_plane_state *surface; 823 824 /* isr safe update parameters. null means no updates */ 825 const struct dc_flip_addrs *flip_addr; 826 const struct dc_plane_info *plane_info; 827 const struct dc_scaling_info *scaling_info; 828 829 /* following updates require alloc/sleep/spin that is not isr safe, 830 * null means no updates 831 */ 832 const struct dc_gamma *gamma; 833 const struct dc_transfer_func *in_transfer_func; 834 835 const struct dc_csc_transform *input_csc_color_matrix; 836 const struct fixed31_32 *coeff_reduction_factor; 837 #if defined(CONFIG_DRM_AMD_DC_DCN2_0) 838 const struct dc_transfer_func *func_shaper; 839 const struct dc_3dlut *lut3d_func; 840 const struct dc_transfer_func *blend_tf; 841 #endif 842 }; 843 844 /* 845 * Create a new surface with default parameters; 846 */ 847 struct dc_plane_state *dc_create_plane_state(struct dc *dc); 848 const struct dc_plane_status *dc_plane_get_status( 849 const struct dc_plane_state *plane_state); 850 851 void dc_plane_state_retain(struct dc_plane_state *plane_state); 852 void dc_plane_state_release(struct dc_plane_state *plane_state); 853 854 void dc_gamma_retain(struct dc_gamma *dc_gamma); 855 void dc_gamma_release(struct dc_gamma **dc_gamma); 856 struct dc_gamma *dc_create_gamma(void); 857 858 void dc_transfer_func_retain(struct dc_transfer_func *dc_tf); 859 void dc_transfer_func_release(struct dc_transfer_func *dc_tf); 860 struct dc_transfer_func *dc_create_transfer_func(void); 861 862 #if defined(CONFIG_DRM_AMD_DC_DCN2_0) 863 struct dc_3dlut *dc_create_3dlut_func(void); 864 void dc_3dlut_func_release(struct dc_3dlut *lut); 865 void dc_3dlut_func_retain(struct dc_3dlut *lut); 866 #endif 867 /* 868 * This structure holds a surface address. There could be multiple addresses 869 * in cases such as Stereo 3D, Planar YUV, etc. Other per-flip attributes such 870 * as frame durations and DCC format can also be set. 871 */ 872 struct dc_flip_addrs { 873 struct dc_plane_address address; 874 unsigned int flip_timestamp_in_us; 875 bool flip_immediate; 876 /* TODO: add flip duration for FreeSync */ 877 }; 878 879 bool dc_post_update_surfaces_to_stream( 880 struct dc *dc); 881 882 #include "dc_stream.h" 883 884 /* 885 * Structure to store surface/stream associations for validation 886 */ 887 struct dc_validation_set { 888 struct dc_stream_state *stream; 889 struct dc_plane_state *plane_states[MAX_SURFACES]; 890 uint8_t plane_count; 891 }; 892 893 bool dc_validate_seamless_boot_timing(const struct dc *dc, 894 const struct dc_sink *sink, 895 struct dc_crtc_timing *crtc_timing); 896 897 enum dc_status dc_validate_plane(struct dc *dc, const struct dc_plane_state *plane_state); 898 899 void get_clock_requirements_for_state(struct dc_state *state, struct AsicStateEx *info); 900 901 bool dc_set_generic_gpio_for_stereo(bool enable, 902 struct gpio_service *gpio_service); 903 904 /* 905 * fast_validate: we return after determining if we can support the new state, 906 * but before we populate the programming info 907 */ 908 enum dc_status dc_validate_global_state( 909 struct dc *dc, 910 struct dc_state *new_ctx, 911 bool fast_validate); 912 913 914 void dc_resource_state_construct( 915 const struct dc *dc, 916 struct dc_state *dst_ctx); 917 918 void dc_resource_state_copy_construct( 919 const struct dc_state *src_ctx, 920 struct dc_state *dst_ctx); 921 922 void dc_resource_state_copy_construct_current( 923 const struct dc *dc, 924 struct dc_state *dst_ctx); 925 926 void dc_resource_state_destruct(struct dc_state *context); 927 928 /* 929 * TODO update to make it about validation sets 930 * Set up streams and links associated to drive sinks 931 * The streams parameter is an absolute set of all active streams. 932 * 933 * After this call: 934 * Phy, Encoder, Timing Generator are programmed and enabled. 935 * New streams are enabled with blank stream; no memory read. 936 */ 937 bool dc_commit_state(struct dc *dc, struct dc_state *context); 938 939 940 struct dc_state *dc_create_state(struct dc *dc); 941 struct dc_state *dc_copy_state(struct dc_state *src_ctx); 942 void dc_retain_state(struct dc_state *context); 943 void dc_release_state(struct dc_state *context); 944 945 /******************************************************************************* 946 * Link Interfaces 947 ******************************************************************************/ 948 949 struct dpcd_caps { 950 union dpcd_rev dpcd_rev; 951 union max_lane_count max_ln_count; 952 union max_down_spread max_down_spread; 953 union dprx_feature dprx_feature; 954 955 /* valid only for eDP v1.4 or higher*/ 956 uint8_t edp_supported_link_rates_count; 957 enum dc_link_rate edp_supported_link_rates[8]; 958 959 /* dongle type (DP converter, CV smart dongle) */ 960 enum display_dongle_type dongle_type; 961 /* branch device or sink device */ 962 bool is_branch_dev; 963 /* Dongle's downstream count. */ 964 union sink_count sink_count; 965 /* If dongle_type == DISPLAY_DONGLE_DP_HDMI_CONVERTER, 966 indicates 'Frame Sequential-to-lllFrame Pack' conversion capability.*/ 967 struct dc_dongle_caps dongle_caps; 968 969 uint32_t sink_dev_id; 970 int8_t sink_dev_id_str[6]; 971 int8_t sink_hw_revision; 972 int8_t sink_fw_revision[2]; 973 974 uint32_t branch_dev_id; 975 int8_t branch_dev_name[6]; 976 int8_t branch_hw_revision; 977 int8_t branch_fw_revision[2]; 978 979 bool allow_invalid_MSA_timing_param; 980 bool panel_mode_edp; 981 bool dpcd_display_control_capable; 982 bool ext_receiver_cap_field_present; 983 #ifdef CONFIG_DRM_AMD_DC_DSC_SUPPORT 984 union dpcd_fec_capability fec_cap; 985 struct dpcd_dsc_capabilities dsc_caps; 986 #endif 987 }; 988 989 #include "dc_link.h" 990 991 /******************************************************************************* 992 * Sink Interfaces - A sink corresponds to a display output device 993 ******************************************************************************/ 994 995 struct dc_container_id { 996 // 128bit GUID in binary form 997 unsigned char guid[16]; 998 // 8 byte port ID -> ELD.PortID 999 unsigned int portId[2]; 1000 // 128bit GUID in binary formufacturer name -> ELD.ManufacturerName 1001 unsigned short manufacturerName; 1002 // 2 byte product code -> ELD.ProductCode 1003 unsigned short productCode; 1004 }; 1005 1006 1007 #ifdef CONFIG_DRM_AMD_DC_DSC_SUPPORT 1008 struct dc_sink_dsc_caps { 1009 // 'true' if these are virtual DPCD's DSC caps (immediately upstream of sink in MST topology), 1010 // 'false' if they are sink's DSC caps 1011 bool is_virtual_dpcd_dsc; 1012 struct dsc_dec_dpcd_caps dsc_dec_caps; 1013 }; 1014 #endif 1015 1016 /* 1017 * The sink structure contains EDID and other display device properties 1018 */ 1019 struct dc_sink { 1020 enum signal_type sink_signal; 1021 struct dc_edid dc_edid; /* raw edid */ 1022 struct dc_edid_caps edid_caps; /* parse display caps */ 1023 struct dc_container_id *dc_container_id; 1024 uint32_t dongle_max_pix_clk; 1025 void *priv; 1026 struct stereo_3d_features features_3d[TIMING_3D_FORMAT_MAX]; 1027 bool converter_disable_audio; 1028 1029 #ifdef CONFIG_DRM_AMD_DC_DSC_SUPPORT 1030 struct dc_sink_dsc_caps sink_dsc_caps; 1031 #endif 1032 1033 /* private to DC core */ 1034 struct dc_link *link; 1035 struct dc_context *ctx; 1036 1037 uint32_t sink_id; 1038 1039 /* private to dc_sink.c */ 1040 // refcount must be the last member in dc_sink, since we want the 1041 // sink structure to be logically cloneable up to (but not including) 1042 // refcount 1043 struct kref refcount; 1044 }; 1045 1046 void dc_sink_retain(struct dc_sink *sink); 1047 void dc_sink_release(struct dc_sink *sink); 1048 1049 struct dc_sink_init_data { 1050 enum signal_type sink_signal; 1051 struct dc_link *link; 1052 uint32_t dongle_max_pix_clk; 1053 bool converter_disable_audio; 1054 }; 1055 1056 struct dc_sink *dc_sink_create(const struct dc_sink_init_data *init_params); 1057 1058 /* Newer interfaces */ 1059 struct dc_cursor { 1060 struct dc_plane_address address; 1061 struct dc_cursor_attributes attributes; 1062 }; 1063 1064 1065 /******************************************************************************* 1066 * Interrupt interfaces 1067 ******************************************************************************/ 1068 enum dc_irq_source dc_interrupt_to_irq_source( 1069 struct dc *dc, 1070 uint32_t src_id, 1071 uint32_t ext_id); 1072 bool dc_interrupt_set(struct dc *dc, enum dc_irq_source src, bool enable); 1073 void dc_interrupt_ack(struct dc *dc, enum dc_irq_source src); 1074 enum dc_irq_source dc_get_hpd_irq_source_at_index( 1075 struct dc *dc, uint32_t link_index); 1076 1077 /******************************************************************************* 1078 * Power Interfaces 1079 ******************************************************************************/ 1080 1081 void dc_set_power_state( 1082 struct dc *dc, 1083 enum dc_acpi_cm_power_state power_state); 1084 void dc_resume(struct dc *dc); 1085 unsigned int dc_get_current_backlight_pwm(struct dc *dc); 1086 unsigned int dc_get_target_backlight_pwm(struct dc *dc); 1087 1088 bool dc_is_dmcu_initialized(struct dc *dc); 1089 1090 enum dc_status dc_set_clock(struct dc *dc, enum dc_clock_type clock_type, uint32_t clk_khz, uint32_t stepping); 1091 void dc_get_clock(struct dc *dc, enum dc_clock_type clock_type, struct dc_clock_config *clock_cfg); 1092 #if defined(CONFIG_DRM_AMD_DC_DSC_SUPPORT) 1093 /******************************************************************************* 1094 * DSC Interfaces 1095 ******************************************************************************/ 1096 #include "dc_dsc.h" 1097 #endif 1098 #endif /* DC_INTERFACE_H_ */ 1099