1 /* 2 * Copyright 2012-14 Advanced Micro Devices, Inc. 3 * 4 * Permission is hereby granted, free of charge, to any person obtaining a 5 * copy of this software and associated documentation files (the "Software"), 6 * to deal in the Software without restriction, including without limitation 7 * the rights to use, copy, modify, merge, publish, distribute, sublicense, 8 * and/or sell copies of the Software, and to permit persons to whom the 9 * Software is furnished to do so, subject to the following conditions: 10 * 11 * The above copyright notice and this permission notice shall be included in 12 * all copies or substantial portions of the Software. 13 * 14 * THE SOFTWARE IS PROVIDED "AS IS", WITHOUT WARRANTY OF ANY KIND, EXPRESS OR 15 * IMPLIED, INCLUDING BUT NOT LIMITED TO THE WARRANTIES OF MERCHANTABILITY, 16 * FITNESS FOR A PARTICULAR PURPOSE AND NONINFRINGEMENT. IN NO EVENT SHALL 17 * THE COPYRIGHT HOLDER(S) OR AUTHOR(S) BE LIABLE FOR ANY CLAIM, DAMAGES OR 18 * OTHER LIABILITY, WHETHER IN AN ACTION OF CONTRACT, TORT OR OTHERWISE, 19 * ARISING FROM, OUT OF OR IN CONNECTION WITH THE SOFTWARE OR THE USE OR 20 * OTHER DEALINGS IN THE SOFTWARE. 21 * 22 * Authors: AMD 23 * 24 */ 25 26 #ifndef DC_INTERFACE_H_ 27 #define DC_INTERFACE_H_ 28 29 #include "dc_types.h" 30 #include "grph_object_defs.h" 31 #include "logger_types.h" 32 #include "hdcp_msg_types.h" 33 #include "gpio_types.h" 34 #include "link_service_types.h" 35 #include "grph_object_ctrl_defs.h" 36 #include <inc/hw/opp.h> 37 38 #include "inc/hw_sequencer.h" 39 #include "inc/compressor.h" 40 #include "inc/hw/dmcu.h" 41 #include "dml/display_mode_lib.h" 42 43 /* forward declaration */ 44 struct aux_payload; 45 struct set_config_cmd_payload; 46 struct dmub_notification; 47 48 #define DC_VER "3.2.225" 49 50 #define MAX_SURFACES 3 51 #define MAX_PLANES 6 52 #define MAX_STREAMS 6 53 #define MIN_VIEWPORT_SIZE 12 54 #define MAX_NUM_EDP 2 55 56 /* Display Core Interfaces */ 57 struct dc_versions { 58 const char *dc_ver; 59 struct dmcu_version dmcu_version; 60 }; 61 62 enum dp_protocol_version { 63 DP_VERSION_1_4, 64 }; 65 66 enum dc_plane_type { 67 DC_PLANE_TYPE_INVALID, 68 DC_PLANE_TYPE_DCE_RGB, 69 DC_PLANE_TYPE_DCE_UNDERLAY, 70 DC_PLANE_TYPE_DCN_UNIVERSAL, 71 }; 72 73 // Sizes defined as multiples of 64KB 74 enum det_size { 75 DET_SIZE_DEFAULT = 0, 76 DET_SIZE_192KB = 3, 77 DET_SIZE_256KB = 4, 78 DET_SIZE_320KB = 5, 79 DET_SIZE_384KB = 6 80 }; 81 82 83 struct dc_plane_cap { 84 enum dc_plane_type type; 85 uint32_t blends_with_above : 1; 86 uint32_t blends_with_below : 1; 87 uint32_t per_pixel_alpha : 1; 88 struct { 89 uint32_t argb8888 : 1; 90 uint32_t nv12 : 1; 91 uint32_t fp16 : 1; 92 uint32_t p010 : 1; 93 uint32_t ayuv : 1; 94 } pixel_format_support; 95 // max upscaling factor x1000 96 // upscaling factors are always >= 1 97 // for example, 1080p -> 8K is 4.0, or 4000 raw value 98 struct { 99 uint32_t argb8888; 100 uint32_t nv12; 101 uint32_t fp16; 102 } max_upscale_factor; 103 // max downscale factor x1000 104 // downscale factors are always <= 1 105 // for example, 8K -> 1080p is 0.25, or 250 raw value 106 struct { 107 uint32_t argb8888; 108 uint32_t nv12; 109 uint32_t fp16; 110 } max_downscale_factor; 111 // minimal width/height 112 uint32_t min_width; 113 uint32_t min_height; 114 }; 115 116 /** 117 * DOC: color-management-caps 118 * 119 * **Color management caps (DPP and MPC)** 120 * 121 * Modules/color calculates various color operations which are translated to 122 * abstracted HW. DCE 5-12 had almost no important changes, but starting with 123 * DCN1, every new generation comes with fairly major differences in color 124 * pipeline. Therefore, we abstract color pipe capabilities so modules/DM can 125 * decide mapping to HW block based on logical capabilities. 126 */ 127 128 /** 129 * struct rom_curve_caps - predefined transfer function caps for degamma and regamma 130 * @srgb: RGB color space transfer func 131 * @bt2020: BT.2020 transfer func 132 * @gamma2_2: standard gamma 133 * @pq: perceptual quantizer transfer function 134 * @hlg: hybrid log–gamma transfer function 135 */ 136 struct rom_curve_caps { 137 uint16_t srgb : 1; 138 uint16_t bt2020 : 1; 139 uint16_t gamma2_2 : 1; 140 uint16_t pq : 1; 141 uint16_t hlg : 1; 142 }; 143 144 /** 145 * struct dpp_color_caps - color pipeline capabilities for display pipe and 146 * plane blocks 147 * 148 * @dcn_arch: all DCE generations treated the same 149 * @input_lut_shared: shared with DGAM. Input LUT is different than most LUTs, 150 * just plain 256-entry lookup 151 * @icsc: input color space conversion 152 * @dgam_ram: programmable degamma LUT 153 * @post_csc: post color space conversion, before gamut remap 154 * @gamma_corr: degamma correction 155 * @hw_3d_lut: 3D LUT support. It implies a shaper LUT before. It may be shared 156 * with MPC by setting mpc:shared_3d_lut flag 157 * @ogam_ram: programmable out/blend gamma LUT 158 * @ocsc: output color space conversion 159 * @dgam_rom_for_yuv: pre-defined degamma LUT for YUV planes 160 * @dgam_rom_caps: pre-definied curve caps for degamma 1D LUT 161 * @ogam_rom_caps: pre-definied curve caps for regamma 1D LUT 162 * 163 * Note: hdr_mult and gamut remap (CTM) are always available in DPP (in that order) 164 */ 165 struct dpp_color_caps { 166 uint16_t dcn_arch : 1; 167 uint16_t input_lut_shared : 1; 168 uint16_t icsc : 1; 169 uint16_t dgam_ram : 1; 170 uint16_t post_csc : 1; 171 uint16_t gamma_corr : 1; 172 uint16_t hw_3d_lut : 1; 173 uint16_t ogam_ram : 1; 174 uint16_t ocsc : 1; 175 uint16_t dgam_rom_for_yuv : 1; 176 struct rom_curve_caps dgam_rom_caps; 177 struct rom_curve_caps ogam_rom_caps; 178 }; 179 180 /** 181 * struct mpc_color_caps - color pipeline capabilities for multiple pipe and 182 * plane combined blocks 183 * 184 * @gamut_remap: color transformation matrix 185 * @ogam_ram: programmable out gamma LUT 186 * @ocsc: output color space conversion matrix 187 * @num_3dluts: MPC 3D LUT; always assumes a preceding shaper LUT 188 * @shared_3d_lut: shared 3D LUT flag. Can be either DPP or MPC, but single 189 * instance 190 * @ogam_rom_caps: pre-definied curve caps for regamma 1D LUT 191 */ 192 struct mpc_color_caps { 193 uint16_t gamut_remap : 1; 194 uint16_t ogam_ram : 1; 195 uint16_t ocsc : 1; 196 uint16_t num_3dluts : 3; 197 uint16_t shared_3d_lut:1; 198 struct rom_curve_caps ogam_rom_caps; 199 }; 200 201 /** 202 * struct dc_color_caps - color pipes capabilities for DPP and MPC hw blocks 203 * @dpp: color pipes caps for DPP 204 * @mpc: color pipes caps for MPC 205 */ 206 struct dc_color_caps { 207 struct dpp_color_caps dpp; 208 struct mpc_color_caps mpc; 209 }; 210 211 struct dc_dmub_caps { 212 bool psr; 213 bool mclk_sw; 214 }; 215 216 struct dc_caps { 217 uint32_t max_streams; 218 uint32_t max_links; 219 uint32_t max_audios; 220 uint32_t max_slave_planes; 221 uint32_t max_slave_yuv_planes; 222 uint32_t max_slave_rgb_planes; 223 uint32_t max_planes; 224 uint32_t max_downscale_ratio; 225 uint32_t i2c_speed_in_khz; 226 uint32_t i2c_speed_in_khz_hdcp; 227 uint32_t dmdata_alloc_size; 228 unsigned int max_cursor_size; 229 unsigned int max_video_width; 230 unsigned int min_horizontal_blanking_period; 231 int linear_pitch_alignment; 232 bool dcc_const_color; 233 bool dynamic_audio; 234 bool is_apu; 235 bool dual_link_dvi; 236 bool post_blend_color_processing; 237 bool force_dp_tps4_for_cp2520; 238 bool disable_dp_clk_share; 239 bool psp_setup_panel_mode; 240 bool extended_aux_timeout_support; 241 bool dmcub_support; 242 bool zstate_support; 243 uint32_t num_of_internal_disp; 244 enum dp_protocol_version max_dp_protocol_version; 245 unsigned int mall_size_per_mem_channel; 246 unsigned int mall_size_total; 247 unsigned int cursor_cache_size; 248 struct dc_plane_cap planes[MAX_PLANES]; 249 struct dc_color_caps color; 250 struct dc_dmub_caps dmub_caps; 251 bool dp_hpo; 252 bool dp_hdmi21_pcon_support; 253 bool edp_dsc_support; 254 bool vbios_lttpr_aware; 255 bool vbios_lttpr_enable; 256 uint32_t max_otg_num; 257 uint32_t max_cab_allocation_bytes; 258 uint32_t cache_line_size; 259 uint32_t cache_num_ways; 260 uint16_t subvp_fw_processing_delay_us; 261 uint8_t subvp_drr_max_vblank_margin_us; 262 uint16_t subvp_prefetch_end_to_mall_start_us; 263 uint8_t subvp_swath_height_margin_lines; // subvp start line must be aligned to 2 x swath height 264 uint16_t subvp_pstate_allow_width_us; 265 uint16_t subvp_vertical_int_margin_us; 266 bool seamless_odm; 267 uint8_t subvp_drr_vblank_start_margin_us; 268 }; 269 270 struct dc_bug_wa { 271 bool no_connect_phy_config; 272 bool dedcn20_305_wa; 273 bool skip_clock_update; 274 bool lt_early_cr_pattern; 275 }; 276 277 struct dc_dcc_surface_param { 278 struct dc_size surface_size; 279 enum surface_pixel_format format; 280 enum swizzle_mode_values swizzle_mode; 281 enum dc_scan_direction scan; 282 }; 283 284 struct dc_dcc_setting { 285 unsigned int max_compressed_blk_size; 286 unsigned int max_uncompressed_blk_size; 287 bool independent_64b_blks; 288 //These bitfields to be used starting with DCN 289 struct { 290 uint32_t dcc_256_64_64 : 1;//available in ASICs before DCN (the worst compression case) 291 uint32_t dcc_128_128_uncontrained : 1; //available in ASICs before DCN 292 uint32_t dcc_256_128_128 : 1; //available starting with DCN 293 uint32_t dcc_256_256_unconstrained : 1; //available in ASICs before DCN (the best compression case) 294 } dcc_controls; 295 }; 296 297 struct dc_surface_dcc_cap { 298 union { 299 struct { 300 struct dc_dcc_setting rgb; 301 } grph; 302 303 struct { 304 struct dc_dcc_setting luma; 305 struct dc_dcc_setting chroma; 306 } video; 307 }; 308 309 bool capable; 310 bool const_color_support; 311 }; 312 313 struct dc_static_screen_params { 314 struct { 315 bool force_trigger; 316 bool cursor_update; 317 bool surface_update; 318 bool overlay_update; 319 } triggers; 320 unsigned int num_frames; 321 }; 322 323 324 /* Surface update type is used by dc_update_surfaces_and_stream 325 * The update type is determined at the very beginning of the function based 326 * on parameters passed in and decides how much programming (or updating) is 327 * going to be done during the call. 328 * 329 * UPDATE_TYPE_FAST is used for really fast updates that do not require much 330 * logical calculations or hardware register programming. This update MUST be 331 * ISR safe on windows. Currently fast update will only be used to flip surface 332 * address. 333 * 334 * UPDATE_TYPE_MED is used for slower updates which require significant hw 335 * re-programming however do not affect bandwidth consumption or clock 336 * requirements. At present, this is the level at which front end updates 337 * that do not require us to run bw_calcs happen. These are in/out transfer func 338 * updates, viewport offset changes, recout size changes and pixel depth changes. 339 * This update can be done at ISR, but we want to minimize how often this happens. 340 * 341 * UPDATE_TYPE_FULL is slow. Really slow. This requires us to recalculate our 342 * bandwidth and clocks, possibly rearrange some pipes and reprogram anything front 343 * end related. Any time viewport dimensions, recout dimensions, scaling ratios or 344 * gamma need to be adjusted or pipe needs to be turned on (or disconnected) we do 345 * a full update. This cannot be done at ISR level and should be a rare event. 346 * Unless someone is stress testing mpo enter/exit, playing with colour or adjusting 347 * underscan we don't expect to see this call at all. 348 */ 349 350 enum surface_update_type { 351 UPDATE_TYPE_FAST, /* super fast, safe to execute in isr */ 352 UPDATE_TYPE_MED, /* ISR safe, most of programming needed, no bw/clk change*/ 353 UPDATE_TYPE_FULL, /* may need to shuffle resources */ 354 }; 355 356 /* Forward declaration*/ 357 struct dc; 358 struct dc_plane_state; 359 struct dc_state; 360 361 362 struct dc_cap_funcs { 363 bool (*get_dcc_compression_cap)(const struct dc *dc, 364 const struct dc_dcc_surface_param *input, 365 struct dc_surface_dcc_cap *output); 366 }; 367 368 struct link_training_settings; 369 370 union allow_lttpr_non_transparent_mode { 371 struct { 372 bool DP1_4A : 1; 373 bool DP2_0 : 1; 374 } bits; 375 unsigned char raw; 376 }; 377 378 /* Structure to hold configuration flags set by dm at dc creation. */ 379 struct dc_config { 380 bool gpu_vm_support; 381 bool disable_disp_pll_sharing; 382 bool fbc_support; 383 bool disable_fractional_pwm; 384 bool allow_seamless_boot_optimization; 385 bool seamless_boot_edp_requested; 386 bool edp_not_connected; 387 bool edp_no_power_sequencing; 388 bool force_enum_edp; 389 bool forced_clocks; 390 union allow_lttpr_non_transparent_mode allow_lttpr_non_transparent_mode; 391 bool multi_mon_pp_mclk_switch; 392 bool disable_dmcu; 393 bool enable_4to1MPC; 394 bool enable_windowed_mpo_odm; 395 bool forceHBR2CP2520; // Used for switching between test patterns TPS4 and CP2520 396 uint32_t allow_edp_hotplug_detection; 397 bool clamp_min_dcfclk; 398 uint64_t vblank_alignment_dto_params; 399 uint8_t vblank_alignment_max_frame_time_diff; 400 bool is_asymmetric_memory; 401 bool is_single_rank_dimm; 402 bool is_vmin_only_asic; 403 bool use_pipe_ctx_sync_logic; 404 bool ignore_dpref_ss; 405 bool enable_mipi_converter_optimization; 406 bool use_default_clock_table; 407 bool force_bios_enable_lttpr; 408 uint8_t force_bios_fixed_vs; 409 int sdpif_request_limit_words_per_umc; 410 bool disable_subvp_drr; 411 }; 412 413 enum visual_confirm { 414 VISUAL_CONFIRM_DISABLE = 0, 415 VISUAL_CONFIRM_SURFACE = 1, 416 VISUAL_CONFIRM_HDR = 2, 417 VISUAL_CONFIRM_MPCTREE = 4, 418 VISUAL_CONFIRM_PSR = 5, 419 VISUAL_CONFIRM_SWAPCHAIN = 6, 420 VISUAL_CONFIRM_FAMS = 7, 421 VISUAL_CONFIRM_SWIZZLE = 9, 422 VISUAL_CONFIRM_SUBVP = 14, 423 }; 424 425 enum dc_psr_power_opts { 426 psr_power_opt_invalid = 0x0, 427 psr_power_opt_smu_opt_static_screen = 0x1, 428 psr_power_opt_z10_static_screen = 0x10, 429 psr_power_opt_ds_disable_allow = 0x100, 430 }; 431 432 enum dml_hostvm_override_opts { 433 DML_HOSTVM_NO_OVERRIDE = 0x0, 434 DML_HOSTVM_OVERRIDE_FALSE = 0x1, 435 DML_HOSTVM_OVERRIDE_TRUE = 0x2, 436 }; 437 438 enum dcc_option { 439 DCC_ENABLE = 0, 440 DCC_DISABLE = 1, 441 DCC_HALF_REQ_DISALBE = 2, 442 }; 443 444 /** 445 * enum pipe_split_policy - Pipe split strategy supported by DCN 446 * 447 * This enum is used to define the pipe split policy supported by DCN. By 448 * default, DC favors MPC_SPLIT_DYNAMIC. 449 */ 450 enum pipe_split_policy { 451 /** 452 * @MPC_SPLIT_DYNAMIC: DC will automatically decide how to split the 453 * pipe in order to bring the best trade-off between performance and 454 * power consumption. This is the recommended option. 455 */ 456 MPC_SPLIT_DYNAMIC = 0, 457 458 /** 459 * @MPC_SPLIT_AVOID: Avoid pipe split, which means that DC will not 460 * try any sort of split optimization. 461 */ 462 MPC_SPLIT_AVOID = 1, 463 464 /** 465 * @MPC_SPLIT_AVOID_MULT_DISP: With this option, DC will only try to 466 * optimize the pipe utilization when using a single display; if the 467 * user connects to a second display, DC will avoid pipe split. 468 */ 469 MPC_SPLIT_AVOID_MULT_DISP = 2, 470 }; 471 472 enum wm_report_mode { 473 WM_REPORT_DEFAULT = 0, 474 WM_REPORT_OVERRIDE = 1, 475 }; 476 enum dtm_pstate{ 477 dtm_level_p0 = 0,/*highest voltage*/ 478 dtm_level_p1, 479 dtm_level_p2, 480 dtm_level_p3, 481 dtm_level_p4,/*when active_display_count = 0*/ 482 }; 483 484 enum dcn_pwr_state { 485 DCN_PWR_STATE_UNKNOWN = -1, 486 DCN_PWR_STATE_MISSION_MODE = 0, 487 DCN_PWR_STATE_LOW_POWER = 3, 488 }; 489 490 enum dcn_zstate_support_state { 491 DCN_ZSTATE_SUPPORT_UNKNOWN, 492 DCN_ZSTATE_SUPPORT_ALLOW, 493 DCN_ZSTATE_SUPPORT_ALLOW_Z8_ONLY, 494 DCN_ZSTATE_SUPPORT_ALLOW_Z8_Z10_ONLY, 495 DCN_ZSTATE_SUPPORT_ALLOW_Z10_ONLY, 496 DCN_ZSTATE_SUPPORT_DISALLOW, 497 }; 498 499 /** 500 * struct dc_clocks - DC pipe clocks 501 * 502 * For any clocks that may differ per pipe only the max is stored in this 503 * structure 504 */ 505 struct dc_clocks { 506 int dispclk_khz; 507 int actual_dispclk_khz; 508 int dppclk_khz; 509 int actual_dppclk_khz; 510 int disp_dpp_voltage_level_khz; 511 int dcfclk_khz; 512 int socclk_khz; 513 int dcfclk_deep_sleep_khz; 514 int fclk_khz; 515 int phyclk_khz; 516 int dramclk_khz; 517 bool p_state_change_support; 518 enum dcn_zstate_support_state zstate_support; 519 bool dtbclk_en; 520 int ref_dtbclk_khz; 521 bool fclk_p_state_change_support; 522 enum dcn_pwr_state pwr_state; 523 /* 524 * Elements below are not compared for the purposes of 525 * optimization required 526 */ 527 bool prev_p_state_change_support; 528 bool fclk_prev_p_state_change_support; 529 int num_ways; 530 531 /* 532 * @fw_based_mclk_switching 533 * 534 * DC has a mechanism that leverage the variable refresh rate to switch 535 * memory clock in cases that we have a large latency to achieve the 536 * memory clock change and a short vblank window. DC has some 537 * requirements to enable this feature, and this field describes if the 538 * system support or not such a feature. 539 */ 540 bool fw_based_mclk_switching; 541 bool fw_based_mclk_switching_shut_down; 542 int prev_num_ways; 543 enum dtm_pstate dtm_level; 544 int max_supported_dppclk_khz; 545 int max_supported_dispclk_khz; 546 int bw_dppclk_khz; /*a copy of dppclk_khz*/ 547 int bw_dispclk_khz; 548 }; 549 550 struct dc_bw_validation_profile { 551 bool enable; 552 553 unsigned long long total_ticks; 554 unsigned long long voltage_level_ticks; 555 unsigned long long watermark_ticks; 556 unsigned long long rq_dlg_ticks; 557 558 unsigned long long total_count; 559 unsigned long long skip_fast_count; 560 unsigned long long skip_pass_count; 561 unsigned long long skip_fail_count; 562 }; 563 564 #define BW_VAL_TRACE_SETUP() \ 565 unsigned long long end_tick = 0; \ 566 unsigned long long voltage_level_tick = 0; \ 567 unsigned long long watermark_tick = 0; \ 568 unsigned long long start_tick = dc->debug.bw_val_profile.enable ? \ 569 dm_get_timestamp(dc->ctx) : 0 570 571 #define BW_VAL_TRACE_COUNT() \ 572 if (dc->debug.bw_val_profile.enable) \ 573 dc->debug.bw_val_profile.total_count++ 574 575 #define BW_VAL_TRACE_SKIP(status) \ 576 if (dc->debug.bw_val_profile.enable) { \ 577 if (!voltage_level_tick) \ 578 voltage_level_tick = dm_get_timestamp(dc->ctx); \ 579 dc->debug.bw_val_profile.skip_ ## status ## _count++; \ 580 } 581 582 #define BW_VAL_TRACE_END_VOLTAGE_LEVEL() \ 583 if (dc->debug.bw_val_profile.enable) \ 584 voltage_level_tick = dm_get_timestamp(dc->ctx) 585 586 #define BW_VAL_TRACE_END_WATERMARKS() \ 587 if (dc->debug.bw_val_profile.enable) \ 588 watermark_tick = dm_get_timestamp(dc->ctx) 589 590 #define BW_VAL_TRACE_FINISH() \ 591 if (dc->debug.bw_val_profile.enable) { \ 592 end_tick = dm_get_timestamp(dc->ctx); \ 593 dc->debug.bw_val_profile.total_ticks += end_tick - start_tick; \ 594 dc->debug.bw_val_profile.voltage_level_ticks += voltage_level_tick - start_tick; \ 595 if (watermark_tick) { \ 596 dc->debug.bw_val_profile.watermark_ticks += watermark_tick - voltage_level_tick; \ 597 dc->debug.bw_val_profile.rq_dlg_ticks += end_tick - watermark_tick; \ 598 } \ 599 } 600 601 union mem_low_power_enable_options { 602 struct { 603 bool vga: 1; 604 bool i2c: 1; 605 bool dmcu: 1; 606 bool dscl: 1; 607 bool cm: 1; 608 bool mpc: 1; 609 bool optc: 1; 610 bool vpg: 1; 611 bool afmt: 1; 612 } bits; 613 uint32_t u32All; 614 }; 615 616 union root_clock_optimization_options { 617 struct { 618 bool dpp: 1; 619 bool dsc: 1; 620 bool hdmistream: 1; 621 bool hdmichar: 1; 622 bool dpstream: 1; 623 bool symclk32_se: 1; 624 bool symclk32_le: 1; 625 bool symclk_fe: 1; 626 bool physymclk: 1; 627 bool dpiasymclk: 1; 628 uint32_t reserved: 22; 629 } bits; 630 uint32_t u32All; 631 }; 632 633 union dpia_debug_options { 634 struct { 635 uint32_t disable_dpia:1; /* bit 0 */ 636 uint32_t force_non_lttpr:1; /* bit 1 */ 637 uint32_t extend_aux_rd_interval:1; /* bit 2 */ 638 uint32_t disable_mst_dsc_work_around:1; /* bit 3 */ 639 uint32_t enable_force_tbt3_work_around:1; /* bit 4 */ 640 uint32_t reserved:27; 641 } bits; 642 uint32_t raw; 643 }; 644 645 /* AUX wake work around options 646 * 0: enable/disable work around 647 * 1: use default timeout LINK_AUX_WAKE_TIMEOUT_MS 648 * 15-2: reserved 649 * 31-16: timeout in ms 650 */ 651 union aux_wake_wa_options { 652 struct { 653 uint32_t enable_wa : 1; 654 uint32_t use_default_timeout : 1; 655 uint32_t rsvd: 14; 656 uint32_t timeout_ms : 16; 657 } bits; 658 uint32_t raw; 659 }; 660 661 struct dc_debug_data { 662 uint32_t ltFailCount; 663 uint32_t i2cErrorCount; 664 uint32_t auxErrorCount; 665 }; 666 667 struct dc_phy_addr_space_config { 668 struct { 669 uint64_t start_addr; 670 uint64_t end_addr; 671 uint64_t fb_top; 672 uint64_t fb_offset; 673 uint64_t fb_base; 674 uint64_t agp_top; 675 uint64_t agp_bot; 676 uint64_t agp_base; 677 } system_aperture; 678 679 struct { 680 uint64_t page_table_start_addr; 681 uint64_t page_table_end_addr; 682 uint64_t page_table_base_addr; 683 bool base_addr_is_mc_addr; 684 } gart_config; 685 686 bool valid; 687 bool is_hvm_enabled; 688 uint64_t page_table_default_page_addr; 689 }; 690 691 struct dc_virtual_addr_space_config { 692 uint64_t page_table_base_addr; 693 uint64_t page_table_start_addr; 694 uint64_t page_table_end_addr; 695 uint32_t page_table_block_size_in_bytes; 696 uint8_t page_table_depth; // 1 = 1 level, 2 = 2 level, etc. 0 = invalid 697 }; 698 699 struct dc_bounding_box_overrides { 700 int sr_exit_time_ns; 701 int sr_enter_plus_exit_time_ns; 702 int urgent_latency_ns; 703 int percent_of_ideal_drambw; 704 int dram_clock_change_latency_ns; 705 int dummy_clock_change_latency_ns; 706 int fclk_clock_change_latency_ns; 707 /* This forces a hard min on the DCFCLK we use 708 * for DML. Unlike the debug option for forcing 709 * DCFCLK, this override affects watermark calculations 710 */ 711 int min_dcfclk_mhz; 712 }; 713 714 struct dc_state; 715 struct resource_pool; 716 struct dce_hwseq; 717 struct link_service; 718 719 /** 720 * struct dc_debug_options - DC debug struct 721 * 722 * This struct provides a simple mechanism for developers to change some 723 * configurations, enable/disable features, and activate extra debug options. 724 * This can be very handy to narrow down whether some specific feature is 725 * causing an issue or not. 726 */ 727 struct dc_debug_options { 728 bool native422_support; 729 bool disable_dsc; 730 enum visual_confirm visual_confirm; 731 int visual_confirm_rect_height; 732 733 bool sanity_checks; 734 bool max_disp_clk; 735 bool surface_trace; 736 bool timing_trace; 737 bool clock_trace; 738 bool validation_trace; 739 bool bandwidth_calcs_trace; 740 int max_downscale_src_width; 741 742 /* stutter efficiency related */ 743 bool disable_stutter; 744 bool use_max_lb; 745 enum dcc_option disable_dcc; 746 747 /** 748 * @pipe_split_policy: Define which pipe split policy is used by the 749 * display core. 750 */ 751 enum pipe_split_policy pipe_split_policy; 752 bool force_single_disp_pipe_split; 753 bool voltage_align_fclk; 754 bool disable_min_fclk; 755 756 bool disable_dfs_bypass; 757 bool disable_dpp_power_gate; 758 bool disable_hubp_power_gate; 759 bool disable_dsc_power_gate; 760 int dsc_min_slice_height_override; 761 int dsc_bpp_increment_div; 762 bool disable_pplib_wm_range; 763 enum wm_report_mode pplib_wm_report_mode; 764 unsigned int min_disp_clk_khz; 765 unsigned int min_dpp_clk_khz; 766 unsigned int min_dram_clk_khz; 767 int sr_exit_time_dpm0_ns; 768 int sr_enter_plus_exit_time_dpm0_ns; 769 int sr_exit_time_ns; 770 int sr_enter_plus_exit_time_ns; 771 int urgent_latency_ns; 772 uint32_t underflow_assert_delay_us; 773 int percent_of_ideal_drambw; 774 int dram_clock_change_latency_ns; 775 bool optimized_watermark; 776 int always_scale; 777 bool disable_pplib_clock_request; 778 bool disable_clock_gate; 779 bool disable_mem_low_power; 780 bool pstate_enabled; 781 bool disable_dmcu; 782 bool force_abm_enable; 783 bool disable_stereo_support; 784 bool vsr_support; 785 bool performance_trace; 786 bool az_endpoint_mute_only; 787 bool always_use_regamma; 788 bool recovery_enabled; 789 bool avoid_vbios_exec_table; 790 bool scl_reset_length10; 791 bool hdmi20_disable; 792 bool skip_detection_link_training; 793 uint32_t edid_read_retry_times; 794 unsigned int force_odm_combine; //bit vector based on otg inst 795 unsigned int seamless_boot_odm_combine; 796 unsigned int force_odm_combine_4to1; //bit vector based on otg inst 797 int minimum_z8_residency_time; 798 bool disable_z9_mpc; 799 unsigned int force_fclk_khz; 800 bool enable_tri_buf; 801 bool dmub_offload_enabled; 802 bool dmcub_emulation; 803 bool disable_idle_power_optimizations; 804 unsigned int mall_size_override; 805 unsigned int mall_additional_timer_percent; 806 bool mall_error_as_fatal; 807 bool dmub_command_table; /* for testing only */ 808 struct dc_bw_validation_profile bw_val_profile; 809 bool disable_fec; 810 bool disable_48mhz_pwrdwn; 811 /* This forces a hard min on the DCFCLK requested to SMU/PP 812 * watermarks are not affected. 813 */ 814 unsigned int force_min_dcfclk_mhz; 815 int dwb_fi_phase; 816 bool disable_timing_sync; 817 bool cm_in_bypass; 818 int force_clock_mode;/*every mode change.*/ 819 820 bool disable_dram_clock_change_vactive_support; 821 bool validate_dml_output; 822 bool enable_dmcub_surface_flip; 823 bool usbc_combo_phy_reset_wa; 824 bool enable_dram_clock_change_one_display_vactive; 825 /* TODO - remove once tested */ 826 bool legacy_dp2_lt; 827 bool set_mst_en_for_sst; 828 bool disable_uhbr; 829 bool force_dp2_lt_fallback_method; 830 bool ignore_cable_id; 831 union mem_low_power_enable_options enable_mem_low_power; 832 union root_clock_optimization_options root_clock_optimization; 833 bool hpo_optimization; 834 bool force_vblank_alignment; 835 836 /* Enable dmub aux for legacy ddc */ 837 bool enable_dmub_aux_for_legacy_ddc; 838 bool disable_fams; 839 /* FEC/PSR1 sequence enable delay in 100us */ 840 uint8_t fec_enable_delay_in100us; 841 bool enable_driver_sequence_debug; 842 enum det_size crb_alloc_policy; 843 int crb_alloc_policy_min_disp_count; 844 bool disable_z10; 845 bool enable_z9_disable_interface; 846 bool psr_skip_crtc_disable; 847 union dpia_debug_options dpia_debug; 848 bool disable_fixed_vs_aux_timeout_wa; 849 bool force_disable_subvp; 850 bool force_subvp_mclk_switch; 851 bool allow_sw_cursor_fallback; 852 unsigned int force_subvp_num_ways; 853 unsigned int force_mall_ss_num_ways; 854 bool alloc_extra_way_for_cursor; 855 uint32_t subvp_extra_lines; 856 bool force_usr_allow; 857 /* uses value at boot and disables switch */ 858 bool disable_dtb_ref_clk_switch; 859 uint32_t fixed_vs_aux_delay_config_wa; 860 bool extended_blank_optimization; 861 union aux_wake_wa_options aux_wake_wa; 862 uint32_t mst_start_top_delay; 863 uint8_t psr_power_use_phy_fsm; 864 enum dml_hostvm_override_opts dml_hostvm_override; 865 bool dml_disallow_alternate_prefetch_modes; 866 bool use_legacy_soc_bb_mechanism; 867 bool exit_idle_opt_for_cursor_updates; 868 bool enable_single_display_2to1_odm_policy; 869 bool enable_double_buffered_dsc_pg_support; 870 bool enable_dp_dig_pixel_rate_div_policy; 871 enum lttpr_mode lttpr_mode_override; 872 unsigned int dsc_delay_factor_wa_x1000; 873 unsigned int min_prefetch_in_strobe_ns; 874 bool disable_unbounded_requesting; 875 bool dig_fifo_off_in_blank; 876 bool temp_mst_deallocation_sequence; 877 bool override_dispclk_programming; 878 }; 879 880 struct gpu_info_soc_bounding_box_v1_0; 881 struct dc { 882 struct dc_debug_options debug; 883 struct dc_versions versions; 884 struct dc_caps caps; 885 struct dc_cap_funcs cap_funcs; 886 struct dc_config config; 887 struct dc_bounding_box_overrides bb_overrides; 888 struct dc_bug_wa work_arounds; 889 struct dc_context *ctx; 890 struct dc_phy_addr_space_config vm_pa_config; 891 892 uint8_t link_count; 893 struct dc_link *links[MAX_PIPES * 2]; 894 const struct link_service *link_srv; 895 896 struct dc_state *current_state; 897 struct resource_pool *res_pool; 898 899 struct clk_mgr *clk_mgr; 900 901 /* Display Engine Clock levels */ 902 struct dm_pp_clock_levels sclk_lvls; 903 904 /* Inputs into BW and WM calculations. */ 905 struct bw_calcs_dceip *bw_dceip; 906 struct bw_calcs_vbios *bw_vbios; 907 struct dcn_soc_bounding_box *dcn_soc; 908 struct dcn_ip_params *dcn_ip; 909 struct display_mode_lib dml; 910 911 /* HW functions */ 912 struct hw_sequencer_funcs hwss; 913 struct dce_hwseq *hwseq; 914 915 /* Require to optimize clocks and bandwidth for added/removed planes */ 916 bool optimized_required; 917 bool wm_optimized_required; 918 bool idle_optimizations_allowed; 919 bool enable_c20_dtm_b0; 920 921 /* Require to maintain clocks and bandwidth for UEFI enabled HW */ 922 923 /* FBC compressor */ 924 struct compressor *fbc_compressor; 925 926 struct dc_debug_data debug_data; 927 struct dpcd_vendor_signature vendor_signature; 928 929 const char *build_id; 930 struct vm_helper *vm_helper; 931 932 uint32_t *dcn_reg_offsets; 933 uint32_t *nbio_reg_offsets; 934 935 /* Scratch memory */ 936 struct { 937 struct { 938 /* 939 * For matching clock_limits table in driver with table 940 * from PMFW. 941 */ 942 struct _vcs_dpi_voltage_scaling_st clock_limits[DC__VOLTAGE_STATES]; 943 } update_bw_bounding_box; 944 } scratch; 945 }; 946 947 enum frame_buffer_mode { 948 FRAME_BUFFER_MODE_LOCAL_ONLY = 0, 949 FRAME_BUFFER_MODE_ZFB_ONLY, 950 FRAME_BUFFER_MODE_MIXED_ZFB_AND_LOCAL, 951 } ; 952 953 struct dchub_init_data { 954 int64_t zfb_phys_addr_base; 955 int64_t zfb_mc_base_addr; 956 uint64_t zfb_size_in_byte; 957 enum frame_buffer_mode fb_mode; 958 bool dchub_initialzied; 959 bool dchub_info_valid; 960 }; 961 962 struct dc_init_data { 963 struct hw_asic_id asic_id; 964 void *driver; /* ctx */ 965 struct cgs_device *cgs_device; 966 struct dc_bounding_box_overrides bb_overrides; 967 968 int num_virtual_links; 969 /* 970 * If 'vbios_override' not NULL, it will be called instead 971 * of the real VBIOS. Intended use is Diagnostics on FPGA. 972 */ 973 struct dc_bios *vbios_override; 974 enum dce_environment dce_environment; 975 976 struct dmub_offload_funcs *dmub_if; 977 struct dc_reg_helper_state *dmub_offload; 978 979 struct dc_config flags; 980 uint64_t log_mask; 981 982 struct dpcd_vendor_signature vendor_signature; 983 bool force_smu_not_present; 984 /* 985 * IP offset for run time initializaion of register addresses 986 * 987 * DCN3.5+ will fail dc_create() if these fields are null for them. They are 988 * applicable starting with DCN32/321 and are not used for ASICs upstreamed 989 * before them. 990 */ 991 uint32_t *dcn_reg_offsets; 992 uint32_t *nbio_reg_offsets; 993 }; 994 995 struct dc_callback_init { 996 struct cp_psp cp_psp; 997 }; 998 999 struct dc *dc_create(const struct dc_init_data *init_params); 1000 void dc_hardware_init(struct dc *dc); 1001 1002 int dc_get_vmid_use_vector(struct dc *dc); 1003 void dc_setup_vm_context(struct dc *dc, struct dc_virtual_addr_space_config *va_config, int vmid); 1004 /* Returns the number of vmids supported */ 1005 int dc_setup_system_context(struct dc *dc, struct dc_phy_addr_space_config *pa_config); 1006 void dc_init_callbacks(struct dc *dc, 1007 const struct dc_callback_init *init_params); 1008 void dc_deinit_callbacks(struct dc *dc); 1009 void dc_destroy(struct dc **dc); 1010 1011 /* Surface Interfaces */ 1012 1013 enum { 1014 TRANSFER_FUNC_POINTS = 1025 1015 }; 1016 1017 struct dc_hdr_static_metadata { 1018 /* display chromaticities and white point in units of 0.00001 */ 1019 unsigned int chromaticity_green_x; 1020 unsigned int chromaticity_green_y; 1021 unsigned int chromaticity_blue_x; 1022 unsigned int chromaticity_blue_y; 1023 unsigned int chromaticity_red_x; 1024 unsigned int chromaticity_red_y; 1025 unsigned int chromaticity_white_point_x; 1026 unsigned int chromaticity_white_point_y; 1027 1028 uint32_t min_luminance; 1029 uint32_t max_luminance; 1030 uint32_t maximum_content_light_level; 1031 uint32_t maximum_frame_average_light_level; 1032 }; 1033 1034 enum dc_transfer_func_type { 1035 TF_TYPE_PREDEFINED, 1036 TF_TYPE_DISTRIBUTED_POINTS, 1037 TF_TYPE_BYPASS, 1038 TF_TYPE_HWPWL 1039 }; 1040 1041 struct dc_transfer_func_distributed_points { 1042 struct fixed31_32 red[TRANSFER_FUNC_POINTS]; 1043 struct fixed31_32 green[TRANSFER_FUNC_POINTS]; 1044 struct fixed31_32 blue[TRANSFER_FUNC_POINTS]; 1045 1046 uint16_t end_exponent; 1047 uint16_t x_point_at_y1_red; 1048 uint16_t x_point_at_y1_green; 1049 uint16_t x_point_at_y1_blue; 1050 }; 1051 1052 enum dc_transfer_func_predefined { 1053 TRANSFER_FUNCTION_SRGB, 1054 TRANSFER_FUNCTION_BT709, 1055 TRANSFER_FUNCTION_PQ, 1056 TRANSFER_FUNCTION_LINEAR, 1057 TRANSFER_FUNCTION_UNITY, 1058 TRANSFER_FUNCTION_HLG, 1059 TRANSFER_FUNCTION_HLG12, 1060 TRANSFER_FUNCTION_GAMMA22, 1061 TRANSFER_FUNCTION_GAMMA24, 1062 TRANSFER_FUNCTION_GAMMA26 1063 }; 1064 1065 1066 struct dc_transfer_func { 1067 struct kref refcount; 1068 enum dc_transfer_func_type type; 1069 enum dc_transfer_func_predefined tf; 1070 /* FP16 1.0 reference level in nits, default is 80 nits, only for PQ*/ 1071 uint32_t sdr_ref_white_level; 1072 union { 1073 struct pwl_params pwl; 1074 struct dc_transfer_func_distributed_points tf_pts; 1075 }; 1076 }; 1077 1078 1079 union dc_3dlut_state { 1080 struct { 1081 uint32_t initialized:1; /*if 3dlut is went through color module for initialization */ 1082 uint32_t rmu_idx_valid:1; /*if mux settings are valid*/ 1083 uint32_t rmu_mux_num:3; /*index of mux to use*/ 1084 uint32_t mpc_rmu0_mux:4; /*select mpcc on mux, one of the following : mpcc0, mpcc1, mpcc2, mpcc3*/ 1085 uint32_t mpc_rmu1_mux:4; 1086 uint32_t mpc_rmu2_mux:4; 1087 uint32_t reserved:15; 1088 } bits; 1089 uint32_t raw; 1090 }; 1091 1092 1093 struct dc_3dlut { 1094 struct kref refcount; 1095 struct tetrahedral_params lut_3d; 1096 struct fixed31_32 hdr_multiplier; 1097 union dc_3dlut_state state; 1098 }; 1099 /* 1100 * This structure is filled in by dc_surface_get_status and contains 1101 * the last requested address and the currently active address so the called 1102 * can determine if there are any outstanding flips 1103 */ 1104 struct dc_plane_status { 1105 struct dc_plane_address requested_address; 1106 struct dc_plane_address current_address; 1107 bool is_flip_pending; 1108 bool is_right_eye; 1109 }; 1110 1111 union surface_update_flags { 1112 1113 struct { 1114 uint32_t addr_update:1; 1115 /* Medium updates */ 1116 uint32_t dcc_change:1; 1117 uint32_t color_space_change:1; 1118 uint32_t horizontal_mirror_change:1; 1119 uint32_t per_pixel_alpha_change:1; 1120 uint32_t global_alpha_change:1; 1121 uint32_t hdr_mult:1; 1122 uint32_t rotation_change:1; 1123 uint32_t swizzle_change:1; 1124 uint32_t scaling_change:1; 1125 uint32_t position_change:1; 1126 uint32_t in_transfer_func_change:1; 1127 uint32_t input_csc_change:1; 1128 uint32_t coeff_reduction_change:1; 1129 uint32_t output_tf_change:1; 1130 uint32_t pixel_format_change:1; 1131 uint32_t plane_size_change:1; 1132 uint32_t gamut_remap_change:1; 1133 1134 /* Full updates */ 1135 uint32_t new_plane:1; 1136 uint32_t bpp_change:1; 1137 uint32_t gamma_change:1; 1138 uint32_t bandwidth_change:1; 1139 uint32_t clock_change:1; 1140 uint32_t stereo_format_change:1; 1141 uint32_t lut_3d:1; 1142 uint32_t tmz_changed:1; 1143 uint32_t full_update:1; 1144 } bits; 1145 1146 uint32_t raw; 1147 }; 1148 1149 struct dc_plane_state { 1150 struct dc_plane_address address; 1151 struct dc_plane_flip_time time; 1152 bool triplebuffer_flips; 1153 struct scaling_taps scaling_quality; 1154 struct rect src_rect; 1155 struct rect dst_rect; 1156 struct rect clip_rect; 1157 1158 struct plane_size plane_size; 1159 union dc_tiling_info tiling_info; 1160 1161 struct dc_plane_dcc_param dcc; 1162 1163 struct dc_gamma *gamma_correction; 1164 struct dc_transfer_func *in_transfer_func; 1165 struct dc_bias_and_scale *bias_and_scale; 1166 struct dc_csc_transform input_csc_color_matrix; 1167 struct fixed31_32 coeff_reduction_factor; 1168 struct fixed31_32 hdr_mult; 1169 struct colorspace_transform gamut_remap_matrix; 1170 1171 // TODO: No longer used, remove 1172 struct dc_hdr_static_metadata hdr_static_ctx; 1173 1174 enum dc_color_space color_space; 1175 1176 struct dc_3dlut *lut3d_func; 1177 struct dc_transfer_func *in_shaper_func; 1178 struct dc_transfer_func *blend_tf; 1179 1180 struct dc_transfer_func *gamcor_tf; 1181 enum surface_pixel_format format; 1182 enum dc_rotation_angle rotation; 1183 enum plane_stereo_format stereo_format; 1184 1185 bool is_tiling_rotated; 1186 bool per_pixel_alpha; 1187 bool pre_multiplied_alpha; 1188 bool global_alpha; 1189 int global_alpha_value; 1190 bool visible; 1191 bool flip_immediate; 1192 bool horizontal_mirror; 1193 int layer_index; 1194 1195 union surface_update_flags update_flags; 1196 bool flip_int_enabled; 1197 bool skip_manual_trigger; 1198 1199 /* private to DC core */ 1200 struct dc_plane_status status; 1201 struct dc_context *ctx; 1202 1203 /* HACK: Workaround for forcing full reprogramming under some conditions */ 1204 bool force_full_update; 1205 1206 bool is_phantom; // TODO: Change mall_stream_config into mall_plane_config instead 1207 1208 /* private to dc_surface.c */ 1209 enum dc_irq_source irq_source; 1210 struct kref refcount; 1211 struct tg_color visual_confirm_color; 1212 1213 bool is_statically_allocated; 1214 }; 1215 1216 struct dc_plane_info { 1217 struct plane_size plane_size; 1218 union dc_tiling_info tiling_info; 1219 struct dc_plane_dcc_param dcc; 1220 enum surface_pixel_format format; 1221 enum dc_rotation_angle rotation; 1222 enum plane_stereo_format stereo_format; 1223 enum dc_color_space color_space; 1224 bool horizontal_mirror; 1225 bool visible; 1226 bool per_pixel_alpha; 1227 bool pre_multiplied_alpha; 1228 bool global_alpha; 1229 int global_alpha_value; 1230 bool input_csc_enabled; 1231 int layer_index; 1232 }; 1233 1234 struct dc_scaling_info { 1235 struct rect src_rect; 1236 struct rect dst_rect; 1237 struct rect clip_rect; 1238 struct scaling_taps scaling_quality; 1239 }; 1240 1241 struct dc_surface_update { 1242 struct dc_plane_state *surface; 1243 1244 /* isr safe update parameters. null means no updates */ 1245 const struct dc_flip_addrs *flip_addr; 1246 const struct dc_plane_info *plane_info; 1247 const struct dc_scaling_info *scaling_info; 1248 struct fixed31_32 hdr_mult; 1249 /* following updates require alloc/sleep/spin that is not isr safe, 1250 * null means no updates 1251 */ 1252 const struct dc_gamma *gamma; 1253 const struct dc_transfer_func *in_transfer_func; 1254 1255 const struct dc_csc_transform *input_csc_color_matrix; 1256 const struct fixed31_32 *coeff_reduction_factor; 1257 const struct dc_transfer_func *func_shaper; 1258 const struct dc_3dlut *lut3d_func; 1259 const struct dc_transfer_func *blend_tf; 1260 const struct colorspace_transform *gamut_remap_matrix; 1261 }; 1262 1263 /* 1264 * Create a new surface with default parameters; 1265 */ 1266 struct dc_plane_state *dc_create_plane_state(struct dc *dc); 1267 const struct dc_plane_status *dc_plane_get_status( 1268 const struct dc_plane_state *plane_state); 1269 1270 void dc_plane_state_retain(struct dc_plane_state *plane_state); 1271 void dc_plane_state_release(struct dc_plane_state *plane_state); 1272 1273 void dc_gamma_retain(struct dc_gamma *dc_gamma); 1274 void dc_gamma_release(struct dc_gamma **dc_gamma); 1275 struct dc_gamma *dc_create_gamma(void); 1276 1277 void dc_transfer_func_retain(struct dc_transfer_func *dc_tf); 1278 void dc_transfer_func_release(struct dc_transfer_func *dc_tf); 1279 struct dc_transfer_func *dc_create_transfer_func(void); 1280 1281 struct dc_3dlut *dc_create_3dlut_func(void); 1282 void dc_3dlut_func_release(struct dc_3dlut *lut); 1283 void dc_3dlut_func_retain(struct dc_3dlut *lut); 1284 1285 void dc_post_update_surfaces_to_stream( 1286 struct dc *dc); 1287 1288 #include "dc_stream.h" 1289 1290 /** 1291 * struct dc_validation_set - Struct to store surface/stream associations for validation 1292 */ 1293 struct dc_validation_set { 1294 /** 1295 * @stream: Stream state properties 1296 */ 1297 struct dc_stream_state *stream; 1298 1299 /** 1300 * @plane_state: Surface state 1301 */ 1302 struct dc_plane_state *plane_states[MAX_SURFACES]; 1303 1304 /** 1305 * @plane_count: Total of active planes 1306 */ 1307 uint8_t plane_count; 1308 }; 1309 1310 bool dc_validate_boot_timing(const struct dc *dc, 1311 const struct dc_sink *sink, 1312 struct dc_crtc_timing *crtc_timing); 1313 1314 enum dc_status dc_validate_plane(struct dc *dc, const struct dc_plane_state *plane_state); 1315 1316 void get_clock_requirements_for_state(struct dc_state *state, struct AsicStateEx *info); 1317 1318 enum dc_status dc_validate_with_context(struct dc *dc, 1319 const struct dc_validation_set set[], 1320 int set_count, 1321 struct dc_state *context, 1322 bool fast_validate); 1323 1324 bool dc_set_generic_gpio_for_stereo(bool enable, 1325 struct gpio_service *gpio_service); 1326 1327 /* 1328 * fast_validate: we return after determining if we can support the new state, 1329 * but before we populate the programming info 1330 */ 1331 enum dc_status dc_validate_global_state( 1332 struct dc *dc, 1333 struct dc_state *new_ctx, 1334 bool fast_validate); 1335 1336 1337 void dc_resource_state_construct( 1338 const struct dc *dc, 1339 struct dc_state *dst_ctx); 1340 1341 bool dc_acquire_release_mpc_3dlut( 1342 struct dc *dc, bool acquire, 1343 struct dc_stream_state *stream, 1344 struct dc_3dlut **lut, 1345 struct dc_transfer_func **shaper); 1346 1347 void dc_resource_state_copy_construct( 1348 const struct dc_state *src_ctx, 1349 struct dc_state *dst_ctx); 1350 1351 void dc_resource_state_copy_construct_current( 1352 const struct dc *dc, 1353 struct dc_state *dst_ctx); 1354 1355 void dc_resource_state_destruct(struct dc_state *context); 1356 1357 bool dc_resource_is_dsc_encoding_supported(const struct dc *dc); 1358 1359 enum dc_status dc_commit_streams(struct dc *dc, 1360 struct dc_stream_state *streams[], 1361 uint8_t stream_count); 1362 1363 /* TODO: When the transition to the new commit sequence is done, remove this 1364 * function in favor of dc_commit_streams. */ 1365 bool dc_commit_state(struct dc *dc, struct dc_state *context); 1366 1367 struct dc_state *dc_create_state(struct dc *dc); 1368 struct dc_state *dc_copy_state(struct dc_state *src_ctx); 1369 void dc_retain_state(struct dc_state *context); 1370 void dc_release_state(struct dc_state *context); 1371 1372 struct dc_plane_state *dc_get_surface_for_mpcc(struct dc *dc, 1373 struct dc_stream_state *stream, 1374 int mpcc_inst); 1375 1376 1377 uint32_t dc_get_opp_for_plane(struct dc *dc, struct dc_plane_state *plane); 1378 1379 /* Link Interfaces */ 1380 /* 1381 * A link contains one or more sinks and their connected status. 1382 * The currently active signal type (HDMI, DP-SST, DP-MST) is also reported. 1383 */ 1384 struct dc_link { 1385 struct dc_sink *remote_sinks[MAX_SINKS_PER_LINK]; 1386 unsigned int sink_count; 1387 struct dc_sink *local_sink; 1388 unsigned int link_index; 1389 enum dc_connection_type type; 1390 enum signal_type connector_signal; 1391 enum dc_irq_source irq_source_hpd; 1392 enum dc_irq_source irq_source_hpd_rx;/* aka DP Short Pulse */ 1393 1394 bool is_hpd_filter_disabled; 1395 bool dp_ss_off; 1396 1397 /** 1398 * @link_state_valid: 1399 * 1400 * If there is no link and local sink, this variable should be set to 1401 * false. Otherwise, it should be set to true; usually, the function 1402 * core_link_enable_stream sets this field to true. 1403 */ 1404 bool link_state_valid; 1405 bool aux_access_disabled; 1406 bool sync_lt_in_progress; 1407 bool skip_stream_reenable; 1408 bool is_internal_display; 1409 /** @todo Rename. Flag an endpoint as having a programmable mapping to a DIG encoder. */ 1410 bool is_dig_mapping_flexible; 1411 bool hpd_status; /* HPD status of link without physical HPD pin. */ 1412 bool is_hpd_pending; /* Indicates a new received hpd */ 1413 bool is_automated; /* Indicates automated testing */ 1414 1415 bool edp_sink_present; 1416 1417 struct dp_trace dp_trace; 1418 1419 /* caps is the same as reported_link_cap. link_traing use 1420 * reported_link_cap. Will clean up. TODO 1421 */ 1422 struct dc_link_settings reported_link_cap; 1423 struct dc_link_settings verified_link_cap; 1424 struct dc_link_settings cur_link_settings; 1425 struct dc_lane_settings cur_lane_setting[LANE_COUNT_DP_MAX]; 1426 struct dc_link_settings preferred_link_setting; 1427 /* preferred_training_settings are override values that 1428 * come from DM. DM is responsible for the memory 1429 * management of the override pointers. 1430 */ 1431 struct dc_link_training_overrides preferred_training_settings; 1432 struct dp_audio_test_data audio_test_data; 1433 1434 uint8_t ddc_hw_inst; 1435 1436 uint8_t hpd_src; 1437 1438 uint8_t link_enc_hw_inst; 1439 /* DIG link encoder ID. Used as index in link encoder resource pool. 1440 * For links with fixed mapping to DIG, this is not changed after dc_link 1441 * object creation. 1442 */ 1443 enum engine_id eng_id; 1444 1445 bool test_pattern_enabled; 1446 union compliance_test_state compliance_test_state; 1447 1448 void *priv; 1449 1450 struct ddc_service *ddc; 1451 1452 bool aux_mode; 1453 1454 /* Private to DC core */ 1455 1456 const struct dc *dc; 1457 1458 struct dc_context *ctx; 1459 1460 struct panel_cntl *panel_cntl; 1461 struct link_encoder *link_enc; 1462 struct graphics_object_id link_id; 1463 /* Endpoint type distinguishes display endpoints which do not have entries 1464 * in the BIOS connector table from those that do. Helps when tracking link 1465 * encoder to display endpoint assignments. 1466 */ 1467 enum display_endpoint_type ep_type; 1468 union ddi_channel_mapping ddi_channel_mapping; 1469 struct connector_device_tag_info device_tag; 1470 struct dpcd_caps dpcd_caps; 1471 uint32_t dongle_max_pix_clk; 1472 unsigned short chip_caps; 1473 unsigned int dpcd_sink_count; 1474 struct hdcp_caps hdcp_caps; 1475 enum edp_revision edp_revision; 1476 union dpcd_sink_ext_caps dpcd_sink_ext_caps; 1477 1478 struct psr_settings psr_settings; 1479 1480 /* Drive settings read from integrated info table */ 1481 struct dc_lane_settings bios_forced_drive_settings; 1482 1483 /* Vendor specific LTTPR workaround variables */ 1484 uint8_t vendor_specific_lttpr_link_rate_wa; 1485 bool apply_vendor_specific_lttpr_link_rate_wa; 1486 1487 /* MST record stream using this link */ 1488 struct link_flags { 1489 bool dp_keep_receiver_powered; 1490 bool dp_skip_DID2; 1491 bool dp_skip_reset_segment; 1492 bool dp_skip_fs_144hz; 1493 bool dp_mot_reset_segment; 1494 /* Some USB4 docks do not handle turning off MST DSC once it has been enabled. */ 1495 bool dpia_mst_dsc_always_on; 1496 /* Forced DPIA into TBT3 compatibility mode. */ 1497 bool dpia_forced_tbt3_mode; 1498 bool dongle_mode_timing_override; 1499 } wa_flags; 1500 struct link_mst_stream_allocation_table mst_stream_alloc_table; 1501 1502 struct dc_link_status link_status; 1503 struct dprx_states dprx_states; 1504 1505 struct gpio *hpd_gpio; 1506 enum dc_link_fec_state fec_state; 1507 bool link_powered_externally; // Used to bypass hardware sequencing delays when panel is powered down forcibly 1508 1509 struct dc_panel_config panel_config; 1510 struct phy_state phy_state; 1511 // BW ALLOCATON USB4 ONLY 1512 struct dc_dpia_bw_alloc dpia_bw_alloc_config; 1513 }; 1514 1515 /* Return an enumerated dc_link. 1516 * dc_link order is constant and determined at 1517 * boot time. They cannot be created or destroyed. 1518 * Use dc_get_caps() to get number of links. 1519 */ 1520 struct dc_link *dc_get_link_at_index(struct dc *dc, uint32_t link_index); 1521 1522 /* Return instance id of the edp link. Inst 0 is primary edp link. */ 1523 bool dc_get_edp_link_panel_inst(const struct dc *dc, 1524 const struct dc_link *link, 1525 unsigned int *inst_out); 1526 1527 /* Return an array of link pointers to edp links. */ 1528 void dc_get_edp_links(const struct dc *dc, 1529 struct dc_link **edp_links, 1530 int *edp_num); 1531 1532 /* The function initiates detection handshake over the given link. It first 1533 * determines if there are display connections over the link. If so it initiates 1534 * detection protocols supported by the connected receiver device. The function 1535 * contains protocol specific handshake sequences which are sometimes mandatory 1536 * to establish a proper connection between TX and RX. So it is always 1537 * recommended to call this function as the first link operation upon HPD event 1538 * or power up event. Upon completion, the function will update link structure 1539 * in place based on latest RX capabilities. The function may also cause dpms 1540 * to be reset to off for all currently enabled streams to the link. It is DM's 1541 * responsibility to serialize detection and DPMS updates. 1542 * 1543 * @reason - Indicate which event triggers this detection. dc may customize 1544 * detection flow depending on the triggering events. 1545 * return false - if detection is not fully completed. This could happen when 1546 * there is an unrecoverable error during detection or detection is partially 1547 * completed (detection has been delegated to dm mst manager ie. 1548 * link->connection_type == dc_connection_mst_branch when returning false). 1549 * return true - detection is completed, link has been fully updated with latest 1550 * detection result. 1551 */ 1552 bool dc_link_detect(struct dc_link *link, enum dc_detect_reason reason); 1553 1554 struct dc_sink_init_data; 1555 1556 /* When link connection type is dc_connection_mst_branch, remote sink can be 1557 * added to the link. The interface creates a remote sink and associates it with 1558 * current link. The sink will be retained by link until remove remote sink is 1559 * called. 1560 * 1561 * @dc_link - link the remote sink will be added to. 1562 * @edid - byte array of EDID raw data. 1563 * @len - size of the edid in byte 1564 * @init_data - 1565 */ 1566 struct dc_sink *dc_link_add_remote_sink( 1567 struct dc_link *dc_link, 1568 const uint8_t *edid, 1569 int len, 1570 struct dc_sink_init_data *init_data); 1571 1572 /* Remove remote sink from a link with dc_connection_mst_branch connection type. 1573 * @link - link the sink should be removed from 1574 * @sink - sink to be removed. 1575 */ 1576 void dc_link_remove_remote_sink( 1577 struct dc_link *link, 1578 struct dc_sink *sink); 1579 1580 /* Enable HPD interrupt handler for a given link */ 1581 void dc_link_enable_hpd(const struct dc_link *link); 1582 1583 /* Disable HPD interrupt handler for a given link */ 1584 void dc_link_disable_hpd(const struct dc_link *link); 1585 1586 /* determine if there is a sink connected to the link 1587 * 1588 * @type - dc_connection_single if connected, dc_connection_none otherwise. 1589 * return - false if an unexpected error occurs, true otherwise. 1590 * 1591 * NOTE: This function doesn't detect downstream sink connections i.e 1592 * dc_connection_mst_branch, dc_connection_sst_branch. In this case, it will 1593 * return dc_connection_single if the branch device is connected despite of 1594 * downstream sink's connection status. 1595 */ 1596 bool dc_link_detect_connection_type(struct dc_link *link, 1597 enum dc_connection_type *type); 1598 1599 /* query current hpd pin value 1600 * return - true HPD is asserted (HPD high), false otherwise (HPD low) 1601 * 1602 */ 1603 bool dc_link_get_hpd_state(struct dc_link *link); 1604 1605 /* Getter for cached link status from given link */ 1606 const struct dc_link_status *dc_link_get_status(const struct dc_link *link); 1607 1608 /* enable/disable hardware HPD filter. 1609 * 1610 * @link - The link the HPD pin is associated with. 1611 * @enable = true - enable hardware HPD filter. HPD event will only queued to irq 1612 * handler once after no HPD change has been detected within dc default HPD 1613 * filtering interval since last HPD event. i.e if display keeps toggling hpd 1614 * pulses within default HPD interval, no HPD event will be received until HPD 1615 * toggles have stopped. Then HPD event will be queued to irq handler once after 1616 * dc default HPD filtering interval since last HPD event. 1617 * 1618 * @enable = false - disable hardware HPD filter. HPD event will be queued 1619 * immediately to irq handler after no HPD change has been detected within 1620 * IRQ_HPD (aka HPD short pulse) interval (i.e 2ms). 1621 */ 1622 void dc_link_enable_hpd_filter(struct dc_link *link, bool enable); 1623 1624 /* submit i2c read/write payloads through ddc channel 1625 * @link_index - index to a link with ddc in i2c mode 1626 * @cmd - i2c command structure 1627 * return - true if success, false otherwise. 1628 */ 1629 bool dc_submit_i2c( 1630 struct dc *dc, 1631 uint32_t link_index, 1632 struct i2c_command *cmd); 1633 1634 /* submit i2c read/write payloads through oem channel 1635 * @link_index - index to a link with ddc in i2c mode 1636 * @cmd - i2c command structure 1637 * return - true if success, false otherwise. 1638 */ 1639 bool dc_submit_i2c_oem( 1640 struct dc *dc, 1641 struct i2c_command *cmd); 1642 1643 enum aux_return_code_type; 1644 /* Attempt to transfer the given aux payload. This function does not perform 1645 * retries or handle error states. The reply is returned in the payload->reply 1646 * and the result through operation_result. Returns the number of bytes 1647 * transferred,or -1 on a failure. 1648 */ 1649 int dc_link_aux_transfer_raw(struct ddc_service *ddc, 1650 struct aux_payload *payload, 1651 enum aux_return_code_type *operation_result); 1652 1653 bool dc_is_oem_i2c_device_present( 1654 struct dc *dc, 1655 size_t slave_address 1656 ); 1657 1658 /* return true if the connected receiver supports the hdcp version */ 1659 bool dc_link_is_hdcp14(struct dc_link *link, enum signal_type signal); 1660 bool dc_link_is_hdcp22(struct dc_link *link, enum signal_type signal); 1661 1662 /* Notify DC about DP RX Interrupt (aka DP IRQ_HPD). 1663 * 1664 * TODO - When defer_handling is true the function will have a different purpose. 1665 * It no longer does complete hpd rx irq handling. We should create a separate 1666 * interface specifically for this case. 1667 * 1668 * Return: 1669 * true - Downstream port status changed. DM should call DC to do the 1670 * detection. 1671 * false - no change in Downstream port status. No further action required 1672 * from DM. 1673 */ 1674 bool dc_link_handle_hpd_rx_irq(struct dc_link *dc_link, 1675 union hpd_irq_data *hpd_irq_dpcd_data, bool *out_link_loss, 1676 bool defer_handling, bool *has_left_work); 1677 /* handle DP specs define test automation sequence*/ 1678 void dc_link_dp_handle_automated_test(struct dc_link *link); 1679 1680 /* handle DP Link loss sequence and try to recover RX link loss with best 1681 * effort 1682 */ 1683 void dc_link_dp_handle_link_loss(struct dc_link *link); 1684 1685 /* Determine if hpd rx irq should be handled or ignored 1686 * return true - hpd rx irq should be handled. 1687 * return false - it is safe to ignore hpd rx irq event 1688 */ 1689 bool dc_link_dp_allow_hpd_rx_irq(const struct dc_link *link); 1690 1691 /* Determine if link loss is indicated with a given hpd_irq_dpcd_data. 1692 * @link - link the hpd irq data associated with 1693 * @hpd_irq_dpcd_data - input hpd irq data 1694 * return - true if hpd irq data indicates a link lost 1695 */ 1696 bool dc_link_check_link_loss_status(struct dc_link *link, 1697 union hpd_irq_data *hpd_irq_dpcd_data); 1698 1699 /* Read hpd rx irq data from a given link 1700 * @link - link where the hpd irq data should be read from 1701 * @irq_data - output hpd irq data 1702 * return - DC_OK if hpd irq data is read successfully, otherwise hpd irq data 1703 * read has failed. 1704 */ 1705 enum dc_status dc_link_dp_read_hpd_rx_irq_data( 1706 struct dc_link *link, 1707 union hpd_irq_data *irq_data); 1708 1709 /* The function clears recorded DP RX states in the link. DM should call this 1710 * function when it is resuming from S3 power state to previously connected links. 1711 * 1712 * TODO - in the future we should consider to expand link resume interface to 1713 * support clearing previous rx states. So we don't have to rely on dm to call 1714 * this interface explicitly. 1715 */ 1716 void dc_link_clear_dprx_states(struct dc_link *link); 1717 1718 /* Destruct the mst topology of the link and reset the allocated payload table 1719 * 1720 * NOTE: this should only be called if DM chooses not to call dc_link_detect but 1721 * still wants to reset MST topology on an unplug event */ 1722 bool dc_link_reset_cur_dp_mst_topology(struct dc_link *link); 1723 1724 /* The function calculates effective DP link bandwidth when a given link is 1725 * using the given link settings. 1726 * 1727 * return - total effective link bandwidth in kbps. 1728 */ 1729 uint32_t dc_link_bandwidth_kbps( 1730 const struct dc_link *link, 1731 const struct dc_link_settings *link_setting); 1732 1733 /* The function returns minimum bandwidth required to drive a given timing 1734 * return - minimum required timing bandwidth in kbps. 1735 */ 1736 uint32_t dc_bandwidth_in_kbps_from_timing( 1737 const struct dc_crtc_timing *timing); 1738 1739 /* The function takes a snapshot of current link resource allocation state 1740 * @dc: pointer to dc of the dm calling this 1741 * @map: a dc link resource snapshot defined internally to dc. 1742 * 1743 * DM needs to capture a snapshot of current link resource allocation mapping 1744 * and store it in its persistent storage. 1745 * 1746 * Some of the link resource is using first come first serve policy. 1747 * The allocation mapping depends on original hotplug order. This information 1748 * is lost after driver is loaded next time. The snapshot is used in order to 1749 * restore link resource to its previous state so user will get consistent 1750 * link capability allocation across reboot. 1751 * 1752 */ 1753 void dc_get_cur_link_res_map(const struct dc *dc, uint32_t *map); 1754 1755 /* This function restores link resource allocation state from a snapshot 1756 * @dc: pointer to dc of the dm calling this 1757 * @map: a dc link resource snapshot defined internally to dc. 1758 * 1759 * DM needs to call this function after initial link detection on boot and 1760 * before first commit streams to restore link resource allocation state 1761 * from previous boot session. 1762 * 1763 * Some of the link resource is using first come first serve policy. 1764 * The allocation mapping depends on original hotplug order. This information 1765 * is lost after driver is loaded next time. The snapshot is used in order to 1766 * restore link resource to its previous state so user will get consistent 1767 * link capability allocation across reboot. 1768 * 1769 */ 1770 void dc_restore_link_res_map(const struct dc *dc, uint32_t *map); 1771 1772 /* TODO: this is not meant to be exposed to DM. Should switch to stream update 1773 * interface i.e stream_update->dsc_config 1774 */ 1775 bool dc_link_update_dsc_config(struct pipe_ctx *pipe_ctx); 1776 1777 /* translate a raw link rate data to bandwidth in kbps */ 1778 uint32_t dc_link_bw_kbps_from_raw_frl_link_rate_data( 1779 struct dc *dc, uint8_t bw); 1780 1781 /* determine the optimal bandwidth given link and required bw. 1782 * @link - current detected link 1783 * @req_bw - requested bandwidth in kbps 1784 * @link_settings - returned most optimal link settings that can fit the 1785 * requested bandwidth 1786 * return - false if link can't support requested bandwidth, true if link 1787 * settings is found. 1788 */ 1789 bool dc_link_decide_edp_link_settings(struct dc_link *link, 1790 struct dc_link_settings *link_settings, 1791 uint32_t req_bw); 1792 1793 /* return the max dp link settings can be driven by the link without considering 1794 * connected RX device and its capability 1795 */ 1796 bool dc_link_dp_get_max_link_enc_cap(const struct dc_link *link, 1797 struct dc_link_settings *max_link_enc_cap); 1798 1799 /* determine when the link is driving MST mode, what DP link channel coding 1800 * format will be used. The decision will remain unchanged until next HPD event. 1801 * 1802 * @link - a link with DP RX connection 1803 * return - if stream is committed to this link with MST signal type, type of 1804 * channel coding format dc will choose. 1805 */ 1806 enum dp_link_encoding dc_link_dp_mst_decide_link_encoding_format( 1807 const struct dc_link *link); 1808 1809 /* get max dp link settings the link can enable with all things considered. (i.e 1810 * TX/RX/Cable capabilities and dp override policies. 1811 * 1812 * @link - a link with DP RX connection 1813 * return - max dp link settings the link can enable. 1814 * 1815 */ 1816 const struct dc_link_settings *dc_link_get_link_cap(const struct dc_link *link); 1817 1818 /* Check if a RX (ex. DP sink, MST hub, passive or active dongle) is connected 1819 * to a link with dp connector signal type. 1820 * @link - a link with dp connector signal type 1821 * return - true if connected, false otherwise 1822 */ 1823 bool dc_link_is_dp_sink_present(struct dc_link *link); 1824 1825 /* Force DP lane settings update to main-link video signal and notify the change 1826 * to DP RX via DPCD. This is a debug interface used for video signal integrity 1827 * tuning purpose. The interface assumes link has already been enabled with DP 1828 * signal. 1829 * 1830 * @lt_settings - a container structure with desired hw_lane_settings 1831 */ 1832 void dc_link_set_drive_settings(struct dc *dc, 1833 struct link_training_settings *lt_settings, 1834 struct dc_link *link); 1835 1836 /* Enable a test pattern in Link or PHY layer in an active link for compliance 1837 * test or debugging purpose. The test pattern will remain until next un-plug. 1838 * 1839 * @link - active link with DP signal output enabled. 1840 * @test_pattern - desired test pattern to output. 1841 * NOTE: set to DP_TEST_PATTERN_VIDEO_MODE to disable previous test pattern. 1842 * @test_pattern_color_space - for video test pattern choose a desired color 1843 * space. 1844 * @p_link_settings - For PHY pattern choose a desired link settings 1845 * @p_custom_pattern - some test pattern will require a custom input to 1846 * customize some pattern details. Otherwise keep it to NULL. 1847 * @cust_pattern_size - size of the custom pattern input. 1848 * 1849 */ 1850 bool dc_link_dp_set_test_pattern( 1851 struct dc_link *link, 1852 enum dp_test_pattern test_pattern, 1853 enum dp_test_pattern_color_space test_pattern_color_space, 1854 const struct link_training_settings *p_link_settings, 1855 const unsigned char *p_custom_pattern, 1856 unsigned int cust_pattern_size); 1857 1858 /* Force DP link settings to always use a specific value until reboot to a 1859 * specific link. If link has already been enabled, the interface will also 1860 * switch to desired link settings immediately. This is a debug interface to 1861 * generic dp issue trouble shooting. 1862 */ 1863 void dc_link_set_preferred_link_settings(struct dc *dc, 1864 struct dc_link_settings *link_setting, 1865 struct dc_link *link); 1866 1867 /* Force DP link to customize a specific link training behavior by overriding to 1868 * standard DP specs defined protocol. This is a debug interface to trouble shoot 1869 * display specific link training issues or apply some display specific 1870 * workaround in link training. 1871 * 1872 * @link_settings - if not NULL, force preferred link settings to the link. 1873 * @lt_override - a set of override pointers. If any pointer is none NULL, dc 1874 * will apply this particular override in future link training. If NULL is 1875 * passed in, dc resets previous overrides. 1876 * NOTE: DM must keep the memory from override pointers until DM resets preferred 1877 * training settings. 1878 */ 1879 void dc_link_set_preferred_training_settings(struct dc *dc, 1880 struct dc_link_settings *link_setting, 1881 struct dc_link_training_overrides *lt_overrides, 1882 struct dc_link *link, 1883 bool skip_immediate_retrain); 1884 1885 /* return - true if FEC is supported with connected DP RX, false otherwise */ 1886 bool dc_link_is_fec_supported(const struct dc_link *link); 1887 1888 /* query FEC enablement policy to determine if FEC will be enabled by dc during 1889 * link enablement. 1890 * return - true if FEC should be enabled, false otherwise. 1891 */ 1892 bool dc_link_should_enable_fec(const struct dc_link *link); 1893 1894 /* determine lttpr mode the current link should be enabled with a specific link 1895 * settings. 1896 */ 1897 enum lttpr_mode dc_link_decide_lttpr_mode(struct dc_link *link, 1898 struct dc_link_settings *link_setting); 1899 1900 /* Force DP RX to update its power state. 1901 * NOTE: this interface doesn't update dp main-link. Calling this function will 1902 * cause DP TX main-link and DP RX power states out of sync. DM has to restore 1903 * RX power state back upon finish DM specific execution requiring DP RX in a 1904 * specific power state. 1905 * @on - true to set DP RX in D0 power state, false to set DP RX in D3 power 1906 * state. 1907 */ 1908 void dc_link_dp_receiver_power_ctrl(struct dc_link *link, bool on); 1909 1910 /* Force link to read base dp receiver caps from dpcd 000h - 00Fh and overwrite 1911 * current value read from extended receiver cap from 02200h - 0220Fh. 1912 * Some DP RX has problems of providing accurate DP receiver caps from extended 1913 * field, this interface is a workaround to revert link back to use base caps. 1914 */ 1915 void dc_link_overwrite_extended_receiver_cap( 1916 struct dc_link *link); 1917 1918 void dc_link_edp_panel_backlight_power_on(struct dc_link *link, 1919 bool wait_for_hpd); 1920 1921 /* Set backlight level of an embedded panel (eDP, LVDS). 1922 * backlight_pwm_u16_16 is unsigned 32 bit with 16 bit integer 1923 * and 16 bit fractional, where 1.0 is max backlight value. 1924 */ 1925 bool dc_link_set_backlight_level(const struct dc_link *dc_link, 1926 uint32_t backlight_pwm_u16_16, 1927 uint32_t frame_ramp); 1928 1929 /* Set/get nits-based backlight level of an embedded panel (eDP, LVDS). */ 1930 bool dc_link_set_backlight_level_nits(struct dc_link *link, 1931 bool isHDR, 1932 uint32_t backlight_millinits, 1933 uint32_t transition_time_in_ms); 1934 1935 bool dc_link_get_backlight_level_nits(struct dc_link *link, 1936 uint32_t *backlight_millinits, 1937 uint32_t *backlight_millinits_peak); 1938 1939 int dc_link_get_backlight_level(const struct dc_link *dc_link); 1940 1941 int dc_link_get_target_backlight_pwm(const struct dc_link *link); 1942 1943 bool dc_link_set_psr_allow_active(struct dc_link *dc_link, const bool *enable, 1944 bool wait, bool force_static, const unsigned int *power_opts); 1945 1946 bool dc_link_get_psr_state(const struct dc_link *dc_link, enum dc_psr_state *state); 1947 1948 bool dc_link_setup_psr(struct dc_link *dc_link, 1949 const struct dc_stream_state *stream, struct psr_config *psr_config, 1950 struct psr_context *psr_context); 1951 1952 /* On eDP links this function call will stall until T12 has elapsed. 1953 * If the panel is not in power off state, this function will return 1954 * immediately. 1955 */ 1956 bool dc_link_wait_for_t12(struct dc_link *link); 1957 1958 /* Determine if dp trace has been initialized to reflect upto date result * 1959 * return - true if trace is initialized and has valid data. False dp trace 1960 * doesn't have valid result. 1961 */ 1962 bool dc_dp_trace_is_initialized(struct dc_link *link); 1963 1964 /* Query a dp trace flag to indicate if the current dp trace data has been 1965 * logged before 1966 */ 1967 bool dc_dp_trace_is_logged(struct dc_link *link, 1968 bool in_detection); 1969 1970 /* Set dp trace flag to indicate whether DM has already logged the current dp 1971 * trace data. DM can set is_logged to true upon logging and check 1972 * dc_dp_trace_is_logged before logging to avoid logging the same result twice. 1973 */ 1974 void dc_dp_trace_set_is_logged_flag(struct dc_link *link, 1975 bool in_detection, 1976 bool is_logged); 1977 1978 /* Obtain driver time stamp for last dp link training end. The time stamp is 1979 * formatted based on dm_get_timestamp DM function. 1980 * @in_detection - true to get link training end time stamp of last link 1981 * training in detection sequence. false to get link training end time stamp 1982 * of last link training in commit (dpms) sequence 1983 */ 1984 unsigned long long dc_dp_trace_get_lt_end_timestamp(struct dc_link *link, 1985 bool in_detection); 1986 1987 /* Get how many link training attempts dc has done with latest sequence. 1988 * @in_detection - true to get link training count of last link 1989 * training in detection sequence. false to get link training count of last link 1990 * training in commit (dpms) sequence 1991 */ 1992 const struct dp_trace_lt_counts *dc_dp_trace_get_lt_counts(struct dc_link *link, 1993 bool in_detection); 1994 1995 /* Get how many link loss has happened since last link training attempts */ 1996 unsigned int dc_dp_trace_get_link_loss_count(struct dc_link *link); 1997 1998 /* 1999 * USB4 DPIA BW ALLOCATION PUBLIC FUNCTIONS 2000 */ 2001 /* 2002 * Send a request from DP-Tx requesting to allocate BW remotely after 2003 * allocating it locally. This will get processed by CM and a CB function 2004 * will be called. 2005 * 2006 * @link: pointer to the dc_link struct instance 2007 * @req_bw: The requested bw in Kbyte to allocated 2008 * 2009 * return: none 2010 */ 2011 void dc_link_set_usb4_req_bw_req(struct dc_link *link, int req_bw); 2012 2013 /* 2014 * Handle function for when the status of the Request above is complete. 2015 * We will find out the result of allocating on CM and update structs. 2016 * 2017 * @link: pointer to the dc_link struct instance 2018 * @bw: Allocated or Estimated BW depending on the result 2019 * @result: Response type 2020 * 2021 * return: none 2022 */ 2023 void dc_link_handle_usb4_bw_alloc_response(struct dc_link *link, 2024 uint8_t bw, uint8_t result); 2025 2026 /* 2027 * Handle the USB4 BW Allocation related functionality here: 2028 * Plug => Try to allocate max bw from timing parameters supported by the sink 2029 * Unplug => de-allocate bw 2030 * 2031 * @link: pointer to the dc_link struct instance 2032 * @peak_bw: Peak bw used by the link/sink 2033 * 2034 * return: allocated bw else return 0 2035 */ 2036 int dc_link_dp_dpia_handle_usb4_bandwidth_allocation_for_link( 2037 struct dc_link *link, int peak_bw); 2038 2039 /* Sink Interfaces - A sink corresponds to a display output device */ 2040 2041 struct dc_container_id { 2042 // 128bit GUID in binary form 2043 unsigned char guid[16]; 2044 // 8 byte port ID -> ELD.PortID 2045 unsigned int portId[2]; 2046 // 128bit GUID in binary formufacturer name -> ELD.ManufacturerName 2047 unsigned short manufacturerName; 2048 // 2 byte product code -> ELD.ProductCode 2049 unsigned short productCode; 2050 }; 2051 2052 2053 struct dc_sink_dsc_caps { 2054 // 'true' if these are virtual DPCD's DSC caps (immediately upstream of sink in MST topology), 2055 // 'false' if they are sink's DSC caps 2056 bool is_virtual_dpcd_dsc; 2057 #if defined(CONFIG_DRM_AMD_DC_DCN) 2058 // 'true' if MST topology supports DSC passthrough for sink 2059 // 'false' if MST topology does not support DSC passthrough 2060 bool is_dsc_passthrough_supported; 2061 #endif 2062 struct dsc_dec_dpcd_caps dsc_dec_caps; 2063 }; 2064 2065 struct dc_sink_fec_caps { 2066 bool is_rx_fec_supported; 2067 bool is_topology_fec_supported; 2068 }; 2069 2070 struct scdc_caps { 2071 union hdmi_scdc_manufacturer_OUI_data manufacturer_OUI; 2072 union hdmi_scdc_device_id_data device_id; 2073 }; 2074 2075 /* 2076 * The sink structure contains EDID and other display device properties 2077 */ 2078 struct dc_sink { 2079 enum signal_type sink_signal; 2080 struct dc_edid dc_edid; /* raw edid */ 2081 struct dc_edid_caps edid_caps; /* parse display caps */ 2082 struct dc_container_id *dc_container_id; 2083 uint32_t dongle_max_pix_clk; 2084 void *priv; 2085 struct stereo_3d_features features_3d[TIMING_3D_FORMAT_MAX]; 2086 bool converter_disable_audio; 2087 2088 struct scdc_caps scdc_caps; 2089 struct dc_sink_dsc_caps dsc_caps; 2090 struct dc_sink_fec_caps fec_caps; 2091 2092 bool is_vsc_sdp_colorimetry_supported; 2093 2094 /* private to DC core */ 2095 struct dc_link *link; 2096 struct dc_context *ctx; 2097 2098 uint32_t sink_id; 2099 2100 /* private to dc_sink.c */ 2101 // refcount must be the last member in dc_sink, since we want the 2102 // sink structure to be logically cloneable up to (but not including) 2103 // refcount 2104 struct kref refcount; 2105 }; 2106 2107 void dc_sink_retain(struct dc_sink *sink); 2108 void dc_sink_release(struct dc_sink *sink); 2109 2110 struct dc_sink_init_data { 2111 enum signal_type sink_signal; 2112 struct dc_link *link; 2113 uint32_t dongle_max_pix_clk; 2114 bool converter_disable_audio; 2115 }; 2116 2117 bool dc_extended_blank_supported(struct dc *dc); 2118 2119 struct dc_sink *dc_sink_create(const struct dc_sink_init_data *init_params); 2120 2121 /* Newer interfaces */ 2122 struct dc_cursor { 2123 struct dc_plane_address address; 2124 struct dc_cursor_attributes attributes; 2125 }; 2126 2127 2128 /* Interrupt interfaces */ 2129 enum dc_irq_source dc_interrupt_to_irq_source( 2130 struct dc *dc, 2131 uint32_t src_id, 2132 uint32_t ext_id); 2133 bool dc_interrupt_set(struct dc *dc, enum dc_irq_source src, bool enable); 2134 void dc_interrupt_ack(struct dc *dc, enum dc_irq_source src); 2135 enum dc_irq_source dc_get_hpd_irq_source_at_index( 2136 struct dc *dc, uint32_t link_index); 2137 2138 void dc_notify_vsync_int_state(struct dc *dc, struct dc_stream_state *stream, bool enable); 2139 2140 /* Power Interfaces */ 2141 2142 void dc_set_power_state( 2143 struct dc *dc, 2144 enum dc_acpi_cm_power_state power_state); 2145 void dc_resume(struct dc *dc); 2146 2147 void dc_power_down_on_boot(struct dc *dc); 2148 2149 /* 2150 * HDCP Interfaces 2151 */ 2152 enum hdcp_message_status dc_process_hdcp_msg( 2153 enum signal_type signal, 2154 struct dc_link *link, 2155 struct hdcp_protection_message *message_info); 2156 bool dc_is_dmcu_initialized(struct dc *dc); 2157 2158 enum dc_status dc_set_clock(struct dc *dc, enum dc_clock_type clock_type, uint32_t clk_khz, uint32_t stepping); 2159 void dc_get_clock(struct dc *dc, enum dc_clock_type clock_type, struct dc_clock_config *clock_cfg); 2160 2161 bool dc_is_plane_eligible_for_idle_optimizations(struct dc *dc, struct dc_plane_state *plane, 2162 struct dc_cursor_attributes *cursor_attr); 2163 2164 void dc_allow_idle_optimizations(struct dc *dc, bool allow); 2165 2166 /* set min and max memory clock to lowest and highest DPM level, respectively */ 2167 void dc_unlock_memory_clock_frequency(struct dc *dc); 2168 2169 /* set min memory clock to the min required for current mode, max to maxDPM */ 2170 void dc_lock_memory_clock_frequency(struct dc *dc); 2171 2172 /* set soft max for memclk, to be used for AC/DC switching clock limitations */ 2173 void dc_enable_dcmode_clk_limit(struct dc *dc, bool enable); 2174 2175 /* cleanup on driver unload */ 2176 void dc_hardware_release(struct dc *dc); 2177 2178 /* disables fw based mclk switch */ 2179 void dc_mclk_switch_using_fw_based_vblank_stretch_shut_down(struct dc *dc); 2180 2181 bool dc_set_psr_allow_active(struct dc *dc, bool enable); 2182 void dc_z10_restore(const struct dc *dc); 2183 void dc_z10_save_init(struct dc *dc); 2184 2185 bool dc_is_dmub_outbox_supported(struct dc *dc); 2186 bool dc_enable_dmub_notifications(struct dc *dc); 2187 2188 void dc_enable_dmub_outbox(struct dc *dc); 2189 2190 bool dc_process_dmub_aux_transfer_async(struct dc *dc, 2191 uint32_t link_index, 2192 struct aux_payload *payload); 2193 2194 /* Get dc link index from dpia port index */ 2195 uint8_t get_link_index_from_dpia_port_index(const struct dc *dc, 2196 uint8_t dpia_port_index); 2197 2198 bool dc_process_dmub_set_config_async(struct dc *dc, 2199 uint32_t link_index, 2200 struct set_config_cmd_payload *payload, 2201 struct dmub_notification *notify); 2202 2203 enum dc_status dc_process_dmub_set_mst_slots(const struct dc *dc, 2204 uint32_t link_index, 2205 uint8_t mst_alloc_slots, 2206 uint8_t *mst_slots_in_use); 2207 2208 void dc_process_dmub_dpia_hpd_int_enable(const struct dc *dc, 2209 uint32_t hpd_int_enable); 2210 2211 /* DSC Interfaces */ 2212 #include "dc_dsc.h" 2213 2214 /* Disable acc mode Interfaces */ 2215 void dc_disable_accelerated_mode(struct dc *dc); 2216 2217 #endif /* DC_INTERFACE_H_ */ 2218