1 /* 2 * Copyright 2012-14 Advanced Micro Devices, Inc. 3 * 4 * Permission is hereby granted, free of charge, to any person obtaining a 5 * copy of this software and associated documentation files (the "Software"), 6 * to deal in the Software without restriction, including without limitation 7 * the rights to use, copy, modify, merge, publish, distribute, sublicense, 8 * and/or sell copies of the Software, and to permit persons to whom the 9 * Software is furnished to do so, subject to the following conditions: 10 * 11 * The above copyright notice and this permission notice shall be included in 12 * all copies or substantial portions of the Software. 13 * 14 * THE SOFTWARE IS PROVIDED "AS IS", WITHOUT WARRANTY OF ANY KIND, EXPRESS OR 15 * IMPLIED, INCLUDING BUT NOT LIMITED TO THE WARRANTIES OF MERCHANTABILITY, 16 * FITNESS FOR A PARTICULAR PURPOSE AND NONINFRINGEMENT. IN NO EVENT SHALL 17 * THE COPYRIGHT HOLDER(S) OR AUTHOR(S) BE LIABLE FOR ANY CLAIM, DAMAGES OR 18 * OTHER LIABILITY, WHETHER IN AN ACTION OF CONTRACT, TORT OR OTHERWISE, 19 * ARISING FROM, OUT OF OR IN CONNECTION WITH THE SOFTWARE OR THE USE OR 20 * OTHER DEALINGS IN THE SOFTWARE. 21 * 22 * Authors: AMD 23 * 24 */ 25 26 #ifndef DC_INTERFACE_H_ 27 #define DC_INTERFACE_H_ 28 29 #include "dc_types.h" 30 #include "grph_object_defs.h" 31 #include "logger_types.h" 32 #if defined(CONFIG_DRM_AMD_DC_HDCP) 33 #include "hdcp_types.h" 34 #endif 35 #include "gpio_types.h" 36 #include "link_service_types.h" 37 #include "grph_object_ctrl_defs.h" 38 #include <inc/hw/opp.h> 39 40 #include "inc/hw_sequencer.h" 41 #include "inc/compressor.h" 42 #include "inc/hw/dmcu.h" 43 #include "dml/display_mode_lib.h" 44 45 /* forward declaration */ 46 struct aux_payload; 47 48 #define DC_VER "3.2.139" 49 50 #define MAX_SURFACES 3 51 #define MAX_PLANES 6 52 #define MAX_STREAMS 6 53 #define MAX_SINKS_PER_LINK 4 54 #define MIN_VIEWPORT_SIZE 12 55 #define MAX_NUM_EDP 2 56 57 /******************************************************************************* 58 * Display Core Interfaces 59 ******************************************************************************/ 60 struct dc_versions { 61 const char *dc_ver; 62 struct dmcu_version dmcu_version; 63 }; 64 65 enum dp_protocol_version { 66 DP_VERSION_1_4, 67 }; 68 69 enum dc_plane_type { 70 DC_PLANE_TYPE_INVALID, 71 DC_PLANE_TYPE_DCE_RGB, 72 DC_PLANE_TYPE_DCE_UNDERLAY, 73 DC_PLANE_TYPE_DCN_UNIVERSAL, 74 }; 75 76 struct dc_plane_cap { 77 enum dc_plane_type type; 78 uint32_t blends_with_above : 1; 79 uint32_t blends_with_below : 1; 80 uint32_t per_pixel_alpha : 1; 81 struct { 82 uint32_t argb8888 : 1; 83 uint32_t nv12 : 1; 84 uint32_t fp16 : 1; 85 uint32_t p010 : 1; 86 uint32_t ayuv : 1; 87 } pixel_format_support; 88 // max upscaling factor x1000 89 // upscaling factors are always >= 1 90 // for example, 1080p -> 8K is 4.0, or 4000 raw value 91 struct { 92 uint32_t argb8888; 93 uint32_t nv12; 94 uint32_t fp16; 95 } max_upscale_factor; 96 // max downscale factor x1000 97 // downscale factors are always <= 1 98 // for example, 8K -> 1080p is 0.25, or 250 raw value 99 struct { 100 uint32_t argb8888; 101 uint32_t nv12; 102 uint32_t fp16; 103 } max_downscale_factor; 104 // minimal width/height 105 uint32_t min_width; 106 uint32_t min_height; 107 }; 108 109 // Color management caps (DPP and MPC) 110 struct rom_curve_caps { 111 uint16_t srgb : 1; 112 uint16_t bt2020 : 1; 113 uint16_t gamma2_2 : 1; 114 uint16_t pq : 1; 115 uint16_t hlg : 1; 116 }; 117 118 struct dpp_color_caps { 119 uint16_t dcn_arch : 1; // all DCE generations treated the same 120 // input lut is different than most LUTs, just plain 256-entry lookup 121 uint16_t input_lut_shared : 1; // shared with DGAM 122 uint16_t icsc : 1; 123 uint16_t dgam_ram : 1; 124 uint16_t post_csc : 1; // before gamut remap 125 uint16_t gamma_corr : 1; 126 127 // hdr_mult and gamut remap always available in DPP (in that order) 128 // 3d lut implies shaper LUT, 129 // it may be shared with MPC - check MPC:shared_3d_lut flag 130 uint16_t hw_3d_lut : 1; 131 uint16_t ogam_ram : 1; // blnd gam 132 uint16_t ocsc : 1; 133 uint16_t dgam_rom_for_yuv : 1; 134 struct rom_curve_caps dgam_rom_caps; 135 struct rom_curve_caps ogam_rom_caps; 136 }; 137 138 struct mpc_color_caps { 139 uint16_t gamut_remap : 1; 140 uint16_t ogam_ram : 1; 141 uint16_t ocsc : 1; 142 uint16_t num_3dluts : 3; //3d lut always assumes a preceding shaper LUT 143 uint16_t shared_3d_lut:1; //can be in either DPP or MPC, but single instance 144 145 struct rom_curve_caps ogam_rom_caps; 146 }; 147 148 struct dc_color_caps { 149 struct dpp_color_caps dpp; 150 struct mpc_color_caps mpc; 151 }; 152 153 struct dc_caps { 154 uint32_t max_streams; 155 uint32_t max_links; 156 uint32_t max_audios; 157 uint32_t max_slave_planes; 158 uint32_t max_slave_yuv_planes; 159 uint32_t max_slave_rgb_planes; 160 uint32_t max_planes; 161 uint32_t max_downscale_ratio; 162 uint32_t i2c_speed_in_khz; 163 uint32_t i2c_speed_in_khz_hdcp; 164 uint32_t dmdata_alloc_size; 165 unsigned int max_cursor_size; 166 unsigned int max_video_width; 167 unsigned int min_horizontal_blanking_period; 168 int linear_pitch_alignment; 169 bool dcc_const_color; 170 bool dynamic_audio; 171 bool is_apu; 172 bool dual_link_dvi; 173 bool post_blend_color_processing; 174 bool force_dp_tps4_for_cp2520; 175 bool disable_dp_clk_share; 176 bool psp_setup_panel_mode; 177 bool extended_aux_timeout_support; 178 bool dmcub_support; 179 uint32_t num_of_internal_disp; 180 enum dp_protocol_version max_dp_protocol_version; 181 unsigned int mall_size_per_mem_channel; 182 unsigned int mall_size_total; 183 unsigned int cursor_cache_size; 184 struct dc_plane_cap planes[MAX_PLANES]; 185 struct dc_color_caps color; 186 }; 187 188 struct dc_bug_wa { 189 bool no_connect_phy_config; 190 bool dedcn20_305_wa; 191 bool skip_clock_update; 192 bool lt_early_cr_pattern; 193 }; 194 195 struct dc_dcc_surface_param { 196 struct dc_size surface_size; 197 enum surface_pixel_format format; 198 enum swizzle_mode_values swizzle_mode; 199 enum dc_scan_direction scan; 200 }; 201 202 struct dc_dcc_setting { 203 unsigned int max_compressed_blk_size; 204 unsigned int max_uncompressed_blk_size; 205 bool independent_64b_blks; 206 #if defined(CONFIG_DRM_AMD_DC_DCN) 207 //These bitfields to be used starting with DCN 3.0 208 struct { 209 uint32_t dcc_256_64_64 : 1;//available in ASICs before DCN 3.0 (the worst compression case) 210 uint32_t dcc_128_128_uncontrained : 1; //available in ASICs before DCN 3.0 211 uint32_t dcc_256_128_128 : 1; //available starting with DCN 3.0 212 uint32_t dcc_256_256_unconstrained : 1; //available in ASICs before DCN 3.0 (the best compression case) 213 } dcc_controls; 214 #endif 215 }; 216 217 struct dc_surface_dcc_cap { 218 union { 219 struct { 220 struct dc_dcc_setting rgb; 221 } grph; 222 223 struct { 224 struct dc_dcc_setting luma; 225 struct dc_dcc_setting chroma; 226 } video; 227 }; 228 229 bool capable; 230 bool const_color_support; 231 }; 232 233 struct dc_static_screen_params { 234 struct { 235 bool force_trigger; 236 bool cursor_update; 237 bool surface_update; 238 bool overlay_update; 239 } triggers; 240 unsigned int num_frames; 241 }; 242 243 244 /* Surface update type is used by dc_update_surfaces_and_stream 245 * The update type is determined at the very beginning of the function based 246 * on parameters passed in and decides how much programming (or updating) is 247 * going to be done during the call. 248 * 249 * UPDATE_TYPE_FAST is used for really fast updates that do not require much 250 * logical calculations or hardware register programming. This update MUST be 251 * ISR safe on windows. Currently fast update will only be used to flip surface 252 * address. 253 * 254 * UPDATE_TYPE_MED is used for slower updates which require significant hw 255 * re-programming however do not affect bandwidth consumption or clock 256 * requirements. At present, this is the level at which front end updates 257 * that do not require us to run bw_calcs happen. These are in/out transfer func 258 * updates, viewport offset changes, recout size changes and pixel depth changes. 259 * This update can be done at ISR, but we want to minimize how often this happens. 260 * 261 * UPDATE_TYPE_FULL is slow. Really slow. This requires us to recalculate our 262 * bandwidth and clocks, possibly rearrange some pipes and reprogram anything front 263 * end related. Any time viewport dimensions, recout dimensions, scaling ratios or 264 * gamma need to be adjusted or pipe needs to be turned on (or disconnected) we do 265 * a full update. This cannot be done at ISR level and should be a rare event. 266 * Unless someone is stress testing mpo enter/exit, playing with colour or adjusting 267 * underscan we don't expect to see this call at all. 268 */ 269 270 enum surface_update_type { 271 UPDATE_TYPE_FAST, /* super fast, safe to execute in isr */ 272 UPDATE_TYPE_MED, /* ISR safe, most of programming needed, no bw/clk change*/ 273 UPDATE_TYPE_FULL, /* may need to shuffle resources */ 274 }; 275 276 /* Forward declaration*/ 277 struct dc; 278 struct dc_plane_state; 279 struct dc_state; 280 281 282 struct dc_cap_funcs { 283 bool (*get_dcc_compression_cap)(const struct dc *dc, 284 const struct dc_dcc_surface_param *input, 285 struct dc_surface_dcc_cap *output); 286 }; 287 288 struct link_training_settings; 289 290 291 /* Structure to hold configuration flags set by dm at dc creation. */ 292 struct dc_config { 293 bool gpu_vm_support; 294 bool disable_disp_pll_sharing; 295 bool fbc_support; 296 bool disable_fractional_pwm; 297 bool allow_seamless_boot_optimization; 298 bool power_down_display_on_boot; 299 bool edp_not_connected; 300 bool force_enum_edp; 301 bool forced_clocks; 302 bool allow_lttpr_non_transparent_mode; 303 bool multi_mon_pp_mclk_switch; 304 bool disable_dmcu; 305 bool enable_4to1MPC; 306 #if defined(CONFIG_DRM_AMD_DC_DCN) 307 bool clamp_min_dcfclk; 308 #endif 309 uint64_t vblank_alignment_dto_params; 310 uint8_t vblank_alignment_max_frame_time_diff; 311 bool is_asymmetric_memory; 312 bool is_single_rank_dimm; 313 }; 314 315 enum visual_confirm { 316 VISUAL_CONFIRM_DISABLE = 0, 317 VISUAL_CONFIRM_SURFACE = 1, 318 VISUAL_CONFIRM_HDR = 2, 319 VISUAL_CONFIRM_MPCTREE = 4, 320 VISUAL_CONFIRM_PSR = 5, 321 VISUAL_CONFIRM_SWIZZLE = 9, 322 }; 323 324 enum dcc_option { 325 DCC_ENABLE = 0, 326 DCC_DISABLE = 1, 327 DCC_HALF_REQ_DISALBE = 2, 328 }; 329 330 enum pipe_split_policy { 331 MPC_SPLIT_DYNAMIC = 0, 332 MPC_SPLIT_AVOID = 1, 333 MPC_SPLIT_AVOID_MULT_DISP = 2, 334 }; 335 336 enum wm_report_mode { 337 WM_REPORT_DEFAULT = 0, 338 WM_REPORT_OVERRIDE = 1, 339 }; 340 enum dtm_pstate{ 341 dtm_level_p0 = 0,/*highest voltage*/ 342 dtm_level_p1, 343 dtm_level_p2, 344 dtm_level_p3, 345 dtm_level_p4,/*when active_display_count = 0*/ 346 }; 347 348 enum dcn_pwr_state { 349 DCN_PWR_STATE_UNKNOWN = -1, 350 DCN_PWR_STATE_MISSION_MODE = 0, 351 DCN_PWR_STATE_LOW_POWER = 3, 352 }; 353 354 #if defined(CONFIG_DRM_AMD_DC_DCN3_1) 355 enum dcn_z9_support_state { 356 DCN_Z9_SUPPORT_UNKNOWN, 357 DCN_Z9_SUPPORT_ALLOW, 358 DCN_Z9_SUPPORT_DISALLOW, 359 }; 360 #endif 361 /* 362 * For any clocks that may differ per pipe 363 * only the max is stored in this structure 364 */ 365 struct dc_clocks { 366 int dispclk_khz; 367 int actual_dispclk_khz; 368 int dppclk_khz; 369 int actual_dppclk_khz; 370 int disp_dpp_voltage_level_khz; 371 int dcfclk_khz; 372 int socclk_khz; 373 int dcfclk_deep_sleep_khz; 374 int fclk_khz; 375 int phyclk_khz; 376 int dramclk_khz; 377 bool p_state_change_support; 378 #if defined(CONFIG_DRM_AMD_DC_DCN3_1) 379 enum dcn_z9_support_state z9_support; 380 bool dtbclk_en; 381 #endif 382 enum dcn_pwr_state pwr_state; 383 /* 384 * Elements below are not compared for the purposes of 385 * optimization required 386 */ 387 bool prev_p_state_change_support; 388 enum dtm_pstate dtm_level; 389 int max_supported_dppclk_khz; 390 int max_supported_dispclk_khz; 391 int bw_dppclk_khz; /*a copy of dppclk_khz*/ 392 int bw_dispclk_khz; 393 }; 394 395 struct dc_bw_validation_profile { 396 bool enable; 397 398 unsigned long long total_ticks; 399 unsigned long long voltage_level_ticks; 400 unsigned long long watermark_ticks; 401 unsigned long long rq_dlg_ticks; 402 403 unsigned long long total_count; 404 unsigned long long skip_fast_count; 405 unsigned long long skip_pass_count; 406 unsigned long long skip_fail_count; 407 }; 408 409 #define BW_VAL_TRACE_SETUP() \ 410 unsigned long long end_tick = 0; \ 411 unsigned long long voltage_level_tick = 0; \ 412 unsigned long long watermark_tick = 0; \ 413 unsigned long long start_tick = dc->debug.bw_val_profile.enable ? \ 414 dm_get_timestamp(dc->ctx) : 0 415 416 #define BW_VAL_TRACE_COUNT() \ 417 if (dc->debug.bw_val_profile.enable) \ 418 dc->debug.bw_val_profile.total_count++ 419 420 #define BW_VAL_TRACE_SKIP(status) \ 421 if (dc->debug.bw_val_profile.enable) { \ 422 if (!voltage_level_tick) \ 423 voltage_level_tick = dm_get_timestamp(dc->ctx); \ 424 dc->debug.bw_val_profile.skip_ ## status ## _count++; \ 425 } 426 427 #define BW_VAL_TRACE_END_VOLTAGE_LEVEL() \ 428 if (dc->debug.bw_val_profile.enable) \ 429 voltage_level_tick = dm_get_timestamp(dc->ctx) 430 431 #define BW_VAL_TRACE_END_WATERMARKS() \ 432 if (dc->debug.bw_val_profile.enable) \ 433 watermark_tick = dm_get_timestamp(dc->ctx) 434 435 #define BW_VAL_TRACE_FINISH() \ 436 if (dc->debug.bw_val_profile.enable) { \ 437 end_tick = dm_get_timestamp(dc->ctx); \ 438 dc->debug.bw_val_profile.total_ticks += end_tick - start_tick; \ 439 dc->debug.bw_val_profile.voltage_level_ticks += voltage_level_tick - start_tick; \ 440 if (watermark_tick) { \ 441 dc->debug.bw_val_profile.watermark_ticks += watermark_tick - voltage_level_tick; \ 442 dc->debug.bw_val_profile.rq_dlg_ticks += end_tick - watermark_tick; \ 443 } \ 444 } 445 446 union mem_low_power_enable_options { 447 struct { 448 bool vga: 1; 449 bool i2c: 1; 450 bool dmcu: 1; 451 bool dscl: 1; 452 bool cm: 1; 453 bool mpc: 1; 454 bool optc: 1; 455 } bits; 456 uint32_t u32All; 457 }; 458 459 struct dc_debug_options { 460 enum visual_confirm visual_confirm; 461 bool sanity_checks; 462 bool max_disp_clk; 463 bool surface_trace; 464 bool timing_trace; 465 bool clock_trace; 466 bool validation_trace; 467 bool bandwidth_calcs_trace; 468 int max_downscale_src_width; 469 470 /* stutter efficiency related */ 471 bool disable_stutter; 472 bool use_max_lb; 473 enum dcc_option disable_dcc; 474 enum pipe_split_policy pipe_split_policy; 475 bool force_single_disp_pipe_split; 476 bool voltage_align_fclk; 477 bool disable_min_fclk; 478 479 bool disable_dfs_bypass; 480 bool disable_dpp_power_gate; 481 bool disable_hubp_power_gate; 482 bool disable_dsc_power_gate; 483 int dsc_min_slice_height_override; 484 int dsc_bpp_increment_div; 485 bool native422_support; 486 bool disable_pplib_wm_range; 487 enum wm_report_mode pplib_wm_report_mode; 488 unsigned int min_disp_clk_khz; 489 unsigned int min_dpp_clk_khz; 490 int sr_exit_time_dpm0_ns; 491 int sr_enter_plus_exit_time_dpm0_ns; 492 int sr_exit_time_ns; 493 int sr_enter_plus_exit_time_ns; 494 int urgent_latency_ns; 495 uint32_t underflow_assert_delay_us; 496 int percent_of_ideal_drambw; 497 int dram_clock_change_latency_ns; 498 bool optimized_watermark; 499 int always_scale; 500 bool disable_pplib_clock_request; 501 bool disable_clock_gate; 502 bool disable_mem_low_power; 503 #if defined(CONFIG_DRM_AMD_DC_DCN3_1) 504 bool pstate_enabled; 505 #endif 506 bool disable_dmcu; 507 bool disable_psr; 508 bool force_abm_enable; 509 bool disable_stereo_support; 510 bool vsr_support; 511 bool performance_trace; 512 bool az_endpoint_mute_only; 513 bool always_use_regamma; 514 bool recovery_enabled; 515 bool avoid_vbios_exec_table; 516 bool scl_reset_length10; 517 bool hdmi20_disable; 518 bool skip_detection_link_training; 519 uint32_t edid_read_retry_times; 520 bool remove_disconnect_edp; 521 unsigned int force_odm_combine; //bit vector based on otg inst 522 #if defined(CONFIG_DRM_AMD_DC_DCN) 523 unsigned int force_odm_combine_4to1; //bit vector based on otg inst 524 #endif 525 #if defined(CONFIG_DRM_AMD_DC_DCN3_1) 526 bool disable_z9_mpc; 527 #endif 528 unsigned int force_fclk_khz; 529 bool enable_tri_buf; 530 bool dmub_offload_enabled; 531 bool dmcub_emulation; 532 #if defined(CONFIG_DRM_AMD_DC_DCN) 533 bool disable_idle_power_optimizations; 534 unsigned int mall_size_override; 535 unsigned int mall_additional_timer_percent; 536 bool mall_error_as_fatal; 537 #endif 538 bool dmub_command_table; /* for testing only */ 539 struct dc_bw_validation_profile bw_val_profile; 540 bool disable_fec; 541 bool disable_48mhz_pwrdwn; 542 /* This forces a hard min on the DCFCLK requested to SMU/PP 543 * watermarks are not affected. 544 */ 545 unsigned int force_min_dcfclk_mhz; 546 #if defined(CONFIG_DRM_AMD_DC_DCN) 547 int dwb_fi_phase; 548 #endif 549 bool disable_timing_sync; 550 bool cm_in_bypass; 551 int force_clock_mode;/*every mode change.*/ 552 553 bool disable_dram_clock_change_vactive_support; 554 bool validate_dml_output; 555 bool enable_dmcub_surface_flip; 556 bool usbc_combo_phy_reset_wa; 557 bool disable_dsc; 558 bool enable_dram_clock_change_one_display_vactive; 559 union mem_low_power_enable_options enable_mem_low_power; 560 bool force_vblank_alignment; 561 562 /* Enable dmub aux for legacy ddc */ 563 bool enable_dmub_aux_for_legacy_ddc; 564 bool optimize_edp_link_rate; /* eDP ILR */ 565 /* force enable edp FEC */ 566 bool force_enable_edp_fec; 567 /* FEC/PSR1 sequence enable delay in 100us */ 568 uint8_t fec_enable_delay_in100us; 569 #if defined(CONFIG_DRM_AMD_DC_DCN3_1) 570 bool disable_z10; 571 bool enable_sw_cntl_psr; 572 #endif 573 }; 574 575 struct dc_debug_data { 576 uint32_t ltFailCount; 577 uint32_t i2cErrorCount; 578 uint32_t auxErrorCount; 579 }; 580 581 struct dc_phy_addr_space_config { 582 struct { 583 uint64_t start_addr; 584 uint64_t end_addr; 585 uint64_t fb_top; 586 uint64_t fb_offset; 587 uint64_t fb_base; 588 uint64_t agp_top; 589 uint64_t agp_bot; 590 uint64_t agp_base; 591 } system_aperture; 592 593 struct { 594 uint64_t page_table_start_addr; 595 uint64_t page_table_end_addr; 596 uint64_t page_table_base_addr; 597 #if defined(CONFIG_DRM_AMD_DC_DCN3_1) 598 bool base_addr_is_mc_addr; 599 #endif 600 } gart_config; 601 602 bool valid; 603 bool is_hvm_enabled; 604 uint64_t page_table_default_page_addr; 605 }; 606 607 struct dc_virtual_addr_space_config { 608 uint64_t page_table_base_addr; 609 uint64_t page_table_start_addr; 610 uint64_t page_table_end_addr; 611 uint32_t page_table_block_size_in_bytes; 612 uint8_t page_table_depth; // 1 = 1 level, 2 = 2 level, etc. 0 = invalid 613 }; 614 615 struct dc_bounding_box_overrides { 616 int sr_exit_time_ns; 617 int sr_enter_plus_exit_time_ns; 618 int urgent_latency_ns; 619 int percent_of_ideal_drambw; 620 int dram_clock_change_latency_ns; 621 int dummy_clock_change_latency_ns; 622 /* This forces a hard min on the DCFCLK we use 623 * for DML. Unlike the debug option for forcing 624 * DCFCLK, this override affects watermark calculations 625 */ 626 int min_dcfclk_mhz; 627 }; 628 629 struct resource_pool; 630 struct dce_hwseq; 631 struct gpu_info_soc_bounding_box_v1_0; 632 struct dc { 633 struct dc_versions versions; 634 struct dc_caps caps; 635 struct dc_cap_funcs cap_funcs; 636 struct dc_config config; 637 struct dc_debug_options debug; 638 struct dc_bounding_box_overrides bb_overrides; 639 struct dc_bug_wa work_arounds; 640 struct dc_context *ctx; 641 struct dc_phy_addr_space_config vm_pa_config; 642 643 uint8_t link_count; 644 struct dc_link *links[MAX_PIPES * 2]; 645 646 struct dc_state *current_state; 647 struct resource_pool *res_pool; 648 649 struct clk_mgr *clk_mgr; 650 651 /* Display Engine Clock levels */ 652 struct dm_pp_clock_levels sclk_lvls; 653 654 /* Inputs into BW and WM calculations. */ 655 struct bw_calcs_dceip *bw_dceip; 656 struct bw_calcs_vbios *bw_vbios; 657 #ifdef CONFIG_DRM_AMD_DC_DCN 658 struct dcn_soc_bounding_box *dcn_soc; 659 struct dcn_ip_params *dcn_ip; 660 struct display_mode_lib dml; 661 #endif 662 663 /* HW functions */ 664 struct hw_sequencer_funcs hwss; 665 struct dce_hwseq *hwseq; 666 667 /* Require to optimize clocks and bandwidth for added/removed planes */ 668 bool optimized_required; 669 bool wm_optimized_required; 670 #if defined(CONFIG_DRM_AMD_DC_DCN) 671 bool idle_optimizations_allowed; 672 #endif 673 674 /* Require to maintain clocks and bandwidth for UEFI enabled HW */ 675 676 /* FBC compressor */ 677 struct compressor *fbc_compressor; 678 679 struct dc_debug_data debug_data; 680 struct dpcd_vendor_signature vendor_signature; 681 682 const char *build_id; 683 struct vm_helper *vm_helper; 684 }; 685 686 enum frame_buffer_mode { 687 FRAME_BUFFER_MODE_LOCAL_ONLY = 0, 688 FRAME_BUFFER_MODE_ZFB_ONLY, 689 FRAME_BUFFER_MODE_MIXED_ZFB_AND_LOCAL, 690 } ; 691 692 struct dchub_init_data { 693 int64_t zfb_phys_addr_base; 694 int64_t zfb_mc_base_addr; 695 uint64_t zfb_size_in_byte; 696 enum frame_buffer_mode fb_mode; 697 bool dchub_initialzied; 698 bool dchub_info_valid; 699 }; 700 701 struct dc_init_data { 702 struct hw_asic_id asic_id; 703 void *driver; /* ctx */ 704 struct cgs_device *cgs_device; 705 struct dc_bounding_box_overrides bb_overrides; 706 707 int num_virtual_links; 708 /* 709 * If 'vbios_override' not NULL, it will be called instead 710 * of the real VBIOS. Intended use is Diagnostics on FPGA. 711 */ 712 struct dc_bios *vbios_override; 713 enum dce_environment dce_environment; 714 715 struct dmub_offload_funcs *dmub_if; 716 struct dc_reg_helper_state *dmub_offload; 717 718 struct dc_config flags; 719 uint64_t log_mask; 720 721 struct dpcd_vendor_signature vendor_signature; 722 #if defined(CONFIG_DRM_AMD_DC_DCN) 723 bool force_smu_not_present; 724 #endif 725 }; 726 727 struct dc_callback_init { 728 #ifdef CONFIG_DRM_AMD_DC_HDCP 729 struct cp_psp cp_psp; 730 #else 731 uint8_t reserved; 732 #endif 733 }; 734 735 struct dc *dc_create(const struct dc_init_data *init_params); 736 void dc_hardware_init(struct dc *dc); 737 738 int dc_get_vmid_use_vector(struct dc *dc); 739 void dc_setup_vm_context(struct dc *dc, struct dc_virtual_addr_space_config *va_config, int vmid); 740 /* Returns the number of vmids supported */ 741 int dc_setup_system_context(struct dc *dc, struct dc_phy_addr_space_config *pa_config); 742 void dc_init_callbacks(struct dc *dc, 743 const struct dc_callback_init *init_params); 744 void dc_deinit_callbacks(struct dc *dc); 745 void dc_destroy(struct dc **dc); 746 747 /******************************************************************************* 748 * Surface Interfaces 749 ******************************************************************************/ 750 751 enum { 752 TRANSFER_FUNC_POINTS = 1025 753 }; 754 755 struct dc_hdr_static_metadata { 756 /* display chromaticities and white point in units of 0.00001 */ 757 unsigned int chromaticity_green_x; 758 unsigned int chromaticity_green_y; 759 unsigned int chromaticity_blue_x; 760 unsigned int chromaticity_blue_y; 761 unsigned int chromaticity_red_x; 762 unsigned int chromaticity_red_y; 763 unsigned int chromaticity_white_point_x; 764 unsigned int chromaticity_white_point_y; 765 766 uint32_t min_luminance; 767 uint32_t max_luminance; 768 uint32_t maximum_content_light_level; 769 uint32_t maximum_frame_average_light_level; 770 }; 771 772 enum dc_transfer_func_type { 773 TF_TYPE_PREDEFINED, 774 TF_TYPE_DISTRIBUTED_POINTS, 775 TF_TYPE_BYPASS, 776 TF_TYPE_HWPWL 777 }; 778 779 struct dc_transfer_func_distributed_points { 780 struct fixed31_32 red[TRANSFER_FUNC_POINTS]; 781 struct fixed31_32 green[TRANSFER_FUNC_POINTS]; 782 struct fixed31_32 blue[TRANSFER_FUNC_POINTS]; 783 784 uint16_t end_exponent; 785 uint16_t x_point_at_y1_red; 786 uint16_t x_point_at_y1_green; 787 uint16_t x_point_at_y1_blue; 788 }; 789 790 enum dc_transfer_func_predefined { 791 TRANSFER_FUNCTION_SRGB, 792 TRANSFER_FUNCTION_BT709, 793 TRANSFER_FUNCTION_PQ, 794 TRANSFER_FUNCTION_LINEAR, 795 TRANSFER_FUNCTION_UNITY, 796 TRANSFER_FUNCTION_HLG, 797 TRANSFER_FUNCTION_HLG12, 798 TRANSFER_FUNCTION_GAMMA22, 799 TRANSFER_FUNCTION_GAMMA24, 800 TRANSFER_FUNCTION_GAMMA26 801 }; 802 803 804 struct dc_transfer_func { 805 struct kref refcount; 806 enum dc_transfer_func_type type; 807 enum dc_transfer_func_predefined tf; 808 /* FP16 1.0 reference level in nits, default is 80 nits, only for PQ*/ 809 uint32_t sdr_ref_white_level; 810 union { 811 struct pwl_params pwl; 812 struct dc_transfer_func_distributed_points tf_pts; 813 }; 814 }; 815 816 817 union dc_3dlut_state { 818 struct { 819 uint32_t initialized:1; /*if 3dlut is went through color module for initialization */ 820 uint32_t rmu_idx_valid:1; /*if mux settings are valid*/ 821 uint32_t rmu_mux_num:3; /*index of mux to use*/ 822 uint32_t mpc_rmu0_mux:4; /*select mpcc on mux, one of the following : mpcc0, mpcc1, mpcc2, mpcc3*/ 823 uint32_t mpc_rmu1_mux:4; 824 uint32_t mpc_rmu2_mux:4; 825 uint32_t reserved:15; 826 } bits; 827 uint32_t raw; 828 }; 829 830 831 struct dc_3dlut { 832 struct kref refcount; 833 struct tetrahedral_params lut_3d; 834 struct fixed31_32 hdr_multiplier; 835 union dc_3dlut_state state; 836 }; 837 /* 838 * This structure is filled in by dc_surface_get_status and contains 839 * the last requested address and the currently active address so the called 840 * can determine if there are any outstanding flips 841 */ 842 struct dc_plane_status { 843 struct dc_plane_address requested_address; 844 struct dc_plane_address current_address; 845 bool is_flip_pending; 846 bool is_right_eye; 847 }; 848 849 union surface_update_flags { 850 851 struct { 852 uint32_t addr_update:1; 853 /* Medium updates */ 854 uint32_t dcc_change:1; 855 uint32_t color_space_change:1; 856 uint32_t horizontal_mirror_change:1; 857 uint32_t per_pixel_alpha_change:1; 858 uint32_t global_alpha_change:1; 859 uint32_t hdr_mult:1; 860 uint32_t rotation_change:1; 861 uint32_t swizzle_change:1; 862 uint32_t scaling_change:1; 863 uint32_t position_change:1; 864 uint32_t in_transfer_func_change:1; 865 uint32_t input_csc_change:1; 866 uint32_t coeff_reduction_change:1; 867 uint32_t output_tf_change:1; 868 uint32_t pixel_format_change:1; 869 uint32_t plane_size_change:1; 870 uint32_t gamut_remap_change:1; 871 872 /* Full updates */ 873 uint32_t new_plane:1; 874 uint32_t bpp_change:1; 875 uint32_t gamma_change:1; 876 uint32_t bandwidth_change:1; 877 uint32_t clock_change:1; 878 uint32_t stereo_format_change:1; 879 uint32_t full_update:1; 880 } bits; 881 882 uint32_t raw; 883 }; 884 885 struct dc_plane_state { 886 struct dc_plane_address address; 887 struct dc_plane_flip_time time; 888 bool triplebuffer_flips; 889 struct scaling_taps scaling_quality; 890 struct rect src_rect; 891 struct rect dst_rect; 892 struct rect clip_rect; 893 894 struct plane_size plane_size; 895 union dc_tiling_info tiling_info; 896 897 struct dc_plane_dcc_param dcc; 898 899 struct dc_gamma *gamma_correction; 900 struct dc_transfer_func *in_transfer_func; 901 struct dc_bias_and_scale *bias_and_scale; 902 struct dc_csc_transform input_csc_color_matrix; 903 struct fixed31_32 coeff_reduction_factor; 904 struct fixed31_32 hdr_mult; 905 struct colorspace_transform gamut_remap_matrix; 906 907 // TODO: No longer used, remove 908 struct dc_hdr_static_metadata hdr_static_ctx; 909 910 enum dc_color_space color_space; 911 912 struct dc_3dlut *lut3d_func; 913 struct dc_transfer_func *in_shaper_func; 914 struct dc_transfer_func *blend_tf; 915 916 #if defined(CONFIG_DRM_AMD_DC_DCN) 917 struct dc_transfer_func *gamcor_tf; 918 #endif 919 enum surface_pixel_format format; 920 enum dc_rotation_angle rotation; 921 enum plane_stereo_format stereo_format; 922 923 bool is_tiling_rotated; 924 bool per_pixel_alpha; 925 bool global_alpha; 926 int global_alpha_value; 927 bool visible; 928 bool flip_immediate; 929 bool horizontal_mirror; 930 int layer_index; 931 932 union surface_update_flags update_flags; 933 bool flip_int_enabled; 934 bool skip_manual_trigger; 935 936 /* private to DC core */ 937 struct dc_plane_status status; 938 struct dc_context *ctx; 939 940 /* HACK: Workaround for forcing full reprogramming under some conditions */ 941 bool force_full_update; 942 943 /* private to dc_surface.c */ 944 enum dc_irq_source irq_source; 945 struct kref refcount; 946 }; 947 948 struct dc_plane_info { 949 struct plane_size plane_size; 950 union dc_tiling_info tiling_info; 951 struct dc_plane_dcc_param dcc; 952 enum surface_pixel_format format; 953 enum dc_rotation_angle rotation; 954 enum plane_stereo_format stereo_format; 955 enum dc_color_space color_space; 956 bool horizontal_mirror; 957 bool visible; 958 bool per_pixel_alpha; 959 bool global_alpha; 960 int global_alpha_value; 961 bool input_csc_enabled; 962 int layer_index; 963 }; 964 965 struct dc_scaling_info { 966 struct rect src_rect; 967 struct rect dst_rect; 968 struct rect clip_rect; 969 struct scaling_taps scaling_quality; 970 }; 971 972 struct dc_surface_update { 973 struct dc_plane_state *surface; 974 975 /* isr safe update parameters. null means no updates */ 976 const struct dc_flip_addrs *flip_addr; 977 const struct dc_plane_info *plane_info; 978 const struct dc_scaling_info *scaling_info; 979 struct fixed31_32 hdr_mult; 980 /* following updates require alloc/sleep/spin that is not isr safe, 981 * null means no updates 982 */ 983 const struct dc_gamma *gamma; 984 const struct dc_transfer_func *in_transfer_func; 985 986 const struct dc_csc_transform *input_csc_color_matrix; 987 const struct fixed31_32 *coeff_reduction_factor; 988 const struct dc_transfer_func *func_shaper; 989 const struct dc_3dlut *lut3d_func; 990 const struct dc_transfer_func *blend_tf; 991 const struct colorspace_transform *gamut_remap_matrix; 992 }; 993 994 /* 995 * Create a new surface with default parameters; 996 */ 997 struct dc_plane_state *dc_create_plane_state(struct dc *dc); 998 const struct dc_plane_status *dc_plane_get_status( 999 const struct dc_plane_state *plane_state); 1000 1001 void dc_plane_state_retain(struct dc_plane_state *plane_state); 1002 void dc_plane_state_release(struct dc_plane_state *plane_state); 1003 1004 void dc_gamma_retain(struct dc_gamma *dc_gamma); 1005 void dc_gamma_release(struct dc_gamma **dc_gamma); 1006 struct dc_gamma *dc_create_gamma(void); 1007 1008 void dc_transfer_func_retain(struct dc_transfer_func *dc_tf); 1009 void dc_transfer_func_release(struct dc_transfer_func *dc_tf); 1010 struct dc_transfer_func *dc_create_transfer_func(void); 1011 1012 struct dc_3dlut *dc_create_3dlut_func(void); 1013 void dc_3dlut_func_release(struct dc_3dlut *lut); 1014 void dc_3dlut_func_retain(struct dc_3dlut *lut); 1015 /* 1016 * This structure holds a surface address. There could be multiple addresses 1017 * in cases such as Stereo 3D, Planar YUV, etc. Other per-flip attributes such 1018 * as frame durations and DCC format can also be set. 1019 */ 1020 struct dc_flip_addrs { 1021 struct dc_plane_address address; 1022 unsigned int flip_timestamp_in_us; 1023 bool flip_immediate; 1024 /* TODO: add flip duration for FreeSync */ 1025 bool triplebuffer_flips; 1026 }; 1027 1028 void dc_post_update_surfaces_to_stream( 1029 struct dc *dc); 1030 1031 #include "dc_stream.h" 1032 1033 /* 1034 * Structure to store surface/stream associations for validation 1035 */ 1036 struct dc_validation_set { 1037 struct dc_stream_state *stream; 1038 struct dc_plane_state *plane_states[MAX_SURFACES]; 1039 uint8_t plane_count; 1040 }; 1041 1042 bool dc_validate_seamless_boot_timing(const struct dc *dc, 1043 const struct dc_sink *sink, 1044 struct dc_crtc_timing *crtc_timing); 1045 1046 enum dc_status dc_validate_plane(struct dc *dc, const struct dc_plane_state *plane_state); 1047 1048 void get_clock_requirements_for_state(struct dc_state *state, struct AsicStateEx *info); 1049 1050 bool dc_set_generic_gpio_for_stereo(bool enable, 1051 struct gpio_service *gpio_service); 1052 1053 /* 1054 * fast_validate: we return after determining if we can support the new state, 1055 * but before we populate the programming info 1056 */ 1057 enum dc_status dc_validate_global_state( 1058 struct dc *dc, 1059 struct dc_state *new_ctx, 1060 bool fast_validate); 1061 1062 1063 void dc_resource_state_construct( 1064 const struct dc *dc, 1065 struct dc_state *dst_ctx); 1066 1067 #if defined(CONFIG_DRM_AMD_DC_DCN) 1068 bool dc_acquire_release_mpc_3dlut( 1069 struct dc *dc, bool acquire, 1070 struct dc_stream_state *stream, 1071 struct dc_3dlut **lut, 1072 struct dc_transfer_func **shaper); 1073 #endif 1074 1075 void dc_resource_state_copy_construct( 1076 const struct dc_state *src_ctx, 1077 struct dc_state *dst_ctx); 1078 1079 void dc_resource_state_copy_construct_current( 1080 const struct dc *dc, 1081 struct dc_state *dst_ctx); 1082 1083 void dc_resource_state_destruct(struct dc_state *context); 1084 1085 bool dc_resource_is_dsc_encoding_supported(const struct dc *dc); 1086 1087 /* 1088 * TODO update to make it about validation sets 1089 * Set up streams and links associated to drive sinks 1090 * The streams parameter is an absolute set of all active streams. 1091 * 1092 * After this call: 1093 * Phy, Encoder, Timing Generator are programmed and enabled. 1094 * New streams are enabled with blank stream; no memory read. 1095 */ 1096 bool dc_commit_state(struct dc *dc, struct dc_state *context); 1097 1098 struct dc_state *dc_create_state(struct dc *dc); 1099 struct dc_state *dc_copy_state(struct dc_state *src_ctx); 1100 void dc_retain_state(struct dc_state *context); 1101 void dc_release_state(struct dc_state *context); 1102 1103 /******************************************************************************* 1104 * Link Interfaces 1105 ******************************************************************************/ 1106 1107 struct dpcd_caps { 1108 union dpcd_rev dpcd_rev; 1109 union max_lane_count max_ln_count; 1110 union max_down_spread max_down_spread; 1111 union dprx_feature dprx_feature; 1112 1113 /* valid only for eDP v1.4 or higher*/ 1114 uint8_t edp_supported_link_rates_count; 1115 enum dc_link_rate edp_supported_link_rates[8]; 1116 1117 /* dongle type (DP converter, CV smart dongle) */ 1118 enum display_dongle_type dongle_type; 1119 /* branch device or sink device */ 1120 bool is_branch_dev; 1121 /* Dongle's downstream count. */ 1122 union sink_count sink_count; 1123 /* If dongle_type == DISPLAY_DONGLE_DP_HDMI_CONVERTER, 1124 indicates 'Frame Sequential-to-lllFrame Pack' conversion capability.*/ 1125 struct dc_dongle_caps dongle_caps; 1126 1127 uint32_t sink_dev_id; 1128 int8_t sink_dev_id_str[6]; 1129 int8_t sink_hw_revision; 1130 int8_t sink_fw_revision[2]; 1131 1132 uint32_t branch_dev_id; 1133 int8_t branch_dev_name[6]; 1134 int8_t branch_hw_revision; 1135 int8_t branch_fw_revision[2]; 1136 1137 bool allow_invalid_MSA_timing_param; 1138 bool panel_mode_edp; 1139 bool dpcd_display_control_capable; 1140 bool ext_receiver_cap_field_present; 1141 bool dynamic_backlight_capable_edp; 1142 union dpcd_fec_capability fec_cap; 1143 struct dpcd_dsc_capabilities dsc_caps; 1144 struct dc_lttpr_caps lttpr_caps; 1145 struct psr_caps psr_caps; 1146 1147 }; 1148 1149 union dpcd_sink_ext_caps { 1150 struct { 1151 /* 0 - Sink supports backlight adjust via PWM during SDR/HDR mode 1152 * 1 - Sink supports backlight adjust via AUX during SDR/HDR mode. 1153 */ 1154 uint8_t sdr_aux_backlight_control : 1; 1155 uint8_t hdr_aux_backlight_control : 1; 1156 uint8_t reserved_1 : 2; 1157 uint8_t oled : 1; 1158 uint8_t reserved : 3; 1159 } bits; 1160 uint8_t raw; 1161 }; 1162 1163 #if defined(CONFIG_DRM_AMD_DC_HDCP) 1164 union hdcp_rx_caps { 1165 struct { 1166 uint8_t version; 1167 uint8_t reserved; 1168 struct { 1169 uint8_t repeater : 1; 1170 uint8_t hdcp_capable : 1; 1171 uint8_t reserved : 6; 1172 } byte0; 1173 } fields; 1174 uint8_t raw[3]; 1175 }; 1176 1177 union hdcp_bcaps { 1178 struct { 1179 uint8_t HDCP_CAPABLE:1; 1180 uint8_t REPEATER:1; 1181 uint8_t RESERVED:6; 1182 } bits; 1183 uint8_t raw; 1184 }; 1185 1186 struct hdcp_caps { 1187 union hdcp_rx_caps rx_caps; 1188 union hdcp_bcaps bcaps; 1189 }; 1190 #endif 1191 1192 #include "dc_link.h" 1193 1194 #if defined(CONFIG_DRM_AMD_DC_DCN) 1195 uint32_t dc_get_opp_for_plane(struct dc *dc, struct dc_plane_state *plane); 1196 1197 #endif 1198 /******************************************************************************* 1199 * Sink Interfaces - A sink corresponds to a display output device 1200 ******************************************************************************/ 1201 1202 struct dc_container_id { 1203 // 128bit GUID in binary form 1204 unsigned char guid[16]; 1205 // 8 byte port ID -> ELD.PortID 1206 unsigned int portId[2]; 1207 // 128bit GUID in binary formufacturer name -> ELD.ManufacturerName 1208 unsigned short manufacturerName; 1209 // 2 byte product code -> ELD.ProductCode 1210 unsigned short productCode; 1211 }; 1212 1213 1214 struct dc_sink_dsc_caps { 1215 // 'true' if these are virtual DPCD's DSC caps (immediately upstream of sink in MST topology), 1216 // 'false' if they are sink's DSC caps 1217 bool is_virtual_dpcd_dsc; 1218 struct dsc_dec_dpcd_caps dsc_dec_caps; 1219 }; 1220 1221 struct dc_sink_fec_caps { 1222 bool is_rx_fec_supported; 1223 bool is_topology_fec_supported; 1224 }; 1225 1226 /* 1227 * The sink structure contains EDID and other display device properties 1228 */ 1229 struct dc_sink { 1230 enum signal_type sink_signal; 1231 struct dc_edid dc_edid; /* raw edid */ 1232 struct dc_edid_caps edid_caps; /* parse display caps */ 1233 struct dc_container_id *dc_container_id; 1234 uint32_t dongle_max_pix_clk; 1235 void *priv; 1236 struct stereo_3d_features features_3d[TIMING_3D_FORMAT_MAX]; 1237 bool converter_disable_audio; 1238 1239 struct dc_sink_dsc_caps dsc_caps; 1240 struct dc_sink_fec_caps fec_caps; 1241 1242 bool is_vsc_sdp_colorimetry_supported; 1243 1244 /* private to DC core */ 1245 struct dc_link *link; 1246 struct dc_context *ctx; 1247 1248 uint32_t sink_id; 1249 1250 /* private to dc_sink.c */ 1251 // refcount must be the last member in dc_sink, since we want the 1252 // sink structure to be logically cloneable up to (but not including) 1253 // refcount 1254 struct kref refcount; 1255 }; 1256 1257 void dc_sink_retain(struct dc_sink *sink); 1258 void dc_sink_release(struct dc_sink *sink); 1259 1260 struct dc_sink_init_data { 1261 enum signal_type sink_signal; 1262 struct dc_link *link; 1263 uint32_t dongle_max_pix_clk; 1264 bool converter_disable_audio; 1265 }; 1266 1267 struct dc_sink *dc_sink_create(const struct dc_sink_init_data *init_params); 1268 1269 /* Newer interfaces */ 1270 struct dc_cursor { 1271 struct dc_plane_address address; 1272 struct dc_cursor_attributes attributes; 1273 }; 1274 1275 1276 /******************************************************************************* 1277 * Interrupt interfaces 1278 ******************************************************************************/ 1279 enum dc_irq_source dc_interrupt_to_irq_source( 1280 struct dc *dc, 1281 uint32_t src_id, 1282 uint32_t ext_id); 1283 bool dc_interrupt_set(struct dc *dc, enum dc_irq_source src, bool enable); 1284 void dc_interrupt_ack(struct dc *dc, enum dc_irq_source src); 1285 enum dc_irq_source dc_get_hpd_irq_source_at_index( 1286 struct dc *dc, uint32_t link_index); 1287 1288 /******************************************************************************* 1289 * Power Interfaces 1290 ******************************************************************************/ 1291 1292 void dc_set_power_state( 1293 struct dc *dc, 1294 enum dc_acpi_cm_power_state power_state); 1295 void dc_resume(struct dc *dc); 1296 1297 void dc_power_down_on_boot(struct dc *dc); 1298 1299 #if defined(CONFIG_DRM_AMD_DC_HDCP) 1300 /* 1301 * HDCP Interfaces 1302 */ 1303 enum hdcp_message_status dc_process_hdcp_msg( 1304 enum signal_type signal, 1305 struct dc_link *link, 1306 struct hdcp_protection_message *message_info); 1307 #endif 1308 bool dc_is_dmcu_initialized(struct dc *dc); 1309 1310 enum dc_status dc_set_clock(struct dc *dc, enum dc_clock_type clock_type, uint32_t clk_khz, uint32_t stepping); 1311 void dc_get_clock(struct dc *dc, enum dc_clock_type clock_type, struct dc_clock_config *clock_cfg); 1312 #if defined(CONFIG_DRM_AMD_DC_DCN) 1313 1314 bool dc_is_plane_eligible_for_idle_optimizations(struct dc *dc, struct dc_plane_state *plane, 1315 struct dc_cursor_attributes *cursor_attr); 1316 1317 void dc_allow_idle_optimizations(struct dc *dc, bool allow); 1318 1319 /* 1320 * blank all streams, and set min and max memory clock to 1321 * lowest and highest DPM level, respectively 1322 */ 1323 void dc_unlock_memory_clock_frequency(struct dc *dc); 1324 1325 /* 1326 * set min memory clock to the min required for current mode, 1327 * max to maxDPM, and unblank streams 1328 */ 1329 void dc_lock_memory_clock_frequency(struct dc *dc); 1330 1331 /* cleanup on driver unload */ 1332 void dc_hardware_release(struct dc *dc); 1333 1334 #endif 1335 1336 bool dc_set_psr_allow_active(struct dc *dc, bool enable); 1337 #if defined(CONFIG_DRM_AMD_DC_DCN3_1) 1338 void dc_z10_restore(struct dc *dc); 1339 #endif 1340 1341 bool dc_enable_dmub_notifications(struct dc *dc); 1342 1343 bool dc_process_dmub_aux_transfer_async(struct dc *dc, 1344 uint32_t link_index, 1345 struct aux_payload *payload); 1346 1347 /******************************************************************************* 1348 * DSC Interfaces 1349 ******************************************************************************/ 1350 #include "dc_dsc.h" 1351 1352 /******************************************************************************* 1353 * Disable acc mode Interfaces 1354 ******************************************************************************/ 1355 void dc_disable_accelerated_mode(struct dc *dc); 1356 1357 #endif /* DC_INTERFACE_H_ */ 1358