1 /* 2 * Copyright 2012-14 Advanced Micro Devices, Inc. 3 * 4 * Permission is hereby granted, free of charge, to any person obtaining a 5 * copy of this software and associated documentation files (the "Software"), 6 * to deal in the Software without restriction, including without limitation 7 * the rights to use, copy, modify, merge, publish, distribute, sublicense, 8 * and/or sell copies of the Software, and to permit persons to whom the 9 * Software is furnished to do so, subject to the following conditions: 10 * 11 * The above copyright notice and this permission notice shall be included in 12 * all copies or substantial portions of the Software. 13 * 14 * THE SOFTWARE IS PROVIDED "AS IS", WITHOUT WARRANTY OF ANY KIND, EXPRESS OR 15 * IMPLIED, INCLUDING BUT NOT LIMITED TO THE WARRANTIES OF MERCHANTABILITY, 16 * FITNESS FOR A PARTICULAR PURPOSE AND NONINFRINGEMENT. IN NO EVENT SHALL 17 * THE COPYRIGHT HOLDER(S) OR AUTHOR(S) BE LIABLE FOR ANY CLAIM, DAMAGES OR 18 * OTHER LIABILITY, WHETHER IN AN ACTION OF CONTRACT, TORT OR OTHERWISE, 19 * ARISING FROM, OUT OF OR IN CONNECTION WITH THE SOFTWARE OR THE USE OR 20 * OTHER DEALINGS IN THE SOFTWARE. 21 * 22 * Authors: AMD 23 * 24 */ 25 26 #ifndef DC_INTERFACE_H_ 27 #define DC_INTERFACE_H_ 28 29 #include "dc_types.h" 30 #include "grph_object_defs.h" 31 #include "logger_types.h" 32 #include "gpio_types.h" 33 #include "link_service_types.h" 34 #include "grph_object_ctrl_defs.h" 35 #include <inc/hw/opp.h> 36 37 #include "inc/hw_sequencer.h" 38 #include "inc/compressor.h" 39 #include "dml/display_mode_lib.h" 40 41 #define DC_VER "3.1.20" 42 43 #define MAX_SURFACES 3 44 #define MAX_STREAMS 6 45 #define MAX_SINKS_PER_LINK 4 46 47 48 /******************************************************************************* 49 * Display Core Interfaces 50 ******************************************************************************/ 51 struct dc_caps { 52 uint32_t max_streams; 53 uint32_t max_links; 54 uint32_t max_audios; 55 uint32_t max_slave_planes; 56 uint32_t max_planes; 57 uint32_t max_downscale_ratio; 58 uint32_t i2c_speed_in_khz; 59 unsigned int max_cursor_size; 60 unsigned int max_video_width; 61 int linear_pitch_alignment; 62 bool dcc_const_color; 63 bool dynamic_audio; 64 bool is_apu; 65 }; 66 67 struct dc_dcc_surface_param { 68 struct dc_size surface_size; 69 enum surface_pixel_format format; 70 enum swizzle_mode_values swizzle_mode; 71 enum dc_scan_direction scan; 72 }; 73 74 struct dc_dcc_setting { 75 unsigned int max_compressed_blk_size; 76 unsigned int max_uncompressed_blk_size; 77 bool independent_64b_blks; 78 }; 79 80 struct dc_surface_dcc_cap { 81 union { 82 struct { 83 struct dc_dcc_setting rgb; 84 } grph; 85 86 struct { 87 struct dc_dcc_setting luma; 88 struct dc_dcc_setting chroma; 89 } video; 90 }; 91 92 bool capable; 93 bool const_color_support; 94 }; 95 96 struct dc_static_screen_events { 97 bool cursor_update; 98 bool surface_update; 99 bool overlay_update; 100 }; 101 102 103 /* Surface update type is used by dc_update_surfaces_and_stream 104 * The update type is determined at the very beginning of the function based 105 * on parameters passed in and decides how much programming (or updating) is 106 * going to be done during the call. 107 * 108 * UPDATE_TYPE_FAST is used for really fast updates that do not require much 109 * logical calculations or hardware register programming. This update MUST be 110 * ISR safe on windows. Currently fast update will only be used to flip surface 111 * address. 112 * 113 * UPDATE_TYPE_MED is used for slower updates which require significant hw 114 * re-programming however do not affect bandwidth consumption or clock 115 * requirements. At present, this is the level at which front end updates 116 * that do not require us to run bw_calcs happen. These are in/out transfer func 117 * updates, viewport offset changes, recout size changes and pixel depth changes. 118 * This update can be done at ISR, but we want to minimize how often this happens. 119 * 120 * UPDATE_TYPE_FULL is slow. Really slow. This requires us to recalculate our 121 * bandwidth and clocks, possibly rearrange some pipes and reprogram anything front 122 * end related. Any time viewport dimensions, recout dimensions, scaling ratios or 123 * gamma need to be adjusted or pipe needs to be turned on (or disconnected) we do 124 * a full update. This cannot be done at ISR level and should be a rare event. 125 * Unless someone is stress testing mpo enter/exit, playing with colour or adjusting 126 * underscan we don't expect to see this call at all. 127 */ 128 129 enum surface_update_type { 130 UPDATE_TYPE_FAST, /* super fast, safe to execute in isr */ 131 UPDATE_TYPE_MED, /* ISR safe, most of programming needed, no bw/clk change*/ 132 UPDATE_TYPE_FULL, /* may need to shuffle resources */ 133 }; 134 135 /* Forward declaration*/ 136 struct dc; 137 struct dc_plane_state; 138 struct dc_state; 139 140 141 struct dc_cap_funcs { 142 bool (*get_dcc_compression_cap)(const struct dc *dc, 143 const struct dc_dcc_surface_param *input, 144 struct dc_surface_dcc_cap *output); 145 }; 146 147 struct link_training_settings; 148 149 150 /* Structure to hold configuration flags set by dm at dc creation. */ 151 struct dc_config { 152 bool gpu_vm_support; 153 bool disable_disp_pll_sharing; 154 }; 155 156 enum dcc_option { 157 DCC_ENABLE = 0, 158 DCC_DISABLE = 1, 159 DCC_HALF_REQ_DISALBE = 2, 160 }; 161 162 enum pipe_split_policy { 163 MPC_SPLIT_DYNAMIC = 0, 164 MPC_SPLIT_AVOID = 1, 165 MPC_SPLIT_AVOID_MULT_DISP = 2, 166 }; 167 168 enum wm_report_mode { 169 WM_REPORT_DEFAULT = 0, 170 WM_REPORT_OVERRIDE = 1, 171 }; 172 173 struct dc_debug { 174 bool surface_visual_confirm; 175 bool sanity_checks; 176 bool max_disp_clk; 177 bool surface_trace; 178 bool timing_trace; 179 bool clock_trace; 180 bool validation_trace; 181 182 /* stutter efficiency related */ 183 bool disable_stutter; 184 bool use_max_lb; 185 enum dcc_option disable_dcc; 186 enum pipe_split_policy pipe_split_policy; 187 bool force_single_disp_pipe_split; 188 bool voltage_align_fclk; 189 190 bool disable_dfs_bypass; 191 bool disable_dpp_power_gate; 192 bool disable_hubp_power_gate; 193 bool disable_pplib_wm_range; 194 enum wm_report_mode pplib_wm_report_mode; 195 unsigned int min_disp_clk_khz; 196 int sr_exit_time_dpm0_ns; 197 int sr_enter_plus_exit_time_dpm0_ns; 198 int sr_exit_time_ns; 199 int sr_enter_plus_exit_time_ns; 200 int urgent_latency_ns; 201 int percent_of_ideal_drambw; 202 int dram_clock_change_latency_ns; 203 int always_scale; 204 bool disable_pplib_clock_request; 205 bool disable_clock_gate; 206 bool disable_dmcu; 207 bool disable_psr; 208 bool force_abm_enable; 209 bool disable_hbup_pg; 210 bool disable_dpp_pg; 211 bool disable_stereo_support; 212 bool vsr_support; 213 bool performance_trace; 214 }; 215 struct dc_state; 216 struct resource_pool; 217 struct dce_hwseq; 218 struct dc { 219 struct dc_caps caps; 220 struct dc_cap_funcs cap_funcs; 221 struct dc_config config; 222 struct dc_debug debug; 223 224 struct dc_context *ctx; 225 226 uint8_t link_count; 227 struct dc_link *links[MAX_PIPES * 2]; 228 229 struct dc_state *current_state; 230 struct resource_pool *res_pool; 231 232 /* Display Engine Clock levels */ 233 struct dm_pp_clock_levels sclk_lvls; 234 235 /* Inputs into BW and WM calculations. */ 236 struct bw_calcs_dceip *bw_dceip; 237 struct bw_calcs_vbios *bw_vbios; 238 #ifdef CONFIG_DRM_AMD_DC_DCN1_0 239 struct dcn_soc_bounding_box *dcn_soc; 240 struct dcn_ip_params *dcn_ip; 241 struct display_mode_lib dml; 242 #endif 243 244 /* HW functions */ 245 struct hw_sequencer_funcs hwss; 246 struct dce_hwseq *hwseq; 247 248 /* temp store of dm_pp_display_configuration 249 * to compare to see if display config changed 250 */ 251 struct dm_pp_display_configuration prev_display_config; 252 253 /* FBC compressor */ 254 #if defined(CONFIG_DRM_AMD_DC_FBC) 255 struct compressor *fbc_compressor; 256 #endif 257 }; 258 259 enum frame_buffer_mode { 260 FRAME_BUFFER_MODE_LOCAL_ONLY = 0, 261 FRAME_BUFFER_MODE_ZFB_ONLY, 262 FRAME_BUFFER_MODE_MIXED_ZFB_AND_LOCAL, 263 } ; 264 265 struct dchub_init_data { 266 int64_t zfb_phys_addr_base; 267 int64_t zfb_mc_base_addr; 268 uint64_t zfb_size_in_byte; 269 enum frame_buffer_mode fb_mode; 270 bool dchub_initialzied; 271 bool dchub_info_valid; 272 }; 273 274 struct dc_init_data { 275 struct hw_asic_id asic_id; 276 void *driver; /* ctx */ 277 struct cgs_device *cgs_device; 278 279 int num_virtual_links; 280 /* 281 * If 'vbios_override' not NULL, it will be called instead 282 * of the real VBIOS. Intended use is Diagnostics on FPGA. 283 */ 284 struct dc_bios *vbios_override; 285 enum dce_environment dce_environment; 286 287 struct dc_config flags; 288 uint32_t log_mask; 289 #if defined(CONFIG_DRM_AMD_DC_FBC) 290 uint64_t fbc_gpu_addr; 291 #endif 292 }; 293 294 struct dc *dc_create(const struct dc_init_data *init_params); 295 296 void dc_destroy(struct dc **dc); 297 298 /******************************************************************************* 299 * Surface Interfaces 300 ******************************************************************************/ 301 302 enum { 303 TRANSFER_FUNC_POINTS = 1025 304 }; 305 306 // Moved here from color module for linux 307 enum color_transfer_func { 308 transfer_func_unknown, 309 transfer_func_srgb, 310 transfer_func_bt709, 311 transfer_func_pq2084, 312 transfer_func_pq2084_interim, 313 transfer_func_linear_0_1, 314 transfer_func_linear_0_125, 315 transfer_func_dolbyvision, 316 transfer_func_gamma_22, 317 transfer_func_gamma_26 318 }; 319 320 struct dc_hdr_static_metadata { 321 /* display chromaticities and white point in units of 0.00001 */ 322 unsigned int chromaticity_green_x; 323 unsigned int chromaticity_green_y; 324 unsigned int chromaticity_blue_x; 325 unsigned int chromaticity_blue_y; 326 unsigned int chromaticity_red_x; 327 unsigned int chromaticity_red_y; 328 unsigned int chromaticity_white_point_x; 329 unsigned int chromaticity_white_point_y; 330 331 uint32_t min_luminance; 332 uint32_t max_luminance; 333 uint32_t maximum_content_light_level; 334 uint32_t maximum_frame_average_light_level; 335 336 bool hdr_supported; 337 bool is_hdr; 338 }; 339 340 enum dc_transfer_func_type { 341 TF_TYPE_PREDEFINED, 342 TF_TYPE_DISTRIBUTED_POINTS, 343 TF_TYPE_BYPASS 344 }; 345 346 struct dc_transfer_func_distributed_points { 347 struct fixed31_32 red[TRANSFER_FUNC_POINTS]; 348 struct fixed31_32 green[TRANSFER_FUNC_POINTS]; 349 struct fixed31_32 blue[TRANSFER_FUNC_POINTS]; 350 351 uint16_t end_exponent; 352 uint16_t x_point_at_y1_red; 353 uint16_t x_point_at_y1_green; 354 uint16_t x_point_at_y1_blue; 355 }; 356 357 enum dc_transfer_func_predefined { 358 TRANSFER_FUNCTION_SRGB, 359 TRANSFER_FUNCTION_BT709, 360 TRANSFER_FUNCTION_PQ, 361 TRANSFER_FUNCTION_LINEAR, 362 }; 363 364 struct dc_transfer_func { 365 struct kref refcount; 366 struct dc_transfer_func_distributed_points tf_pts; 367 enum dc_transfer_func_type type; 368 enum dc_transfer_func_predefined tf; 369 struct dc_context *ctx; 370 }; 371 372 /* 373 * This structure is filled in by dc_surface_get_status and contains 374 * the last requested address and the currently active address so the called 375 * can determine if there are any outstanding flips 376 */ 377 struct dc_plane_status { 378 struct dc_plane_address requested_address; 379 struct dc_plane_address current_address; 380 bool is_flip_pending; 381 bool is_right_eye; 382 }; 383 384 union surface_update_flags { 385 386 struct { 387 /* Medium updates */ 388 uint32_t color_space_change:1; 389 uint32_t input_tf_change:1; 390 uint32_t horizontal_mirror_change:1; 391 uint32_t per_pixel_alpha_change:1; 392 uint32_t rotation_change:1; 393 uint32_t swizzle_change:1; 394 uint32_t scaling_change:1; 395 uint32_t position_change:1; 396 uint32_t in_transfer_func:1; 397 uint32_t input_csc_change:1; 398 399 /* Full updates */ 400 uint32_t new_plane:1; 401 uint32_t bpp_change:1; 402 uint32_t bandwidth_change:1; 403 uint32_t clock_change:1; 404 uint32_t stereo_format_change:1; 405 uint32_t full_update:1; 406 } bits; 407 408 uint32_t raw; 409 }; 410 411 struct dc_plane_state { 412 struct dc_plane_address address; 413 struct scaling_taps scaling_quality; 414 struct rect src_rect; 415 struct rect dst_rect; 416 struct rect clip_rect; 417 418 union plane_size plane_size; 419 union dc_tiling_info tiling_info; 420 421 struct dc_plane_dcc_param dcc; 422 423 struct dc_gamma *gamma_correction; 424 struct dc_transfer_func *in_transfer_func; 425 struct dc_bias_and_scale *bias_and_scale; 426 struct csc_transform input_csc_color_matrix; 427 struct fixed31_32 coeff_reduction_factor; 428 429 // TODO: No longer used, remove 430 struct dc_hdr_static_metadata hdr_static_ctx; 431 432 enum dc_color_space color_space; 433 enum color_transfer_func input_tf; 434 435 enum surface_pixel_format format; 436 enum dc_rotation_angle rotation; 437 enum plane_stereo_format stereo_format; 438 439 bool per_pixel_alpha; 440 bool visible; 441 bool flip_immediate; 442 bool horizontal_mirror; 443 444 union surface_update_flags update_flags; 445 /* private to DC core */ 446 struct dc_plane_status status; 447 struct dc_context *ctx; 448 449 /* private to dc_surface.c */ 450 enum dc_irq_source irq_source; 451 struct kref refcount; 452 }; 453 454 struct dc_plane_info { 455 union plane_size plane_size; 456 union dc_tiling_info tiling_info; 457 struct dc_plane_dcc_param dcc; 458 enum surface_pixel_format format; 459 enum dc_rotation_angle rotation; 460 enum plane_stereo_format stereo_format; 461 enum dc_color_space color_space; 462 enum color_transfer_func input_tf; 463 bool horizontal_mirror; 464 bool visible; 465 bool per_pixel_alpha; 466 bool input_csc_enabled; 467 }; 468 469 struct dc_scaling_info { 470 struct rect src_rect; 471 struct rect dst_rect; 472 struct rect clip_rect; 473 struct scaling_taps scaling_quality; 474 }; 475 476 struct dc_surface_update { 477 struct dc_plane_state *surface; 478 479 /* isr safe update parameters. null means no updates */ 480 struct dc_flip_addrs *flip_addr; 481 struct dc_plane_info *plane_info; 482 struct dc_scaling_info *scaling_info; 483 484 /* following updates require alloc/sleep/spin that is not isr safe, 485 * null means no updates 486 */ 487 /* gamma TO BE REMOVED */ 488 struct dc_gamma *gamma; 489 enum color_transfer_func color_input_tf; 490 enum color_transfer_func color_output_tf; 491 struct dc_transfer_func *in_transfer_func; 492 493 struct csc_transform *input_csc_color_matrix; 494 struct fixed31_32 *coeff_reduction_factor; 495 }; 496 497 /* 498 * Create a new surface with default parameters; 499 */ 500 struct dc_plane_state *dc_create_plane_state(struct dc *dc); 501 const struct dc_plane_status *dc_plane_get_status( 502 const struct dc_plane_state *plane_state); 503 504 void dc_plane_state_retain(struct dc_plane_state *plane_state); 505 void dc_plane_state_release(struct dc_plane_state *plane_state); 506 507 void dc_gamma_retain(struct dc_gamma *dc_gamma); 508 void dc_gamma_release(struct dc_gamma **dc_gamma); 509 struct dc_gamma *dc_create_gamma(void); 510 511 void dc_transfer_func_retain(struct dc_transfer_func *dc_tf); 512 void dc_transfer_func_release(struct dc_transfer_func *dc_tf); 513 struct dc_transfer_func *dc_create_transfer_func(void); 514 515 /* 516 * This structure holds a surface address. There could be multiple addresses 517 * in cases such as Stereo 3D, Planar YUV, etc. Other per-flip attributes such 518 * as frame durations and DCC format can also be set. 519 */ 520 struct dc_flip_addrs { 521 struct dc_plane_address address; 522 bool flip_immediate; 523 /* TODO: add flip duration for FreeSync */ 524 }; 525 526 bool dc_post_update_surfaces_to_stream( 527 struct dc *dc); 528 529 #include "dc_stream.h" 530 531 /* 532 * Structure to store surface/stream associations for validation 533 */ 534 struct dc_validation_set { 535 struct dc_stream_state *stream; 536 struct dc_plane_state *plane_states[MAX_SURFACES]; 537 uint8_t plane_count; 538 }; 539 540 enum dc_status dc_validate_plane(struct dc *dc, const struct dc_plane_state *plane_state); 541 542 enum dc_status dc_validate_global_state( 543 struct dc *dc, 544 struct dc_state *new_ctx); 545 546 547 void dc_resource_state_construct( 548 const struct dc *dc, 549 struct dc_state *dst_ctx); 550 551 void dc_resource_state_copy_construct( 552 const struct dc_state *src_ctx, 553 struct dc_state *dst_ctx); 554 555 void dc_resource_state_copy_construct_current( 556 const struct dc *dc, 557 struct dc_state *dst_ctx); 558 559 void dc_resource_state_destruct(struct dc_state *context); 560 561 /* 562 * TODO update to make it about validation sets 563 * Set up streams and links associated to drive sinks 564 * The streams parameter is an absolute set of all active streams. 565 * 566 * After this call: 567 * Phy, Encoder, Timing Generator are programmed and enabled. 568 * New streams are enabled with blank stream; no memory read. 569 */ 570 bool dc_commit_state(struct dc *dc, struct dc_state *context); 571 572 573 struct dc_state *dc_create_state(void); 574 void dc_retain_state(struct dc_state *context); 575 void dc_release_state(struct dc_state *context); 576 577 /******************************************************************************* 578 * Link Interfaces 579 ******************************************************************************/ 580 581 struct dpcd_caps { 582 union dpcd_rev dpcd_rev; 583 union max_lane_count max_ln_count; 584 union max_down_spread max_down_spread; 585 586 /* dongle type (DP converter, CV smart dongle) */ 587 enum display_dongle_type dongle_type; 588 /* Dongle's downstream count. */ 589 union sink_count sink_count; 590 /* If dongle_type == DISPLAY_DONGLE_DP_HDMI_CONVERTER, 591 indicates 'Frame Sequential-to-lllFrame Pack' conversion capability.*/ 592 struct dc_dongle_caps dongle_caps; 593 594 uint32_t sink_dev_id; 595 uint32_t branch_dev_id; 596 int8_t branch_dev_name[6]; 597 int8_t branch_hw_revision; 598 599 bool allow_invalid_MSA_timing_param; 600 bool panel_mode_edp; 601 bool dpcd_display_control_capable; 602 }; 603 604 #include "dc_link.h" 605 606 /******************************************************************************* 607 * Sink Interfaces - A sink corresponds to a display output device 608 ******************************************************************************/ 609 610 struct dc_container_id { 611 // 128bit GUID in binary form 612 unsigned char guid[16]; 613 // 8 byte port ID -> ELD.PortID 614 unsigned int portId[2]; 615 // 128bit GUID in binary formufacturer name -> ELD.ManufacturerName 616 unsigned short manufacturerName; 617 // 2 byte product code -> ELD.ProductCode 618 unsigned short productCode; 619 }; 620 621 622 623 /* 624 * The sink structure contains EDID and other display device properties 625 */ 626 struct dc_sink { 627 enum signal_type sink_signal; 628 struct dc_edid dc_edid; /* raw edid */ 629 struct dc_edid_caps edid_caps; /* parse display caps */ 630 struct dc_container_id *dc_container_id; 631 uint32_t dongle_max_pix_clk; 632 void *priv; 633 struct stereo_3d_features features_3d[TIMING_3D_FORMAT_MAX]; 634 bool converter_disable_audio; 635 636 /* private to DC core */ 637 struct dc_link *link; 638 struct dc_context *ctx; 639 640 /* private to dc_sink.c */ 641 struct kref refcount; 642 643 }; 644 645 void dc_sink_retain(struct dc_sink *sink); 646 void dc_sink_release(struct dc_sink *sink); 647 648 struct dc_sink_init_data { 649 enum signal_type sink_signal; 650 struct dc_link *link; 651 uint32_t dongle_max_pix_clk; 652 bool converter_disable_audio; 653 }; 654 655 struct dc_sink *dc_sink_create(const struct dc_sink_init_data *init_params); 656 657 /* Newer interfaces */ 658 struct dc_cursor { 659 struct dc_plane_address address; 660 struct dc_cursor_attributes attributes; 661 }; 662 663 /******************************************************************************* 664 * Interrupt interfaces 665 ******************************************************************************/ 666 enum dc_irq_source dc_interrupt_to_irq_source( 667 struct dc *dc, 668 uint32_t src_id, 669 uint32_t ext_id); 670 void dc_interrupt_set(struct dc *dc, enum dc_irq_source src, bool enable); 671 void dc_interrupt_ack(struct dc *dc, enum dc_irq_source src); 672 enum dc_irq_source dc_get_hpd_irq_source_at_index( 673 struct dc *dc, uint32_t link_index); 674 675 /******************************************************************************* 676 * Power Interfaces 677 ******************************************************************************/ 678 679 void dc_set_power_state( 680 struct dc *dc, 681 enum dc_acpi_cm_power_state power_state); 682 void dc_resume(struct dc *dc); 683 684 #endif /* DC_INTERFACE_H_ */ 685