1 /* 2 * Copyright 2012-14 Advanced Micro Devices, Inc. 3 * 4 * Permission is hereby granted, free of charge, to any person obtaining a 5 * copy of this software and associated documentation files (the "Software"), 6 * to deal in the Software without restriction, including without limitation 7 * the rights to use, copy, modify, merge, publish, distribute, sublicense, 8 * and/or sell copies of the Software, and to permit persons to whom the 9 * Software is furnished to do so, subject to the following conditions: 10 * 11 * The above copyright notice and this permission notice shall be included in 12 * all copies or substantial portions of the Software. 13 * 14 * THE SOFTWARE IS PROVIDED "AS IS", WITHOUT WARRANTY OF ANY KIND, EXPRESS OR 15 * IMPLIED, INCLUDING BUT NOT LIMITED TO THE WARRANTIES OF MERCHANTABILITY, 16 * FITNESS FOR A PARTICULAR PURPOSE AND NONINFRINGEMENT. IN NO EVENT SHALL 17 * THE COPYRIGHT HOLDER(S) OR AUTHOR(S) BE LIABLE FOR ANY CLAIM, DAMAGES OR 18 * OTHER LIABILITY, WHETHER IN AN ACTION OF CONTRACT, TORT OR OTHERWISE, 19 * ARISING FROM, OUT OF OR IN CONNECTION WITH THE SOFTWARE OR THE USE OR 20 * OTHER DEALINGS IN THE SOFTWARE. 21 * 22 * Authors: AMD 23 * 24 */ 25 26 #ifndef DC_INTERFACE_H_ 27 #define DC_INTERFACE_H_ 28 29 #include "dc_types.h" 30 #include "grph_object_defs.h" 31 #include "logger_types.h" 32 #if defined(CONFIG_DRM_AMD_DC_HDCP) 33 #include "hdcp_types.h" 34 #endif 35 #include "gpio_types.h" 36 #include "link_service_types.h" 37 #include "grph_object_ctrl_defs.h" 38 #include <inc/hw/opp.h> 39 40 #include "inc/hw_sequencer.h" 41 #include "inc/compressor.h" 42 #include "inc/hw/dmcu.h" 43 #include "dml/display_mode_lib.h" 44 45 #define DC_VER "3.2.104" 46 47 #define MAX_SURFACES 3 48 #define MAX_PLANES 6 49 #define MAX_STREAMS 6 50 #define MAX_SINKS_PER_LINK 4 51 52 /******************************************************************************* 53 * Display Core Interfaces 54 ******************************************************************************/ 55 struct dc_versions { 56 const char *dc_ver; 57 struct dmcu_version dmcu_version; 58 }; 59 60 enum dp_protocol_version { 61 DP_VERSION_1_4, 62 }; 63 64 enum dc_plane_type { 65 DC_PLANE_TYPE_INVALID, 66 DC_PLANE_TYPE_DCE_RGB, 67 DC_PLANE_TYPE_DCE_UNDERLAY, 68 DC_PLANE_TYPE_DCN_UNIVERSAL, 69 }; 70 71 struct dc_plane_cap { 72 enum dc_plane_type type; 73 uint32_t blends_with_above : 1; 74 uint32_t blends_with_below : 1; 75 uint32_t per_pixel_alpha : 1; 76 struct { 77 uint32_t argb8888 : 1; 78 uint32_t nv12 : 1; 79 uint32_t fp16 : 1; 80 uint32_t p010 : 1; 81 uint32_t ayuv : 1; 82 } pixel_format_support; 83 // max upscaling factor x1000 84 // upscaling factors are always >= 1 85 // for example, 1080p -> 8K is 4.0, or 4000 raw value 86 struct { 87 uint32_t argb8888; 88 uint32_t nv12; 89 uint32_t fp16; 90 } max_upscale_factor; 91 // max downscale factor x1000 92 // downscale factors are always <= 1 93 // for example, 8K -> 1080p is 0.25, or 250 raw value 94 struct { 95 uint32_t argb8888; 96 uint32_t nv12; 97 uint32_t fp16; 98 } max_downscale_factor; 99 // minimal width/height 100 uint32_t min_width; 101 uint32_t min_height; 102 }; 103 104 // Color management caps (DPP and MPC) 105 struct rom_curve_caps { 106 uint16_t srgb : 1; 107 uint16_t bt2020 : 1; 108 uint16_t gamma2_2 : 1; 109 uint16_t pq : 1; 110 uint16_t hlg : 1; 111 }; 112 113 struct dpp_color_caps { 114 uint16_t dcn_arch : 1; // all DCE generations treated the same 115 // input lut is different than most LUTs, just plain 256-entry lookup 116 uint16_t input_lut_shared : 1; // shared with DGAM 117 uint16_t icsc : 1; 118 uint16_t dgam_ram : 1; 119 uint16_t post_csc : 1; // before gamut remap 120 uint16_t gamma_corr : 1; 121 122 // hdr_mult and gamut remap always available in DPP (in that order) 123 // 3d lut implies shaper LUT, 124 // it may be shared with MPC - check MPC:shared_3d_lut flag 125 uint16_t hw_3d_lut : 1; 126 uint16_t ogam_ram : 1; // blnd gam 127 uint16_t ocsc : 1; 128 struct rom_curve_caps dgam_rom_caps; 129 struct rom_curve_caps ogam_rom_caps; 130 }; 131 132 struct mpc_color_caps { 133 uint16_t gamut_remap : 1; 134 uint16_t ogam_ram : 1; 135 uint16_t ocsc : 1; 136 uint16_t num_3dluts : 3; //3d lut always assumes a preceding shaper LUT 137 uint16_t shared_3d_lut:1; //can be in either DPP or MPC, but single instance 138 139 struct rom_curve_caps ogam_rom_caps; 140 }; 141 142 struct dc_color_caps { 143 struct dpp_color_caps dpp; 144 struct mpc_color_caps mpc; 145 }; 146 147 struct dc_caps { 148 uint32_t max_streams; 149 uint32_t max_links; 150 uint32_t max_audios; 151 uint32_t max_slave_planes; 152 uint32_t max_planes; 153 uint32_t max_downscale_ratio; 154 uint32_t i2c_speed_in_khz; 155 uint32_t dmdata_alloc_size; 156 unsigned int max_cursor_size; 157 unsigned int max_video_width; 158 int linear_pitch_alignment; 159 bool dcc_const_color; 160 bool dynamic_audio; 161 bool is_apu; 162 bool dual_link_dvi; 163 bool post_blend_color_processing; 164 bool force_dp_tps4_for_cp2520; 165 bool disable_dp_clk_share; 166 bool psp_setup_panel_mode; 167 bool extended_aux_timeout_support; 168 bool dmcub_support; 169 enum dp_protocol_version max_dp_protocol_version; 170 struct dc_plane_cap planes[MAX_PLANES]; 171 struct dc_color_caps color; 172 }; 173 174 struct dc_bug_wa { 175 bool no_connect_phy_config; 176 bool dedcn20_305_wa; 177 bool skip_clock_update; 178 bool lt_early_cr_pattern; 179 }; 180 181 struct dc_dcc_surface_param { 182 struct dc_size surface_size; 183 enum surface_pixel_format format; 184 enum swizzle_mode_values swizzle_mode; 185 enum dc_scan_direction scan; 186 }; 187 188 struct dc_dcc_setting { 189 unsigned int max_compressed_blk_size; 190 unsigned int max_uncompressed_blk_size; 191 bool independent_64b_blks; 192 #if defined(CONFIG_DRM_AMD_DC_DCN3_0) 193 //These bitfields to be used starting with DCN 3.0 194 struct { 195 uint32_t dcc_256_64_64 : 1;//available in ASICs before DCN 3.0 (the worst compression case) 196 uint32_t dcc_128_128_uncontrained : 1; //available in ASICs before DCN 3.0 197 uint32_t dcc_256_128_128 : 1; //available starting with DCN 3.0 198 uint32_t dcc_256_256_unconstrained : 1; //available in ASICs before DCN 3.0 (the best compression case) 199 } dcc_controls; 200 #endif 201 }; 202 203 struct dc_surface_dcc_cap { 204 union { 205 struct { 206 struct dc_dcc_setting rgb; 207 } grph; 208 209 struct { 210 struct dc_dcc_setting luma; 211 struct dc_dcc_setting chroma; 212 } video; 213 }; 214 215 bool capable; 216 bool const_color_support; 217 }; 218 219 struct dc_static_screen_params { 220 struct { 221 bool force_trigger; 222 bool cursor_update; 223 bool surface_update; 224 bool overlay_update; 225 } triggers; 226 unsigned int num_frames; 227 }; 228 229 230 /* Surface update type is used by dc_update_surfaces_and_stream 231 * The update type is determined at the very beginning of the function based 232 * on parameters passed in and decides how much programming (or updating) is 233 * going to be done during the call. 234 * 235 * UPDATE_TYPE_FAST is used for really fast updates that do not require much 236 * logical calculations or hardware register programming. This update MUST be 237 * ISR safe on windows. Currently fast update will only be used to flip surface 238 * address. 239 * 240 * UPDATE_TYPE_MED is used for slower updates which require significant hw 241 * re-programming however do not affect bandwidth consumption or clock 242 * requirements. At present, this is the level at which front end updates 243 * that do not require us to run bw_calcs happen. These are in/out transfer func 244 * updates, viewport offset changes, recout size changes and pixel depth changes. 245 * This update can be done at ISR, but we want to minimize how often this happens. 246 * 247 * UPDATE_TYPE_FULL is slow. Really slow. This requires us to recalculate our 248 * bandwidth and clocks, possibly rearrange some pipes and reprogram anything front 249 * end related. Any time viewport dimensions, recout dimensions, scaling ratios or 250 * gamma need to be adjusted or pipe needs to be turned on (or disconnected) we do 251 * a full update. This cannot be done at ISR level and should be a rare event. 252 * Unless someone is stress testing mpo enter/exit, playing with colour or adjusting 253 * underscan we don't expect to see this call at all. 254 */ 255 256 enum surface_update_type { 257 UPDATE_TYPE_FAST, /* super fast, safe to execute in isr */ 258 UPDATE_TYPE_MED, /* ISR safe, most of programming needed, no bw/clk change*/ 259 UPDATE_TYPE_FULL, /* may need to shuffle resources */ 260 }; 261 262 /* Forward declaration*/ 263 struct dc; 264 struct dc_plane_state; 265 struct dc_state; 266 267 268 struct dc_cap_funcs { 269 bool (*get_dcc_compression_cap)(const struct dc *dc, 270 const struct dc_dcc_surface_param *input, 271 struct dc_surface_dcc_cap *output); 272 }; 273 274 struct link_training_settings; 275 276 277 /* Structure to hold configuration flags set by dm at dc creation. */ 278 struct dc_config { 279 bool gpu_vm_support; 280 bool disable_disp_pll_sharing; 281 bool fbc_support; 282 bool optimize_edp_link_rate; 283 bool disable_fractional_pwm; 284 bool allow_seamless_boot_optimization; 285 bool power_down_display_on_boot; 286 bool edp_not_connected; 287 bool force_enum_edp; 288 bool forced_clocks; 289 bool allow_lttpr_non_transparent_mode; 290 bool multi_mon_pp_mclk_switch; 291 bool disable_dmcu; 292 bool enable_4to1MPC; 293 #if defined(CONFIG_DRM_AMD_DC_DCN3_0) 294 bool clamp_min_dcfclk; 295 #endif 296 }; 297 298 enum visual_confirm { 299 VISUAL_CONFIRM_DISABLE = 0, 300 VISUAL_CONFIRM_SURFACE = 1, 301 VISUAL_CONFIRM_HDR = 2, 302 VISUAL_CONFIRM_MPCTREE = 4, 303 VISUAL_CONFIRM_PSR = 5, 304 }; 305 306 enum dcc_option { 307 DCC_ENABLE = 0, 308 DCC_DISABLE = 1, 309 DCC_HALF_REQ_DISALBE = 2, 310 }; 311 312 enum pipe_split_policy { 313 MPC_SPLIT_DYNAMIC = 0, 314 MPC_SPLIT_AVOID = 1, 315 MPC_SPLIT_AVOID_MULT_DISP = 2, 316 }; 317 318 enum wm_report_mode { 319 WM_REPORT_DEFAULT = 0, 320 WM_REPORT_OVERRIDE = 1, 321 }; 322 enum dtm_pstate{ 323 dtm_level_p0 = 0,/*highest voltage*/ 324 dtm_level_p1, 325 dtm_level_p2, 326 dtm_level_p3, 327 dtm_level_p4,/*when active_display_count = 0*/ 328 }; 329 330 enum dcn_pwr_state { 331 DCN_PWR_STATE_UNKNOWN = -1, 332 DCN_PWR_STATE_MISSION_MODE = 0, 333 DCN_PWR_STATE_LOW_POWER = 3, 334 }; 335 336 /* 337 * For any clocks that may differ per pipe 338 * only the max is stored in this structure 339 */ 340 struct dc_clocks { 341 int dispclk_khz; 342 int dppclk_khz; 343 int disp_dpp_voltage_level_khz; 344 int dcfclk_khz; 345 int socclk_khz; 346 int dcfclk_deep_sleep_khz; 347 int fclk_khz; 348 int phyclk_khz; 349 int dramclk_khz; 350 bool p_state_change_support; 351 enum dcn_pwr_state pwr_state; 352 /* 353 * Elements below are not compared for the purposes of 354 * optimization required 355 */ 356 bool prev_p_state_change_support; 357 enum dtm_pstate dtm_level; 358 int max_supported_dppclk_khz; 359 int max_supported_dispclk_khz; 360 int bw_dppclk_khz; /*a copy of dppclk_khz*/ 361 int bw_dispclk_khz; 362 }; 363 364 struct dc_bw_validation_profile { 365 bool enable; 366 367 unsigned long long total_ticks; 368 unsigned long long voltage_level_ticks; 369 unsigned long long watermark_ticks; 370 unsigned long long rq_dlg_ticks; 371 372 unsigned long long total_count; 373 unsigned long long skip_fast_count; 374 unsigned long long skip_pass_count; 375 unsigned long long skip_fail_count; 376 }; 377 378 #define BW_VAL_TRACE_SETUP() \ 379 unsigned long long end_tick = 0; \ 380 unsigned long long voltage_level_tick = 0; \ 381 unsigned long long watermark_tick = 0; \ 382 unsigned long long start_tick = dc->debug.bw_val_profile.enable ? \ 383 dm_get_timestamp(dc->ctx) : 0 384 385 #define BW_VAL_TRACE_COUNT() \ 386 if (dc->debug.bw_val_profile.enable) \ 387 dc->debug.bw_val_profile.total_count++ 388 389 #define BW_VAL_TRACE_SKIP(status) \ 390 if (dc->debug.bw_val_profile.enable) { \ 391 if (!voltage_level_tick) \ 392 voltage_level_tick = dm_get_timestamp(dc->ctx); \ 393 dc->debug.bw_val_profile.skip_ ## status ## _count++; \ 394 } 395 396 #define BW_VAL_TRACE_END_VOLTAGE_LEVEL() \ 397 if (dc->debug.bw_val_profile.enable) \ 398 voltage_level_tick = dm_get_timestamp(dc->ctx) 399 400 #define BW_VAL_TRACE_END_WATERMARKS() \ 401 if (dc->debug.bw_val_profile.enable) \ 402 watermark_tick = dm_get_timestamp(dc->ctx) 403 404 #define BW_VAL_TRACE_FINISH() \ 405 if (dc->debug.bw_val_profile.enable) { \ 406 end_tick = dm_get_timestamp(dc->ctx); \ 407 dc->debug.bw_val_profile.total_ticks += end_tick - start_tick; \ 408 dc->debug.bw_val_profile.voltage_level_ticks += voltage_level_tick - start_tick; \ 409 if (watermark_tick) { \ 410 dc->debug.bw_val_profile.watermark_ticks += watermark_tick - voltage_level_tick; \ 411 dc->debug.bw_val_profile.rq_dlg_ticks += end_tick - watermark_tick; \ 412 } \ 413 } 414 415 struct dc_debug_options { 416 enum visual_confirm visual_confirm; 417 bool sanity_checks; 418 bool max_disp_clk; 419 bool surface_trace; 420 bool timing_trace; 421 bool clock_trace; 422 bool validation_trace; 423 bool bandwidth_calcs_trace; 424 int max_downscale_src_width; 425 426 /* stutter efficiency related */ 427 bool disable_stutter; 428 bool use_max_lb; 429 enum dcc_option disable_dcc; 430 enum pipe_split_policy pipe_split_policy; 431 bool force_single_disp_pipe_split; 432 bool voltage_align_fclk; 433 434 bool disable_dfs_bypass; 435 bool disable_dpp_power_gate; 436 bool disable_hubp_power_gate; 437 bool disable_dsc_power_gate; 438 int dsc_min_slice_height_override; 439 int dsc_bpp_increment_div; 440 bool native422_support; 441 bool disable_pplib_wm_range; 442 enum wm_report_mode pplib_wm_report_mode; 443 unsigned int min_disp_clk_khz; 444 unsigned int min_dpp_clk_khz; 445 int sr_exit_time_dpm0_ns; 446 int sr_enter_plus_exit_time_dpm0_ns; 447 int sr_exit_time_ns; 448 int sr_enter_plus_exit_time_ns; 449 int urgent_latency_ns; 450 uint32_t underflow_assert_delay_us; 451 int percent_of_ideal_drambw; 452 int dram_clock_change_latency_ns; 453 bool optimized_watermark; 454 int always_scale; 455 bool disable_pplib_clock_request; 456 bool disable_clock_gate; 457 bool disable_mem_low_power; 458 bool disable_dmcu; 459 bool disable_psr; 460 bool force_abm_enable; 461 bool disable_stereo_support; 462 bool vsr_support; 463 bool performance_trace; 464 bool az_endpoint_mute_only; 465 bool always_use_regamma; 466 bool p010_mpo_support; 467 bool recovery_enabled; 468 bool avoid_vbios_exec_table; 469 bool scl_reset_length10; 470 bool hdmi20_disable; 471 bool skip_detection_link_training; 472 bool edid_read_retry_times; 473 bool remove_disconnect_edp; 474 unsigned int force_odm_combine; //bit vector based on otg inst 475 #if defined(CONFIG_DRM_AMD_DC_DCN3_0) 476 unsigned int force_odm_combine_4to1; //bit vector based on otg inst 477 #endif 478 unsigned int force_fclk_khz; 479 bool enable_tri_buf; 480 bool dmub_offload_enabled; 481 bool dmcub_emulation; 482 #if defined(CONFIG_DRM_AMD_DC_DCN3_0) 483 bool disable_idle_power_optimizations; 484 #endif 485 bool dmub_command_table; /* for testing only */ 486 struct dc_bw_validation_profile bw_val_profile; 487 bool disable_fec; 488 bool disable_48mhz_pwrdwn; 489 /* This forces a hard min on the DCFCLK requested to SMU/PP 490 * watermarks are not affected. 491 */ 492 unsigned int force_min_dcfclk_mhz; 493 #if defined(CONFIG_DRM_AMD_DC_DCN3_0) 494 int dwb_fi_phase; 495 #endif 496 bool disable_timing_sync; 497 bool cm_in_bypass; 498 int force_clock_mode;/*every mode change.*/ 499 500 bool disable_dram_clock_change_vactive_support; 501 bool validate_dml_output; 502 bool enable_dmcub_surface_flip; 503 bool usbc_combo_phy_reset_wa; 504 bool disable_dsc; 505 bool enable_dram_clock_change_one_display_vactive; 506 bool force_ignore_link_settings; 507 }; 508 509 struct dc_debug_data { 510 uint32_t ltFailCount; 511 uint32_t i2cErrorCount; 512 uint32_t auxErrorCount; 513 }; 514 515 struct dc_phy_addr_space_config { 516 struct { 517 uint64_t start_addr; 518 uint64_t end_addr; 519 uint64_t fb_top; 520 uint64_t fb_offset; 521 uint64_t fb_base; 522 uint64_t agp_top; 523 uint64_t agp_bot; 524 uint64_t agp_base; 525 } system_aperture; 526 527 struct { 528 uint64_t page_table_start_addr; 529 uint64_t page_table_end_addr; 530 uint64_t page_table_base_addr; 531 } gart_config; 532 533 bool valid; 534 bool is_hvm_enabled; 535 uint64_t page_table_default_page_addr; 536 }; 537 538 struct dc_virtual_addr_space_config { 539 uint64_t page_table_base_addr; 540 uint64_t page_table_start_addr; 541 uint64_t page_table_end_addr; 542 uint32_t page_table_block_size_in_bytes; 543 uint8_t page_table_depth; // 1 = 1 level, 2 = 2 level, etc. 0 = invalid 544 }; 545 546 struct dc_bounding_box_overrides { 547 int sr_exit_time_ns; 548 int sr_enter_plus_exit_time_ns; 549 int urgent_latency_ns; 550 int percent_of_ideal_drambw; 551 int dram_clock_change_latency_ns; 552 int dummy_clock_change_latency_ns; 553 /* This forces a hard min on the DCFCLK we use 554 * for DML. Unlike the debug option for forcing 555 * DCFCLK, this override affects watermark calculations 556 */ 557 int min_dcfclk_mhz; 558 }; 559 560 struct dc_state; 561 struct resource_pool; 562 struct dce_hwseq; 563 struct gpu_info_soc_bounding_box_v1_0; 564 struct dc { 565 struct dc_versions versions; 566 struct dc_caps caps; 567 struct dc_cap_funcs cap_funcs; 568 struct dc_config config; 569 struct dc_debug_options debug; 570 struct dc_bounding_box_overrides bb_overrides; 571 struct dc_bug_wa work_arounds; 572 struct dc_context *ctx; 573 struct dc_phy_addr_space_config vm_pa_config; 574 575 uint8_t link_count; 576 struct dc_link *links[MAX_PIPES * 2]; 577 578 struct dc_state *current_state; 579 struct resource_pool *res_pool; 580 581 struct clk_mgr *clk_mgr; 582 583 /* Display Engine Clock levels */ 584 struct dm_pp_clock_levels sclk_lvls; 585 586 /* Inputs into BW and WM calculations. */ 587 struct bw_calcs_dceip *bw_dceip; 588 struct bw_calcs_vbios *bw_vbios; 589 #ifdef CONFIG_DRM_AMD_DC_DCN 590 struct dcn_soc_bounding_box *dcn_soc; 591 struct dcn_ip_params *dcn_ip; 592 struct display_mode_lib dml; 593 #endif 594 595 /* HW functions */ 596 struct hw_sequencer_funcs hwss; 597 struct dce_hwseq *hwseq; 598 599 /* Require to optimize clocks and bandwidth for added/removed planes */ 600 bool optimized_required; 601 bool wm_optimized_required; 602 #if defined(CONFIG_DRM_AMD_DC_DCN3_0) 603 bool idle_optimizations_allowed; 604 #endif 605 606 /* Require to maintain clocks and bandwidth for UEFI enabled HW */ 607 int optimize_seamless_boot_streams; 608 609 /* FBC compressor */ 610 struct compressor *fbc_compressor; 611 612 struct dc_debug_data debug_data; 613 struct dpcd_vendor_signature vendor_signature; 614 615 const char *build_id; 616 struct vm_helper *vm_helper; 617 const struct gpu_info_soc_bounding_box_v1_0 *soc_bounding_box; 618 }; 619 620 enum frame_buffer_mode { 621 FRAME_BUFFER_MODE_LOCAL_ONLY = 0, 622 FRAME_BUFFER_MODE_ZFB_ONLY, 623 FRAME_BUFFER_MODE_MIXED_ZFB_AND_LOCAL, 624 } ; 625 626 struct dchub_init_data { 627 int64_t zfb_phys_addr_base; 628 int64_t zfb_mc_base_addr; 629 uint64_t zfb_size_in_byte; 630 enum frame_buffer_mode fb_mode; 631 bool dchub_initialzied; 632 bool dchub_info_valid; 633 }; 634 635 struct dc_init_data { 636 struct hw_asic_id asic_id; 637 void *driver; /* ctx */ 638 struct cgs_device *cgs_device; 639 struct dc_bounding_box_overrides bb_overrides; 640 641 int num_virtual_links; 642 /* 643 * If 'vbios_override' not NULL, it will be called instead 644 * of the real VBIOS. Intended use is Diagnostics on FPGA. 645 */ 646 struct dc_bios *vbios_override; 647 enum dce_environment dce_environment; 648 649 struct dmub_offload_funcs *dmub_if; 650 struct dc_reg_helper_state *dmub_offload; 651 652 struct dc_config flags; 653 uint64_t log_mask; 654 655 /** 656 * gpu_info FW provided soc bounding box struct or 0 if not 657 * available in FW 658 */ 659 const struct gpu_info_soc_bounding_box_v1_0 *soc_bounding_box; 660 struct dpcd_vendor_signature vendor_signature; 661 #if defined(CONFIG_DRM_AMD_DC_DCN3_0) 662 bool force_smu_not_present; 663 #endif 664 bool force_ignore_link_settings; 665 }; 666 667 struct dc_callback_init { 668 #ifdef CONFIG_DRM_AMD_DC_HDCP 669 struct cp_psp cp_psp; 670 #else 671 uint8_t reserved; 672 #endif 673 }; 674 675 struct dc *dc_create(const struct dc_init_data *init_params); 676 void dc_hardware_init(struct dc *dc); 677 678 int dc_get_vmid_use_vector(struct dc *dc); 679 void dc_setup_vm_context(struct dc *dc, struct dc_virtual_addr_space_config *va_config, int vmid); 680 /* Returns the number of vmids supported */ 681 int dc_setup_system_context(struct dc *dc, struct dc_phy_addr_space_config *pa_config); 682 void dc_init_callbacks(struct dc *dc, 683 const struct dc_callback_init *init_params); 684 void dc_deinit_callbacks(struct dc *dc); 685 void dc_destroy(struct dc **dc); 686 687 /******************************************************************************* 688 * Surface Interfaces 689 ******************************************************************************/ 690 691 enum { 692 TRANSFER_FUNC_POINTS = 1025 693 }; 694 695 struct dc_hdr_static_metadata { 696 /* display chromaticities and white point in units of 0.00001 */ 697 unsigned int chromaticity_green_x; 698 unsigned int chromaticity_green_y; 699 unsigned int chromaticity_blue_x; 700 unsigned int chromaticity_blue_y; 701 unsigned int chromaticity_red_x; 702 unsigned int chromaticity_red_y; 703 unsigned int chromaticity_white_point_x; 704 unsigned int chromaticity_white_point_y; 705 706 uint32_t min_luminance; 707 uint32_t max_luminance; 708 uint32_t maximum_content_light_level; 709 uint32_t maximum_frame_average_light_level; 710 }; 711 712 enum dc_transfer_func_type { 713 TF_TYPE_PREDEFINED, 714 TF_TYPE_DISTRIBUTED_POINTS, 715 TF_TYPE_BYPASS, 716 TF_TYPE_HWPWL 717 }; 718 719 struct dc_transfer_func_distributed_points { 720 struct fixed31_32 red[TRANSFER_FUNC_POINTS]; 721 struct fixed31_32 green[TRANSFER_FUNC_POINTS]; 722 struct fixed31_32 blue[TRANSFER_FUNC_POINTS]; 723 724 uint16_t end_exponent; 725 uint16_t x_point_at_y1_red; 726 uint16_t x_point_at_y1_green; 727 uint16_t x_point_at_y1_blue; 728 }; 729 730 enum dc_transfer_func_predefined { 731 TRANSFER_FUNCTION_SRGB, 732 TRANSFER_FUNCTION_BT709, 733 TRANSFER_FUNCTION_PQ, 734 TRANSFER_FUNCTION_LINEAR, 735 TRANSFER_FUNCTION_UNITY, 736 TRANSFER_FUNCTION_HLG, 737 TRANSFER_FUNCTION_HLG12, 738 TRANSFER_FUNCTION_GAMMA22, 739 TRANSFER_FUNCTION_GAMMA24, 740 TRANSFER_FUNCTION_GAMMA26 741 }; 742 743 744 struct dc_transfer_func { 745 struct kref refcount; 746 enum dc_transfer_func_type type; 747 enum dc_transfer_func_predefined tf; 748 /* FP16 1.0 reference level in nits, default is 80 nits, only for PQ*/ 749 uint32_t sdr_ref_white_level; 750 union { 751 struct pwl_params pwl; 752 struct dc_transfer_func_distributed_points tf_pts; 753 }; 754 }; 755 756 757 union dc_3dlut_state { 758 struct { 759 uint32_t initialized:1; /*if 3dlut is went through color module for initialization */ 760 uint32_t rmu_idx_valid:1; /*if mux settings are valid*/ 761 uint32_t rmu_mux_num:3; /*index of mux to use*/ 762 uint32_t mpc_rmu0_mux:4; /*select mpcc on mux, one of the following : mpcc0, mpcc1, mpcc2, mpcc3*/ 763 uint32_t mpc_rmu1_mux:4; 764 uint32_t mpc_rmu2_mux:4; 765 uint32_t reserved:15; 766 } bits; 767 uint32_t raw; 768 }; 769 770 771 struct dc_3dlut { 772 struct kref refcount; 773 struct tetrahedral_params lut_3d; 774 struct fixed31_32 hdr_multiplier; 775 union dc_3dlut_state state; 776 }; 777 /* 778 * This structure is filled in by dc_surface_get_status and contains 779 * the last requested address and the currently active address so the called 780 * can determine if there are any outstanding flips 781 */ 782 struct dc_plane_status { 783 struct dc_plane_address requested_address; 784 struct dc_plane_address current_address; 785 bool is_flip_pending; 786 bool is_right_eye; 787 }; 788 789 union surface_update_flags { 790 791 struct { 792 uint32_t addr_update:1; 793 /* Medium updates */ 794 uint32_t dcc_change:1; 795 uint32_t color_space_change:1; 796 uint32_t horizontal_mirror_change:1; 797 uint32_t per_pixel_alpha_change:1; 798 uint32_t global_alpha_change:1; 799 uint32_t hdr_mult:1; 800 uint32_t rotation_change:1; 801 uint32_t swizzle_change:1; 802 uint32_t scaling_change:1; 803 uint32_t position_change:1; 804 uint32_t in_transfer_func_change:1; 805 uint32_t input_csc_change:1; 806 uint32_t coeff_reduction_change:1; 807 uint32_t output_tf_change:1; 808 uint32_t pixel_format_change:1; 809 uint32_t plane_size_change:1; 810 uint32_t gamut_remap_change:1; 811 812 /* Full updates */ 813 uint32_t new_plane:1; 814 uint32_t bpp_change:1; 815 uint32_t gamma_change:1; 816 uint32_t bandwidth_change:1; 817 uint32_t clock_change:1; 818 uint32_t stereo_format_change:1; 819 uint32_t full_update:1; 820 } bits; 821 822 uint32_t raw; 823 }; 824 825 struct dc_plane_state { 826 struct dc_plane_address address; 827 struct dc_plane_flip_time time; 828 bool triplebuffer_flips; 829 struct scaling_taps scaling_quality; 830 struct rect src_rect; 831 struct rect dst_rect; 832 struct rect clip_rect; 833 834 struct plane_size plane_size; 835 union dc_tiling_info tiling_info; 836 837 struct dc_plane_dcc_param dcc; 838 839 struct dc_gamma *gamma_correction; 840 struct dc_transfer_func *in_transfer_func; 841 struct dc_bias_and_scale *bias_and_scale; 842 struct dc_csc_transform input_csc_color_matrix; 843 struct fixed31_32 coeff_reduction_factor; 844 struct fixed31_32 hdr_mult; 845 struct colorspace_transform gamut_remap_matrix; 846 847 // TODO: No longer used, remove 848 struct dc_hdr_static_metadata hdr_static_ctx; 849 850 enum dc_color_space color_space; 851 852 struct dc_3dlut *lut3d_func; 853 struct dc_transfer_func *in_shaper_func; 854 struct dc_transfer_func *blend_tf; 855 856 #if defined(CONFIG_DRM_AMD_DC_DCN3_0) 857 struct dc_transfer_func *gamcor_tf; 858 #endif 859 enum surface_pixel_format format; 860 enum dc_rotation_angle rotation; 861 enum plane_stereo_format stereo_format; 862 863 bool is_tiling_rotated; 864 bool per_pixel_alpha; 865 bool global_alpha; 866 int global_alpha_value; 867 bool visible; 868 bool flip_immediate; 869 bool horizontal_mirror; 870 int layer_index; 871 872 union surface_update_flags update_flags; 873 /* private to DC core */ 874 struct dc_plane_status status; 875 struct dc_context *ctx; 876 877 /* HACK: Workaround for forcing full reprogramming under some conditions */ 878 bool force_full_update; 879 880 /* private to dc_surface.c */ 881 enum dc_irq_source irq_source; 882 struct kref refcount; 883 }; 884 885 struct dc_plane_info { 886 struct plane_size plane_size; 887 union dc_tiling_info tiling_info; 888 struct dc_plane_dcc_param dcc; 889 enum surface_pixel_format format; 890 enum dc_rotation_angle rotation; 891 enum plane_stereo_format stereo_format; 892 enum dc_color_space color_space; 893 bool horizontal_mirror; 894 bool visible; 895 bool per_pixel_alpha; 896 bool global_alpha; 897 int global_alpha_value; 898 bool input_csc_enabled; 899 int layer_index; 900 }; 901 902 struct dc_scaling_info { 903 struct rect src_rect; 904 struct rect dst_rect; 905 struct rect clip_rect; 906 struct scaling_taps scaling_quality; 907 }; 908 909 struct dc_surface_update { 910 struct dc_plane_state *surface; 911 912 /* isr safe update parameters. null means no updates */ 913 const struct dc_flip_addrs *flip_addr; 914 const struct dc_plane_info *plane_info; 915 const struct dc_scaling_info *scaling_info; 916 struct fixed31_32 hdr_mult; 917 /* following updates require alloc/sleep/spin that is not isr safe, 918 * null means no updates 919 */ 920 const struct dc_gamma *gamma; 921 const struct dc_transfer_func *in_transfer_func; 922 923 const struct dc_csc_transform *input_csc_color_matrix; 924 const struct fixed31_32 *coeff_reduction_factor; 925 const struct dc_transfer_func *func_shaper; 926 const struct dc_3dlut *lut3d_func; 927 const struct dc_transfer_func *blend_tf; 928 const struct colorspace_transform *gamut_remap_matrix; 929 }; 930 931 /* 932 * Create a new surface with default parameters; 933 */ 934 struct dc_plane_state *dc_create_plane_state(struct dc *dc); 935 const struct dc_plane_status *dc_plane_get_status( 936 const struct dc_plane_state *plane_state); 937 938 void dc_plane_state_retain(struct dc_plane_state *plane_state); 939 void dc_plane_state_release(struct dc_plane_state *plane_state); 940 941 void dc_gamma_retain(struct dc_gamma *dc_gamma); 942 void dc_gamma_release(struct dc_gamma **dc_gamma); 943 struct dc_gamma *dc_create_gamma(void); 944 945 void dc_transfer_func_retain(struct dc_transfer_func *dc_tf); 946 void dc_transfer_func_release(struct dc_transfer_func *dc_tf); 947 struct dc_transfer_func *dc_create_transfer_func(void); 948 949 struct dc_3dlut *dc_create_3dlut_func(void); 950 void dc_3dlut_func_release(struct dc_3dlut *lut); 951 void dc_3dlut_func_retain(struct dc_3dlut *lut); 952 /* 953 * This structure holds a surface address. There could be multiple addresses 954 * in cases such as Stereo 3D, Planar YUV, etc. Other per-flip attributes such 955 * as frame durations and DCC format can also be set. 956 */ 957 struct dc_flip_addrs { 958 struct dc_plane_address address; 959 unsigned int flip_timestamp_in_us; 960 bool flip_immediate; 961 /* TODO: add flip duration for FreeSync */ 962 bool triplebuffer_flips; 963 }; 964 965 bool dc_post_update_surfaces_to_stream( 966 struct dc *dc); 967 968 #include "dc_stream.h" 969 970 /* 971 * Structure to store surface/stream associations for validation 972 */ 973 struct dc_validation_set { 974 struct dc_stream_state *stream; 975 struct dc_plane_state *plane_states[MAX_SURFACES]; 976 uint8_t plane_count; 977 }; 978 979 bool dc_validate_seamless_boot_timing(const struct dc *dc, 980 const struct dc_sink *sink, 981 struct dc_crtc_timing *crtc_timing); 982 983 enum dc_status dc_validate_plane(struct dc *dc, const struct dc_plane_state *plane_state); 984 985 void get_clock_requirements_for_state(struct dc_state *state, struct AsicStateEx *info); 986 987 bool dc_set_generic_gpio_for_stereo(bool enable, 988 struct gpio_service *gpio_service); 989 990 /* 991 * fast_validate: we return after determining if we can support the new state, 992 * but before we populate the programming info 993 */ 994 enum dc_status dc_validate_global_state( 995 struct dc *dc, 996 struct dc_state *new_ctx, 997 bool fast_validate); 998 999 1000 void dc_resource_state_construct( 1001 const struct dc *dc, 1002 struct dc_state *dst_ctx); 1003 1004 #if defined(CONFIG_DRM_AMD_DC_DCN3_0) 1005 bool dc_acquire_release_mpc_3dlut( 1006 struct dc *dc, bool acquire, 1007 struct dc_stream_state *stream, 1008 struct dc_3dlut **lut, 1009 struct dc_transfer_func **shaper); 1010 #endif 1011 1012 void dc_resource_state_copy_construct( 1013 const struct dc_state *src_ctx, 1014 struct dc_state *dst_ctx); 1015 1016 void dc_resource_state_copy_construct_current( 1017 const struct dc *dc, 1018 struct dc_state *dst_ctx); 1019 1020 void dc_resource_state_destruct(struct dc_state *context); 1021 1022 bool dc_resource_is_dsc_encoding_supported(const struct dc *dc); 1023 1024 /* 1025 * TODO update to make it about validation sets 1026 * Set up streams and links associated to drive sinks 1027 * The streams parameter is an absolute set of all active streams. 1028 * 1029 * After this call: 1030 * Phy, Encoder, Timing Generator are programmed and enabled. 1031 * New streams are enabled with blank stream; no memory read. 1032 */ 1033 bool dc_commit_state(struct dc *dc, struct dc_state *context); 1034 1035 void dc_power_down_on_boot(struct dc *dc); 1036 1037 struct dc_state *dc_create_state(struct dc *dc); 1038 struct dc_state *dc_copy_state(struct dc_state *src_ctx); 1039 void dc_retain_state(struct dc_state *context); 1040 void dc_release_state(struct dc_state *context); 1041 1042 /******************************************************************************* 1043 * Link Interfaces 1044 ******************************************************************************/ 1045 1046 struct dpcd_caps { 1047 union dpcd_rev dpcd_rev; 1048 union max_lane_count max_ln_count; 1049 union max_down_spread max_down_spread; 1050 union dprx_feature dprx_feature; 1051 1052 /* valid only for eDP v1.4 or higher*/ 1053 uint8_t edp_supported_link_rates_count; 1054 enum dc_link_rate edp_supported_link_rates[8]; 1055 1056 /* dongle type (DP converter, CV smart dongle) */ 1057 enum display_dongle_type dongle_type; 1058 /* branch device or sink device */ 1059 bool is_branch_dev; 1060 /* Dongle's downstream count. */ 1061 union sink_count sink_count; 1062 /* If dongle_type == DISPLAY_DONGLE_DP_HDMI_CONVERTER, 1063 indicates 'Frame Sequential-to-lllFrame Pack' conversion capability.*/ 1064 struct dc_dongle_caps dongle_caps; 1065 1066 uint32_t sink_dev_id; 1067 int8_t sink_dev_id_str[6]; 1068 int8_t sink_hw_revision; 1069 int8_t sink_fw_revision[2]; 1070 1071 uint32_t branch_dev_id; 1072 int8_t branch_dev_name[6]; 1073 int8_t branch_hw_revision; 1074 int8_t branch_fw_revision[2]; 1075 1076 bool allow_invalid_MSA_timing_param; 1077 bool panel_mode_edp; 1078 bool dpcd_display_control_capable; 1079 bool ext_receiver_cap_field_present; 1080 union dpcd_fec_capability fec_cap; 1081 struct dpcd_dsc_capabilities dsc_caps; 1082 struct dc_lttpr_caps lttpr_caps; 1083 struct psr_caps psr_caps; 1084 1085 }; 1086 1087 union dpcd_sink_ext_caps { 1088 struct { 1089 /* 0 - Sink supports backlight adjust via PWM during SDR/HDR mode 1090 * 1 - Sink supports backlight adjust via AUX during SDR/HDR mode. 1091 */ 1092 uint8_t sdr_aux_backlight_control : 1; 1093 uint8_t hdr_aux_backlight_control : 1; 1094 uint8_t reserved_1 : 2; 1095 uint8_t oled : 1; 1096 uint8_t reserved : 3; 1097 } bits; 1098 uint8_t raw; 1099 }; 1100 1101 #if defined(CONFIG_DRM_AMD_DC_HDCP) 1102 union hdcp_rx_caps { 1103 struct { 1104 uint8_t version; 1105 uint8_t reserved; 1106 struct { 1107 uint8_t repeater : 1; 1108 uint8_t hdcp_capable : 1; 1109 uint8_t reserved : 6; 1110 } byte0; 1111 } fields; 1112 uint8_t raw[3]; 1113 }; 1114 1115 union hdcp_bcaps { 1116 struct { 1117 uint8_t HDCP_CAPABLE:1; 1118 uint8_t REPEATER:1; 1119 uint8_t RESERVED:6; 1120 } bits; 1121 uint8_t raw; 1122 }; 1123 1124 struct hdcp_caps { 1125 union hdcp_rx_caps rx_caps; 1126 union hdcp_bcaps bcaps; 1127 }; 1128 #endif 1129 1130 #include "dc_link.h" 1131 1132 #if defined(CONFIG_DRM_AMD_DC_DCN3_0) 1133 uint32_t dc_get_opp_for_plane(struct dc *dc, struct dc_plane_state *plane); 1134 1135 #endif 1136 /******************************************************************************* 1137 * Sink Interfaces - A sink corresponds to a display output device 1138 ******************************************************************************/ 1139 1140 struct dc_container_id { 1141 // 128bit GUID in binary form 1142 unsigned char guid[16]; 1143 // 8 byte port ID -> ELD.PortID 1144 unsigned int portId[2]; 1145 // 128bit GUID in binary formufacturer name -> ELD.ManufacturerName 1146 unsigned short manufacturerName; 1147 // 2 byte product code -> ELD.ProductCode 1148 unsigned short productCode; 1149 }; 1150 1151 1152 struct dc_sink_dsc_caps { 1153 // 'true' if these are virtual DPCD's DSC caps (immediately upstream of sink in MST topology), 1154 // 'false' if they are sink's DSC caps 1155 bool is_virtual_dpcd_dsc; 1156 struct dsc_dec_dpcd_caps dsc_dec_caps; 1157 }; 1158 1159 struct dc_sink_fec_caps { 1160 bool is_rx_fec_supported; 1161 bool is_topology_fec_supported; 1162 }; 1163 1164 /* 1165 * The sink structure contains EDID and other display device properties 1166 */ 1167 struct dc_sink { 1168 enum signal_type sink_signal; 1169 struct dc_edid dc_edid; /* raw edid */ 1170 struct dc_edid_caps edid_caps; /* parse display caps */ 1171 struct dc_container_id *dc_container_id; 1172 uint32_t dongle_max_pix_clk; 1173 void *priv; 1174 struct stereo_3d_features features_3d[TIMING_3D_FORMAT_MAX]; 1175 bool converter_disable_audio; 1176 bool is_mst_legacy; 1177 struct dc_sink_dsc_caps dsc_caps; 1178 struct dc_sink_fec_caps fec_caps; 1179 1180 bool is_vsc_sdp_colorimetry_supported; 1181 1182 /* private to DC core */ 1183 struct dc_link *link; 1184 struct dc_context *ctx; 1185 1186 uint32_t sink_id; 1187 1188 /* private to dc_sink.c */ 1189 // refcount must be the last member in dc_sink, since we want the 1190 // sink structure to be logically cloneable up to (but not including) 1191 // refcount 1192 struct kref refcount; 1193 }; 1194 1195 void dc_sink_retain(struct dc_sink *sink); 1196 void dc_sink_release(struct dc_sink *sink); 1197 1198 struct dc_sink_init_data { 1199 enum signal_type sink_signal; 1200 struct dc_link *link; 1201 uint32_t dongle_max_pix_clk; 1202 bool converter_disable_audio; 1203 bool sink_is_legacy; 1204 }; 1205 1206 struct dc_sink *dc_sink_create(const struct dc_sink_init_data *init_params); 1207 1208 /* Newer interfaces */ 1209 struct dc_cursor { 1210 struct dc_plane_address address; 1211 struct dc_cursor_attributes attributes; 1212 }; 1213 1214 1215 /******************************************************************************* 1216 * Interrupt interfaces 1217 ******************************************************************************/ 1218 enum dc_irq_source dc_interrupt_to_irq_source( 1219 struct dc *dc, 1220 uint32_t src_id, 1221 uint32_t ext_id); 1222 bool dc_interrupt_set(struct dc *dc, enum dc_irq_source src, bool enable); 1223 void dc_interrupt_ack(struct dc *dc, enum dc_irq_source src); 1224 enum dc_irq_source dc_get_hpd_irq_source_at_index( 1225 struct dc *dc, uint32_t link_index); 1226 1227 /******************************************************************************* 1228 * Power Interfaces 1229 ******************************************************************************/ 1230 1231 void dc_set_power_state( 1232 struct dc *dc, 1233 enum dc_acpi_cm_power_state power_state); 1234 void dc_resume(struct dc *dc); 1235 1236 void dc_power_down_on_boot(struct dc *dc); 1237 1238 #if defined(CONFIG_DRM_AMD_DC_HDCP) 1239 /* 1240 * HDCP Interfaces 1241 */ 1242 enum hdcp_message_status dc_process_hdcp_msg( 1243 enum signal_type signal, 1244 struct dc_link *link, 1245 struct hdcp_protection_message *message_info); 1246 #endif 1247 bool dc_is_dmcu_initialized(struct dc *dc); 1248 1249 enum dc_status dc_set_clock(struct dc *dc, enum dc_clock_type clock_type, uint32_t clk_khz, uint32_t stepping); 1250 void dc_get_clock(struct dc *dc, enum dc_clock_type clock_type, struct dc_clock_config *clock_cfg); 1251 #if defined(CONFIG_DRM_AMD_DC_DCN3_0) 1252 1253 bool dc_is_plane_eligible_for_idle_optimizations(struct dc *dc, 1254 struct dc_plane_state *plane); 1255 1256 void dc_allow_idle_optimizations(struct dc *dc, bool allow); 1257 1258 /* 1259 * blank all streams, and set min and max memory clock to 1260 * lowest and highest DPM level, respectively 1261 */ 1262 void dc_unlock_memory_clock_frequency(struct dc *dc); 1263 1264 /* 1265 * set min memory clock to the min required for current mode, 1266 * max to maxDPM, and unblank streams 1267 */ 1268 void dc_lock_memory_clock_frequency(struct dc *dc); 1269 1270 #endif 1271 1272 bool dc_set_psr_allow_active(struct dc *dc, bool enable); 1273 1274 /******************************************************************************* 1275 * DSC Interfaces 1276 ******************************************************************************/ 1277 #include "dc_dsc.h" 1278 #endif /* DC_INTERFACE_H_ */ 1279