1 /* 2 * Copyright 2012-14 Advanced Micro Devices, Inc. 3 * 4 * Permission is hereby granted, free of charge, to any person obtaining a 5 * copy of this software and associated documentation files (the "Software"), 6 * to deal in the Software without restriction, including without limitation 7 * the rights to use, copy, modify, merge, publish, distribute, sublicense, 8 * and/or sell copies of the Software, and to permit persons to whom the 9 * Software is furnished to do so, subject to the following conditions: 10 * 11 * The above copyright notice and this permission notice shall be included in 12 * all copies or substantial portions of the Software. 13 * 14 * THE SOFTWARE IS PROVIDED "AS IS", WITHOUT WARRANTY OF ANY KIND, EXPRESS OR 15 * IMPLIED, INCLUDING BUT NOT LIMITED TO THE WARRANTIES OF MERCHANTABILITY, 16 * FITNESS FOR A PARTICULAR PURPOSE AND NONINFRINGEMENT. IN NO EVENT SHALL 17 * THE COPYRIGHT HOLDER(S) OR AUTHOR(S) BE LIABLE FOR ANY CLAIM, DAMAGES OR 18 * OTHER LIABILITY, WHETHER IN AN ACTION OF CONTRACT, TORT OR OTHERWISE, 19 * ARISING FROM, OUT OF OR IN CONNECTION WITH THE SOFTWARE OR THE USE OR 20 * OTHER DEALINGS IN THE SOFTWARE. 21 * 22 * Authors: AMD 23 * 24 */ 25 26 #ifndef DC_INTERFACE_H_ 27 #define DC_INTERFACE_H_ 28 29 #include "dc_types.h" 30 #include "grph_object_defs.h" 31 #include "logger_types.h" 32 #include "gpio_types.h" 33 #include "link_service_types.h" 34 #include "grph_object_ctrl_defs.h" 35 #include <inc/hw/opp.h> 36 37 #include "inc/hw_sequencer.h" 38 #include "inc/compressor.h" 39 #include "inc/hw/dmcu.h" 40 #include "dml/display_mode_lib.h" 41 42 #define DC_VER "3.2.41" 43 44 #define MAX_SURFACES 3 45 #define MAX_PLANES 6 46 #define MAX_STREAMS 6 47 #define MAX_SINKS_PER_LINK 4 48 49 /******************************************************************************* 50 * Display Core Interfaces 51 ******************************************************************************/ 52 struct dc_versions { 53 const char *dc_ver; 54 struct dmcu_version dmcu_version; 55 }; 56 57 enum dc_plane_type { 58 DC_PLANE_TYPE_INVALID, 59 DC_PLANE_TYPE_DCE_RGB, 60 DC_PLANE_TYPE_DCE_UNDERLAY, 61 DC_PLANE_TYPE_DCN_UNIVERSAL, 62 }; 63 64 struct dc_plane_cap { 65 enum dc_plane_type type; 66 uint32_t blends_with_above : 1; 67 uint32_t blends_with_below : 1; 68 uint32_t per_pixel_alpha : 1; 69 struct { 70 uint32_t argb8888 : 1; 71 uint32_t nv12 : 1; 72 uint32_t fp16 : 1; 73 uint32_t p010 : 1; 74 uint32_t ayuv : 1; 75 } pixel_format_support; 76 // max upscaling factor x1000 77 // upscaling factors are always >= 1 78 // for example, 1080p -> 8K is 4.0, or 4000 raw value 79 struct { 80 uint32_t argb8888; 81 uint32_t nv12; 82 uint32_t fp16; 83 } max_upscale_factor; 84 // max downscale factor x1000 85 // downscale factors are always <= 1 86 // for example, 8K -> 1080p is 0.25, or 250 raw value 87 struct { 88 uint32_t argb8888; 89 uint32_t nv12; 90 uint32_t fp16; 91 } max_downscale_factor; 92 }; 93 94 struct dc_caps { 95 uint32_t max_streams; 96 uint32_t max_links; 97 uint32_t max_audios; 98 uint32_t max_slave_planes; 99 uint32_t max_planes; 100 uint32_t max_downscale_ratio; 101 uint32_t i2c_speed_in_khz; 102 uint32_t dmdata_alloc_size; 103 unsigned int max_cursor_size; 104 unsigned int max_video_width; 105 int linear_pitch_alignment; 106 bool dcc_const_color; 107 bool dynamic_audio; 108 bool is_apu; 109 bool dual_link_dvi; 110 bool post_blend_color_processing; 111 bool force_dp_tps4_for_cp2520; 112 bool disable_dp_clk_share; 113 bool psp_setup_panel_mode; 114 #ifdef CONFIG_DRM_AMD_DC_DCN2_0 115 bool hw_3d_lut; 116 #endif 117 struct dc_plane_cap planes[MAX_PLANES]; 118 }; 119 120 #if defined(CONFIG_DRM_AMD_DC_DCN2_0) 121 struct dc_bug_wa { 122 bool no_connect_phy_config; 123 bool dedcn20_305_wa; 124 }; 125 #endif 126 127 struct dc_dcc_surface_param { 128 struct dc_size surface_size; 129 enum surface_pixel_format format; 130 enum swizzle_mode_values swizzle_mode; 131 enum dc_scan_direction scan; 132 }; 133 134 struct dc_dcc_setting { 135 unsigned int max_compressed_blk_size; 136 unsigned int max_uncompressed_blk_size; 137 bool independent_64b_blks; 138 }; 139 140 struct dc_surface_dcc_cap { 141 union { 142 struct { 143 struct dc_dcc_setting rgb; 144 } grph; 145 146 struct { 147 struct dc_dcc_setting luma; 148 struct dc_dcc_setting chroma; 149 } video; 150 }; 151 152 bool capable; 153 bool const_color_support; 154 }; 155 156 struct dc_static_screen_events { 157 bool force_trigger; 158 bool cursor_update; 159 bool surface_update; 160 bool overlay_update; 161 }; 162 163 164 /* Surface update type is used by dc_update_surfaces_and_stream 165 * The update type is determined at the very beginning of the function based 166 * on parameters passed in and decides how much programming (or updating) is 167 * going to be done during the call. 168 * 169 * UPDATE_TYPE_FAST is used for really fast updates that do not require much 170 * logical calculations or hardware register programming. This update MUST be 171 * ISR safe on windows. Currently fast update will only be used to flip surface 172 * address. 173 * 174 * UPDATE_TYPE_MED is used for slower updates which require significant hw 175 * re-programming however do not affect bandwidth consumption or clock 176 * requirements. At present, this is the level at which front end updates 177 * that do not require us to run bw_calcs happen. These are in/out transfer func 178 * updates, viewport offset changes, recout size changes and pixel depth changes. 179 * This update can be done at ISR, but we want to minimize how often this happens. 180 * 181 * UPDATE_TYPE_FULL is slow. Really slow. This requires us to recalculate our 182 * bandwidth and clocks, possibly rearrange some pipes and reprogram anything front 183 * end related. Any time viewport dimensions, recout dimensions, scaling ratios or 184 * gamma need to be adjusted or pipe needs to be turned on (or disconnected) we do 185 * a full update. This cannot be done at ISR level and should be a rare event. 186 * Unless someone is stress testing mpo enter/exit, playing with colour or adjusting 187 * underscan we don't expect to see this call at all. 188 */ 189 190 enum surface_update_type { 191 UPDATE_TYPE_FAST, /* super fast, safe to execute in isr */ 192 UPDATE_TYPE_MED, /* ISR safe, most of programming needed, no bw/clk change*/ 193 UPDATE_TYPE_FULL, /* may need to shuffle resources */ 194 }; 195 196 /* Forward declaration*/ 197 struct dc; 198 struct dc_plane_state; 199 struct dc_state; 200 201 202 struct dc_cap_funcs { 203 bool (*get_dcc_compression_cap)(const struct dc *dc, 204 const struct dc_dcc_surface_param *input, 205 struct dc_surface_dcc_cap *output); 206 }; 207 208 struct link_training_settings; 209 210 211 /* Structure to hold configuration flags set by dm at dc creation. */ 212 struct dc_config { 213 bool gpu_vm_support; 214 bool disable_disp_pll_sharing; 215 bool fbc_support; 216 bool optimize_edp_link_rate; 217 bool disable_fractional_pwm; 218 bool allow_seamless_boot_optimization; 219 bool power_down_display_on_boot; 220 bool edp_not_connected; 221 bool forced_clocks; 222 223 }; 224 225 enum visual_confirm { 226 VISUAL_CONFIRM_DISABLE = 0, 227 VISUAL_CONFIRM_SURFACE = 1, 228 VISUAL_CONFIRM_HDR = 2, 229 }; 230 231 enum dcc_option { 232 DCC_ENABLE = 0, 233 DCC_DISABLE = 1, 234 DCC_HALF_REQ_DISALBE = 2, 235 }; 236 237 enum pipe_split_policy { 238 MPC_SPLIT_DYNAMIC = 0, 239 MPC_SPLIT_AVOID = 1, 240 MPC_SPLIT_AVOID_MULT_DISP = 2, 241 }; 242 243 enum wm_report_mode { 244 WM_REPORT_DEFAULT = 0, 245 WM_REPORT_OVERRIDE = 1, 246 }; 247 248 /* 249 * For any clocks that may differ per pipe 250 * only the max is stored in this structure 251 */ 252 struct dc_clocks { 253 int dispclk_khz; 254 int max_supported_dppclk_khz; 255 int max_supported_dispclk_khz; 256 int dppclk_khz; 257 int bw_dppclk_khz; /*a copy of dppclk_khz*/ 258 int bw_dispclk_khz; 259 int dcfclk_khz; 260 int socclk_khz; 261 int dcfclk_deep_sleep_khz; 262 int fclk_khz; 263 int phyclk_khz; 264 int dramclk_khz; 265 bool p_state_change_support; 266 }; 267 268 struct dc_bw_validation_profile { 269 bool enable; 270 271 unsigned long long total_ticks; 272 unsigned long long voltage_level_ticks; 273 unsigned long long watermark_ticks; 274 unsigned long long rq_dlg_ticks; 275 276 unsigned long long total_count; 277 unsigned long long skip_fast_count; 278 unsigned long long skip_pass_count; 279 unsigned long long skip_fail_count; 280 }; 281 282 #define BW_VAL_TRACE_SETUP() \ 283 unsigned long long end_tick = 0; \ 284 unsigned long long voltage_level_tick = 0; \ 285 unsigned long long watermark_tick = 0; \ 286 unsigned long long start_tick = dc->debug.bw_val_profile.enable ? \ 287 dm_get_timestamp(dc->ctx) : 0 288 289 #define BW_VAL_TRACE_COUNT() \ 290 if (dc->debug.bw_val_profile.enable) \ 291 dc->debug.bw_val_profile.total_count++ 292 293 #define BW_VAL_TRACE_SKIP(status) \ 294 if (dc->debug.bw_val_profile.enable) { \ 295 if (!voltage_level_tick) \ 296 voltage_level_tick = dm_get_timestamp(dc->ctx); \ 297 dc->debug.bw_val_profile.skip_ ## status ## _count++; \ 298 } 299 300 #define BW_VAL_TRACE_END_VOLTAGE_LEVEL() \ 301 if (dc->debug.bw_val_profile.enable) \ 302 voltage_level_tick = dm_get_timestamp(dc->ctx) 303 304 #define BW_VAL_TRACE_END_WATERMARKS() \ 305 if (dc->debug.bw_val_profile.enable) \ 306 watermark_tick = dm_get_timestamp(dc->ctx) 307 308 #define BW_VAL_TRACE_FINISH() \ 309 if (dc->debug.bw_val_profile.enable) { \ 310 end_tick = dm_get_timestamp(dc->ctx); \ 311 dc->debug.bw_val_profile.total_ticks += end_tick - start_tick; \ 312 dc->debug.bw_val_profile.voltage_level_ticks += voltage_level_tick - start_tick; \ 313 if (watermark_tick) { \ 314 dc->debug.bw_val_profile.watermark_ticks += watermark_tick - voltage_level_tick; \ 315 dc->debug.bw_val_profile.rq_dlg_ticks += end_tick - watermark_tick; \ 316 } \ 317 } 318 319 struct dc_debug_options { 320 enum visual_confirm visual_confirm; 321 bool sanity_checks; 322 bool max_disp_clk; 323 bool surface_trace; 324 bool timing_trace; 325 bool clock_trace; 326 bool validation_trace; 327 bool bandwidth_calcs_trace; 328 int max_downscale_src_width; 329 330 /* stutter efficiency related */ 331 bool disable_stutter; 332 bool use_max_lb; 333 enum dcc_option disable_dcc; 334 enum pipe_split_policy pipe_split_policy; 335 bool force_single_disp_pipe_split; 336 bool voltage_align_fclk; 337 338 bool disable_dfs_bypass; 339 bool disable_dpp_power_gate; 340 bool disable_hubp_power_gate; 341 #ifdef CONFIG_DRM_AMD_DC_DSC_SUPPORT 342 bool disable_dsc_power_gate; 343 #endif 344 bool disable_pplib_wm_range; 345 enum wm_report_mode pplib_wm_report_mode; 346 unsigned int min_disp_clk_khz; 347 int sr_exit_time_dpm0_ns; 348 int sr_enter_plus_exit_time_dpm0_ns; 349 int sr_exit_time_ns; 350 int sr_enter_plus_exit_time_ns; 351 int urgent_latency_ns; 352 uint32_t underflow_assert_delay_us; 353 int percent_of_ideal_drambw; 354 int dram_clock_change_latency_ns; 355 bool optimized_watermark; 356 int always_scale; 357 bool disable_pplib_clock_request; 358 bool disable_clock_gate; 359 bool disable_dmcu; 360 bool disable_psr; 361 bool force_abm_enable; 362 bool disable_stereo_support; 363 bool vsr_support; 364 bool performance_trace; 365 bool az_endpoint_mute_only; 366 bool always_use_regamma; 367 bool p010_mpo_support; 368 bool recovery_enabled; 369 bool avoid_vbios_exec_table; 370 bool scl_reset_length10; 371 bool hdmi20_disable; 372 bool skip_detection_link_training; 373 unsigned int force_odm_combine; //bit vector based on otg inst 374 unsigned int force_fclk_khz; 375 bool disable_tri_buf; 376 struct dc_bw_validation_profile bw_val_profile; 377 #ifdef CONFIG_DRM_AMD_DC_DSC_SUPPORT 378 bool disable_fec; 379 #endif 380 /* This forces a hard min on the DCFCLK requested to SMU/PP 381 * watermarks are not affected. 382 */ 383 unsigned int force_min_dcfclk_mhz; 384 bool disable_timing_sync; 385 #if defined(CONFIG_DRM_AMD_DC_DCN2_0) 386 bool cm_in_bypass; 387 #endif 388 }; 389 390 struct dc_debug_data { 391 uint32_t ltFailCount; 392 uint32_t i2cErrorCount; 393 uint32_t auxErrorCount; 394 }; 395 396 #ifdef CONFIG_DRM_AMD_DC_DCN2_0 397 struct dc_phy_addr_space_config { 398 struct { 399 uint64_t start_addr; 400 uint64_t end_addr; 401 uint64_t fb_top; 402 uint64_t fb_offset; 403 uint64_t fb_base; 404 uint64_t agp_top; 405 uint64_t agp_bot; 406 uint64_t agp_base; 407 } system_aperture; 408 409 struct { 410 uint64_t page_table_start_addr; 411 uint64_t page_table_end_addr; 412 uint64_t page_table_base_addr; 413 } gart_config; 414 415 bool valid; 416 }; 417 418 struct dc_virtual_addr_space_config { 419 uint64_t page_table_base_addr; 420 uint64_t page_table_start_addr; 421 uint64_t page_table_end_addr; 422 uint32_t page_table_block_size_in_bytes; 423 uint8_t page_table_depth; // 1 = 1 level, 2 = 2 level, etc. 0 = invalid 424 }; 425 #endif 426 427 struct dc_bounding_box_overrides { 428 int sr_exit_time_ns; 429 int sr_enter_plus_exit_time_ns; 430 int urgent_latency_ns; 431 int percent_of_ideal_drambw; 432 int dram_clock_change_latency_ns; 433 /* This forces a hard min on the DCFCLK we use 434 * for DML. Unlike the debug option for forcing 435 * DCFCLK, this override affects watermark calculations 436 */ 437 int min_dcfclk_mhz; 438 }; 439 440 struct dc_state; 441 struct resource_pool; 442 struct dce_hwseq; 443 struct gpu_info_soc_bounding_box_v1_0; 444 struct dc { 445 struct dc_versions versions; 446 struct dc_caps caps; 447 struct dc_cap_funcs cap_funcs; 448 struct dc_config config; 449 struct dc_debug_options debug; 450 struct dc_bounding_box_overrides bb_overrides; 451 #if defined(CONFIG_DRM_AMD_DC_DCN2_0) 452 struct dc_bug_wa work_arounds; 453 #endif 454 struct dc_context *ctx; 455 #ifdef CONFIG_DRM_AMD_DC_DCN2_0 456 struct dc_phy_addr_space_config vm_pa_config; 457 #endif 458 459 uint8_t link_count; 460 struct dc_link *links[MAX_PIPES * 2]; 461 462 struct dc_state *current_state; 463 struct resource_pool *res_pool; 464 465 struct clk_mgr *clk_mgr; 466 467 /* Display Engine Clock levels */ 468 struct dm_pp_clock_levels sclk_lvls; 469 470 /* Inputs into BW and WM calculations. */ 471 struct bw_calcs_dceip *bw_dceip; 472 struct bw_calcs_vbios *bw_vbios; 473 #ifdef CONFIG_DRM_AMD_DC_DCN1_0 474 struct dcn_soc_bounding_box *dcn_soc; 475 struct dcn_ip_params *dcn_ip; 476 struct display_mode_lib dml; 477 #endif 478 479 /* HW functions */ 480 struct hw_sequencer_funcs hwss; 481 struct dce_hwseq *hwseq; 482 483 /* Require to optimize clocks and bandwidth for added/removed planes */ 484 bool optimized_required; 485 486 /* Require to maintain clocks and bandwidth for UEFI enabled HW */ 487 bool optimize_seamless_boot; 488 489 /* FBC compressor */ 490 struct compressor *fbc_compressor; 491 492 struct dc_debug_data debug_data; 493 494 const char *build_id; 495 #ifdef CONFIG_DRM_AMD_DC_DCN2_0 496 struct vm_helper *vm_helper; 497 const struct gpu_info_soc_bounding_box_v1_0 *soc_bounding_box; 498 #endif 499 }; 500 501 enum frame_buffer_mode { 502 FRAME_BUFFER_MODE_LOCAL_ONLY = 0, 503 FRAME_BUFFER_MODE_ZFB_ONLY, 504 FRAME_BUFFER_MODE_MIXED_ZFB_AND_LOCAL, 505 } ; 506 507 struct dchub_init_data { 508 int64_t zfb_phys_addr_base; 509 int64_t zfb_mc_base_addr; 510 uint64_t zfb_size_in_byte; 511 enum frame_buffer_mode fb_mode; 512 bool dchub_initialzied; 513 bool dchub_info_valid; 514 }; 515 516 struct dc_init_data { 517 struct hw_asic_id asic_id; 518 void *driver; /* ctx */ 519 struct cgs_device *cgs_device; 520 struct dc_bounding_box_overrides bb_overrides; 521 522 int num_virtual_links; 523 /* 524 * If 'vbios_override' not NULL, it will be called instead 525 * of the real VBIOS. Intended use is Diagnostics on FPGA. 526 */ 527 struct dc_bios *vbios_override; 528 enum dce_environment dce_environment; 529 530 struct dc_config flags; 531 uint32_t log_mask; 532 #ifdef CONFIG_DRM_AMD_DC_DCN2_0 533 /** 534 * gpu_info FW provided soc bounding box struct or 0 if not 535 * available in FW 536 */ 537 const struct gpu_info_soc_bounding_box_v1_0 *soc_bounding_box; 538 #endif 539 }; 540 541 struct dc_callback_init { 542 uint8_t reserved; 543 }; 544 545 struct dc *dc_create(const struct dc_init_data *init_params); 546 int dc_get_vmid_use_vector(struct dc *dc); 547 #ifdef CONFIG_DRM_AMD_DC_DCN2_0 548 void dc_setup_vm_context(struct dc *dc, struct dc_virtual_addr_space_config *va_config, int vmid); 549 /* Returns the number of vmids supported */ 550 int dc_setup_system_context(struct dc *dc, struct dc_phy_addr_space_config *pa_config); 551 #endif 552 void dc_init_callbacks(struct dc *dc, 553 const struct dc_callback_init *init_params); 554 void dc_destroy(struct dc **dc); 555 556 /******************************************************************************* 557 * Surface Interfaces 558 ******************************************************************************/ 559 560 enum { 561 TRANSFER_FUNC_POINTS = 1025 562 }; 563 564 struct dc_hdr_static_metadata { 565 /* display chromaticities and white point in units of 0.00001 */ 566 unsigned int chromaticity_green_x; 567 unsigned int chromaticity_green_y; 568 unsigned int chromaticity_blue_x; 569 unsigned int chromaticity_blue_y; 570 unsigned int chromaticity_red_x; 571 unsigned int chromaticity_red_y; 572 unsigned int chromaticity_white_point_x; 573 unsigned int chromaticity_white_point_y; 574 575 uint32_t min_luminance; 576 uint32_t max_luminance; 577 uint32_t maximum_content_light_level; 578 uint32_t maximum_frame_average_light_level; 579 }; 580 581 enum dc_transfer_func_type { 582 TF_TYPE_PREDEFINED, 583 TF_TYPE_DISTRIBUTED_POINTS, 584 TF_TYPE_BYPASS, 585 TF_TYPE_HWPWL 586 }; 587 588 struct dc_transfer_func_distributed_points { 589 struct fixed31_32 red[TRANSFER_FUNC_POINTS]; 590 struct fixed31_32 green[TRANSFER_FUNC_POINTS]; 591 struct fixed31_32 blue[TRANSFER_FUNC_POINTS]; 592 593 uint16_t end_exponent; 594 uint16_t x_point_at_y1_red; 595 uint16_t x_point_at_y1_green; 596 uint16_t x_point_at_y1_blue; 597 }; 598 599 enum dc_transfer_func_predefined { 600 TRANSFER_FUNCTION_SRGB, 601 TRANSFER_FUNCTION_BT709, 602 TRANSFER_FUNCTION_PQ, 603 TRANSFER_FUNCTION_LINEAR, 604 TRANSFER_FUNCTION_UNITY, 605 TRANSFER_FUNCTION_HLG, 606 TRANSFER_FUNCTION_HLG12, 607 TRANSFER_FUNCTION_GAMMA22 608 }; 609 610 struct dc_transfer_func { 611 struct kref refcount; 612 enum dc_transfer_func_type type; 613 enum dc_transfer_func_predefined tf; 614 /* FP16 1.0 reference level in nits, default is 80 nits, only for PQ*/ 615 uint32_t sdr_ref_white_level; 616 struct dc_context *ctx; 617 union { 618 struct pwl_params pwl; 619 struct dc_transfer_func_distributed_points tf_pts; 620 }; 621 }; 622 623 #if defined(CONFIG_DRM_AMD_DC_DCN2_0) 624 625 union dc_3dlut_state { 626 struct { 627 uint32_t initialized:1; /*if 3dlut is went through color module for initialization */ 628 uint32_t rmu_idx_valid:1; /*if mux settings are valid*/ 629 uint32_t rmu_mux_num:3; /*index of mux to use*/ 630 uint32_t mpc_rmu0_mux:4; /*select mpcc on mux, one of the following : mpcc0, mpcc1, mpcc2, mpcc3*/ 631 uint32_t mpc_rmu1_mux:4; 632 uint32_t mpc_rmu2_mux:4; 633 uint32_t reserved:15; 634 } bits; 635 uint32_t raw; 636 }; 637 638 639 struct dc_3dlut { 640 struct kref refcount; 641 struct tetrahedral_params lut_3d; 642 uint32_t hdr_multiplier; 643 bool initialized; /*remove after diag fix*/ 644 union dc_3dlut_state state; 645 struct dc_context *ctx; 646 }; 647 #endif 648 /* 649 * This structure is filled in by dc_surface_get_status and contains 650 * the last requested address and the currently active address so the called 651 * can determine if there are any outstanding flips 652 */ 653 struct dc_plane_status { 654 struct dc_plane_address requested_address; 655 struct dc_plane_address current_address; 656 bool is_flip_pending; 657 bool is_right_eye; 658 }; 659 660 union surface_update_flags { 661 662 struct { 663 uint32_t addr_update:1; 664 /* Medium updates */ 665 uint32_t dcc_change:1; 666 uint32_t color_space_change:1; 667 uint32_t horizontal_mirror_change:1; 668 uint32_t per_pixel_alpha_change:1; 669 uint32_t global_alpha_change:1; 670 uint32_t sdr_white_level:1; 671 uint32_t rotation_change:1; 672 uint32_t swizzle_change:1; 673 uint32_t scaling_change:1; 674 uint32_t position_change:1; 675 uint32_t in_transfer_func_change:1; 676 uint32_t input_csc_change:1; 677 uint32_t coeff_reduction_change:1; 678 uint32_t output_tf_change:1; 679 uint32_t pixel_format_change:1; 680 uint32_t plane_size_change:1; 681 682 /* Full updates */ 683 uint32_t new_plane:1; 684 uint32_t bpp_change:1; 685 uint32_t gamma_change:1; 686 uint32_t bandwidth_change:1; 687 uint32_t clock_change:1; 688 uint32_t stereo_format_change:1; 689 uint32_t full_update:1; 690 } bits; 691 692 uint32_t raw; 693 }; 694 695 struct dc_plane_state { 696 struct dc_plane_address address; 697 struct dc_plane_flip_time time; 698 #if defined(CONFIG_DRM_AMD_DC_DCN2_0) 699 bool triplebuffer_flips; 700 #endif 701 struct scaling_taps scaling_quality; 702 struct rect src_rect; 703 struct rect dst_rect; 704 struct rect clip_rect; 705 706 union plane_size plane_size; 707 union dc_tiling_info tiling_info; 708 709 struct dc_plane_dcc_param dcc; 710 711 struct dc_gamma *gamma_correction; 712 struct dc_transfer_func *in_transfer_func; 713 struct dc_bias_and_scale *bias_and_scale; 714 struct dc_csc_transform input_csc_color_matrix; 715 struct fixed31_32 coeff_reduction_factor; 716 uint32_t sdr_white_level; 717 718 // TODO: No longer used, remove 719 struct dc_hdr_static_metadata hdr_static_ctx; 720 721 enum dc_color_space color_space; 722 723 #if defined(CONFIG_DRM_AMD_DC_DCN2_0) 724 struct dc_3dlut *lut3d_func; 725 struct dc_transfer_func *in_shaper_func; 726 struct dc_transfer_func *blend_tf; 727 #endif 728 729 enum surface_pixel_format format; 730 enum dc_rotation_angle rotation; 731 enum plane_stereo_format stereo_format; 732 733 bool is_tiling_rotated; 734 bool per_pixel_alpha; 735 bool global_alpha; 736 int global_alpha_value; 737 bool visible; 738 bool flip_immediate; 739 bool horizontal_mirror; 740 741 union surface_update_flags update_flags; 742 /* private to DC core */ 743 struct dc_plane_status status; 744 struct dc_context *ctx; 745 746 /* HACK: Workaround for forcing full reprogramming under some conditions */ 747 bool force_full_update; 748 749 /* private to dc_surface.c */ 750 enum dc_irq_source irq_source; 751 struct kref refcount; 752 }; 753 754 struct dc_plane_info { 755 union plane_size plane_size; 756 union dc_tiling_info tiling_info; 757 struct dc_plane_dcc_param dcc; 758 enum surface_pixel_format format; 759 enum dc_rotation_angle rotation; 760 enum plane_stereo_format stereo_format; 761 enum dc_color_space color_space; 762 unsigned int sdr_white_level; 763 bool horizontal_mirror; 764 bool visible; 765 bool per_pixel_alpha; 766 bool global_alpha; 767 int global_alpha_value; 768 bool input_csc_enabled; 769 }; 770 771 struct dc_scaling_info { 772 struct rect src_rect; 773 struct rect dst_rect; 774 struct rect clip_rect; 775 struct scaling_taps scaling_quality; 776 }; 777 778 struct dc_surface_update { 779 struct dc_plane_state *surface; 780 781 /* isr safe update parameters. null means no updates */ 782 const struct dc_flip_addrs *flip_addr; 783 const struct dc_plane_info *plane_info; 784 const struct dc_scaling_info *scaling_info; 785 786 /* following updates require alloc/sleep/spin that is not isr safe, 787 * null means no updates 788 */ 789 const struct dc_gamma *gamma; 790 const struct dc_transfer_func *in_transfer_func; 791 792 const struct dc_csc_transform *input_csc_color_matrix; 793 const struct fixed31_32 *coeff_reduction_factor; 794 #if defined(CONFIG_DRM_AMD_DC_DCN2_0) 795 const struct dc_transfer_func *func_shaper; 796 const struct dc_3dlut *lut3d_func; 797 const struct dc_transfer_func *blend_tf; 798 #endif 799 }; 800 801 /* 802 * Create a new surface with default parameters; 803 */ 804 struct dc_plane_state *dc_create_plane_state(struct dc *dc); 805 const struct dc_plane_status *dc_plane_get_status( 806 const struct dc_plane_state *plane_state); 807 808 void dc_plane_state_retain(struct dc_plane_state *plane_state); 809 void dc_plane_state_release(struct dc_plane_state *plane_state); 810 811 void dc_gamma_retain(struct dc_gamma *dc_gamma); 812 void dc_gamma_release(struct dc_gamma **dc_gamma); 813 struct dc_gamma *dc_create_gamma(void); 814 815 void dc_transfer_func_retain(struct dc_transfer_func *dc_tf); 816 void dc_transfer_func_release(struct dc_transfer_func *dc_tf); 817 struct dc_transfer_func *dc_create_transfer_func(void); 818 819 #if defined(CONFIG_DRM_AMD_DC_DCN2_0) 820 struct dc_3dlut *dc_create_3dlut_func(void); 821 void dc_3dlut_func_release(struct dc_3dlut *lut); 822 void dc_3dlut_func_retain(struct dc_3dlut *lut); 823 #endif 824 /* 825 * This structure holds a surface address. There could be multiple addresses 826 * in cases such as Stereo 3D, Planar YUV, etc. Other per-flip attributes such 827 * as frame durations and DCC format can also be set. 828 */ 829 struct dc_flip_addrs { 830 struct dc_plane_address address; 831 unsigned int flip_timestamp_in_us; 832 bool flip_immediate; 833 /* TODO: add flip duration for FreeSync */ 834 }; 835 836 bool dc_post_update_surfaces_to_stream( 837 struct dc *dc); 838 839 #include "dc_stream.h" 840 841 /* 842 * Structure to store surface/stream associations for validation 843 */ 844 struct dc_validation_set { 845 struct dc_stream_state *stream; 846 struct dc_plane_state *plane_states[MAX_SURFACES]; 847 uint8_t plane_count; 848 }; 849 850 bool dc_validate_seamless_boot_timing(const struct dc *dc, 851 const struct dc_sink *sink, 852 struct dc_crtc_timing *crtc_timing); 853 854 enum dc_status dc_validate_plane(struct dc *dc, const struct dc_plane_state *plane_state); 855 856 void get_clock_requirements_for_state(struct dc_state *state, struct AsicStateEx *info); 857 858 bool dc_set_generic_gpio_for_stereo(bool enable, 859 struct gpio_service *gpio_service); 860 861 /* 862 * fast_validate: we return after determining if we can support the new state, 863 * but before we populate the programming info 864 */ 865 enum dc_status dc_validate_global_state( 866 struct dc *dc, 867 struct dc_state *new_ctx, 868 bool fast_validate); 869 870 871 void dc_resource_state_construct( 872 const struct dc *dc, 873 struct dc_state *dst_ctx); 874 875 void dc_resource_state_copy_construct( 876 const struct dc_state *src_ctx, 877 struct dc_state *dst_ctx); 878 879 void dc_resource_state_copy_construct_current( 880 const struct dc *dc, 881 struct dc_state *dst_ctx); 882 883 void dc_resource_state_destruct(struct dc_state *context); 884 885 /* 886 * TODO update to make it about validation sets 887 * Set up streams and links associated to drive sinks 888 * The streams parameter is an absolute set of all active streams. 889 * 890 * After this call: 891 * Phy, Encoder, Timing Generator are programmed and enabled. 892 * New streams are enabled with blank stream; no memory read. 893 */ 894 bool dc_commit_state(struct dc *dc, struct dc_state *context); 895 896 897 struct dc_state *dc_create_state(struct dc *dc); 898 struct dc_state *dc_copy_state(struct dc_state *src_ctx); 899 void dc_retain_state(struct dc_state *context); 900 void dc_release_state(struct dc_state *context); 901 902 /******************************************************************************* 903 * Link Interfaces 904 ******************************************************************************/ 905 906 struct dpcd_caps { 907 union dpcd_rev dpcd_rev; 908 union max_lane_count max_ln_count; 909 union max_down_spread max_down_spread; 910 union dprx_feature dprx_feature; 911 912 /* valid only for eDP v1.4 or higher*/ 913 uint8_t edp_supported_link_rates_count; 914 enum dc_link_rate edp_supported_link_rates[8]; 915 916 /* dongle type (DP converter, CV smart dongle) */ 917 enum display_dongle_type dongle_type; 918 /* branch device or sink device */ 919 bool is_branch_dev; 920 /* Dongle's downstream count. */ 921 union sink_count sink_count; 922 /* If dongle_type == DISPLAY_DONGLE_DP_HDMI_CONVERTER, 923 indicates 'Frame Sequential-to-lllFrame Pack' conversion capability.*/ 924 struct dc_dongle_caps dongle_caps; 925 926 uint32_t sink_dev_id; 927 int8_t sink_dev_id_str[6]; 928 int8_t sink_hw_revision; 929 int8_t sink_fw_revision[2]; 930 931 uint32_t branch_dev_id; 932 int8_t branch_dev_name[6]; 933 int8_t branch_hw_revision; 934 int8_t branch_fw_revision[2]; 935 936 bool allow_invalid_MSA_timing_param; 937 bool panel_mode_edp; 938 bool dpcd_display_control_capable; 939 bool ext_receiver_cap_field_present; 940 #ifdef CONFIG_DRM_AMD_DC_DSC_SUPPORT 941 union dpcd_fec_capability fec_cap; 942 struct dpcd_dsc_capabilities dsc_caps; 943 #endif 944 }; 945 946 #include "dc_link.h" 947 948 /******************************************************************************* 949 * Sink Interfaces - A sink corresponds to a display output device 950 ******************************************************************************/ 951 952 struct dc_container_id { 953 // 128bit GUID in binary form 954 unsigned char guid[16]; 955 // 8 byte port ID -> ELD.PortID 956 unsigned int portId[2]; 957 // 128bit GUID in binary formufacturer name -> ELD.ManufacturerName 958 unsigned short manufacturerName; 959 // 2 byte product code -> ELD.ProductCode 960 unsigned short productCode; 961 }; 962 963 964 #ifdef CONFIG_DRM_AMD_DC_DSC_SUPPORT 965 struct dc_sink_dsc_caps { 966 // 'true' if these are virtual DPCD's DSC caps (immediately upstream of sink in MST topology), 967 // 'false' if they are sink's DSC caps 968 bool is_virtual_dpcd_dsc; 969 struct dsc_dec_dpcd_caps dsc_dec_caps; 970 }; 971 #endif 972 973 /* 974 * The sink structure contains EDID and other display device properties 975 */ 976 struct dc_sink { 977 enum signal_type sink_signal; 978 struct dc_edid dc_edid; /* raw edid */ 979 struct dc_edid_caps edid_caps; /* parse display caps */ 980 struct dc_container_id *dc_container_id; 981 uint32_t dongle_max_pix_clk; 982 void *priv; 983 struct stereo_3d_features features_3d[TIMING_3D_FORMAT_MAX]; 984 bool converter_disable_audio; 985 986 #ifdef CONFIG_DRM_AMD_DC_DSC_SUPPORT 987 struct dc_sink_dsc_caps sink_dsc_caps; 988 #endif 989 990 /* private to DC core */ 991 struct dc_link *link; 992 struct dc_context *ctx; 993 994 uint32_t sink_id; 995 996 /* private to dc_sink.c */ 997 // refcount must be the last member in dc_sink, since we want the 998 // sink structure to be logically cloneable up to (but not including) 999 // refcount 1000 struct kref refcount; 1001 }; 1002 1003 void dc_sink_retain(struct dc_sink *sink); 1004 void dc_sink_release(struct dc_sink *sink); 1005 1006 struct dc_sink_init_data { 1007 enum signal_type sink_signal; 1008 struct dc_link *link; 1009 uint32_t dongle_max_pix_clk; 1010 bool converter_disable_audio; 1011 }; 1012 1013 struct dc_sink *dc_sink_create(const struct dc_sink_init_data *init_params); 1014 1015 /* Newer interfaces */ 1016 struct dc_cursor { 1017 struct dc_plane_address address; 1018 struct dc_cursor_attributes attributes; 1019 }; 1020 1021 1022 /******************************************************************************* 1023 * Interrupt interfaces 1024 ******************************************************************************/ 1025 enum dc_irq_source dc_interrupt_to_irq_source( 1026 struct dc *dc, 1027 uint32_t src_id, 1028 uint32_t ext_id); 1029 bool dc_interrupt_set(struct dc *dc, enum dc_irq_source src, bool enable); 1030 void dc_interrupt_ack(struct dc *dc, enum dc_irq_source src); 1031 enum dc_irq_source dc_get_hpd_irq_source_at_index( 1032 struct dc *dc, uint32_t link_index); 1033 1034 /******************************************************************************* 1035 * Power Interfaces 1036 ******************************************************************************/ 1037 1038 void dc_set_power_state( 1039 struct dc *dc, 1040 enum dc_acpi_cm_power_state power_state); 1041 void dc_resume(struct dc *dc); 1042 unsigned int dc_get_current_backlight_pwm(struct dc *dc); 1043 unsigned int dc_get_target_backlight_pwm(struct dc *dc); 1044 1045 bool dc_is_dmcu_initialized(struct dc *dc); 1046 1047 enum dc_status dc_set_clock(struct dc *dc, enum dc_clock_type clock_type, uint32_t clk_khz, uint32_t stepping); 1048 void dc_get_clock(struct dc *dc, enum dc_clock_type clock_type, struct dc_clock_config *clock_cfg); 1049 #if defined(CONFIG_DRM_AMD_DC_DSC_SUPPORT) 1050 /******************************************************************************* 1051 * DSC Interfaces 1052 ******************************************************************************/ 1053 #include "dc_dsc.h" 1054 #endif 1055 #endif /* DC_INTERFACE_H_ */ 1056