1 /* 2 * Copyright 2012-14 Advanced Micro Devices, Inc. 3 * 4 * Permission is hereby granted, free of charge, to any person obtaining a 5 * copy of this software and associated documentation files (the "Software"), 6 * to deal in the Software without restriction, including without limitation 7 * the rights to use, copy, modify, merge, publish, distribute, sublicense, 8 * and/or sell copies of the Software, and to permit persons to whom the 9 * Software is furnished to do so, subject to the following conditions: 10 * 11 * The above copyright notice and this permission notice shall be included in 12 * all copies or substantial portions of the Software. 13 * 14 * THE SOFTWARE IS PROVIDED "AS IS", WITHOUT WARRANTY OF ANY KIND, EXPRESS OR 15 * IMPLIED, INCLUDING BUT NOT LIMITED TO THE WARRANTIES OF MERCHANTABILITY, 16 * FITNESS FOR A PARTICULAR PURPOSE AND NONINFRINGEMENT. IN NO EVENT SHALL 17 * THE COPYRIGHT HOLDER(S) OR AUTHOR(S) BE LIABLE FOR ANY CLAIM, DAMAGES OR 18 * OTHER LIABILITY, WHETHER IN AN ACTION OF CONTRACT, TORT OR OTHERWISE, 19 * ARISING FROM, OUT OF OR IN CONNECTION WITH THE SOFTWARE OR THE USE OR 20 * OTHER DEALINGS IN THE SOFTWARE. 21 * 22 * Authors: AMD 23 * 24 */ 25 26 #ifndef DC_INTERFACE_H_ 27 #define DC_INTERFACE_H_ 28 29 #include "dc_types.h" 30 #include "grph_object_defs.h" 31 #include "logger_types.h" 32 #if defined(CONFIG_DRM_AMD_DC_HDCP) 33 #include "hdcp_types.h" 34 #endif 35 #include "gpio_types.h" 36 #include "link_service_types.h" 37 #include "grph_object_ctrl_defs.h" 38 #include <inc/hw/opp.h> 39 40 #include "inc/hw_sequencer.h" 41 #include "inc/compressor.h" 42 #include "inc/hw/dmcu.h" 43 #include "dml/display_mode_lib.h" 44 45 #define DC_VER "3.2.110" 46 47 #define MAX_SURFACES 3 48 #define MAX_PLANES 6 49 #define MAX_STREAMS 6 50 #define MAX_SINKS_PER_LINK 4 51 52 /******************************************************************************* 53 * Display Core Interfaces 54 ******************************************************************************/ 55 struct dc_versions { 56 const char *dc_ver; 57 struct dmcu_version dmcu_version; 58 }; 59 60 enum dp_protocol_version { 61 DP_VERSION_1_4, 62 }; 63 64 enum dc_plane_type { 65 DC_PLANE_TYPE_INVALID, 66 DC_PLANE_TYPE_DCE_RGB, 67 DC_PLANE_TYPE_DCE_UNDERLAY, 68 DC_PLANE_TYPE_DCN_UNIVERSAL, 69 }; 70 71 struct dc_plane_cap { 72 enum dc_plane_type type; 73 uint32_t blends_with_above : 1; 74 uint32_t blends_with_below : 1; 75 uint32_t per_pixel_alpha : 1; 76 struct { 77 uint32_t argb8888 : 1; 78 uint32_t nv12 : 1; 79 uint32_t fp16 : 1; 80 uint32_t p010 : 1; 81 uint32_t ayuv : 1; 82 } pixel_format_support; 83 // max upscaling factor x1000 84 // upscaling factors are always >= 1 85 // for example, 1080p -> 8K is 4.0, or 4000 raw value 86 struct { 87 uint32_t argb8888; 88 uint32_t nv12; 89 uint32_t fp16; 90 } max_upscale_factor; 91 // max downscale factor x1000 92 // downscale factors are always <= 1 93 // for example, 8K -> 1080p is 0.25, or 250 raw value 94 struct { 95 uint32_t argb8888; 96 uint32_t nv12; 97 uint32_t fp16; 98 } max_downscale_factor; 99 // minimal width/height 100 uint32_t min_width; 101 uint32_t min_height; 102 }; 103 104 // Color management caps (DPP and MPC) 105 struct rom_curve_caps { 106 uint16_t srgb : 1; 107 uint16_t bt2020 : 1; 108 uint16_t gamma2_2 : 1; 109 uint16_t pq : 1; 110 uint16_t hlg : 1; 111 }; 112 113 struct dpp_color_caps { 114 uint16_t dcn_arch : 1; // all DCE generations treated the same 115 // input lut is different than most LUTs, just plain 256-entry lookup 116 uint16_t input_lut_shared : 1; // shared with DGAM 117 uint16_t icsc : 1; 118 uint16_t dgam_ram : 1; 119 uint16_t post_csc : 1; // before gamut remap 120 uint16_t gamma_corr : 1; 121 122 // hdr_mult and gamut remap always available in DPP (in that order) 123 // 3d lut implies shaper LUT, 124 // it may be shared with MPC - check MPC:shared_3d_lut flag 125 uint16_t hw_3d_lut : 1; 126 uint16_t ogam_ram : 1; // blnd gam 127 uint16_t ocsc : 1; 128 struct rom_curve_caps dgam_rom_caps; 129 struct rom_curve_caps ogam_rom_caps; 130 }; 131 132 struct mpc_color_caps { 133 uint16_t gamut_remap : 1; 134 uint16_t ogam_ram : 1; 135 uint16_t ocsc : 1; 136 uint16_t num_3dluts : 3; //3d lut always assumes a preceding shaper LUT 137 uint16_t shared_3d_lut:1; //can be in either DPP or MPC, but single instance 138 139 struct rom_curve_caps ogam_rom_caps; 140 }; 141 142 struct dc_color_caps { 143 struct dpp_color_caps dpp; 144 struct mpc_color_caps mpc; 145 }; 146 147 struct dc_caps { 148 uint32_t max_streams; 149 uint32_t max_links; 150 uint32_t max_audios; 151 uint32_t max_slave_planes; 152 uint32_t max_planes; 153 uint32_t max_downscale_ratio; 154 uint32_t i2c_speed_in_khz; 155 uint32_t i2c_speed_in_khz_hdcp; 156 uint32_t dmdata_alloc_size; 157 unsigned int max_cursor_size; 158 unsigned int max_video_width; 159 unsigned int min_horizontal_blanking_period; 160 int linear_pitch_alignment; 161 bool dcc_const_color; 162 bool dynamic_audio; 163 bool is_apu; 164 bool dual_link_dvi; 165 bool post_blend_color_processing; 166 bool force_dp_tps4_for_cp2520; 167 bool disable_dp_clk_share; 168 bool psp_setup_panel_mode; 169 bool extended_aux_timeout_support; 170 bool dmcub_support; 171 enum dp_protocol_version max_dp_protocol_version; 172 struct dc_plane_cap planes[MAX_PLANES]; 173 struct dc_color_caps color; 174 }; 175 176 struct dc_bug_wa { 177 bool no_connect_phy_config; 178 bool dedcn20_305_wa; 179 bool skip_clock_update; 180 bool lt_early_cr_pattern; 181 }; 182 183 struct dc_dcc_surface_param { 184 struct dc_size surface_size; 185 enum surface_pixel_format format; 186 enum swizzle_mode_values swizzle_mode; 187 enum dc_scan_direction scan; 188 }; 189 190 struct dc_dcc_setting { 191 unsigned int max_compressed_blk_size; 192 unsigned int max_uncompressed_blk_size; 193 bool independent_64b_blks; 194 #if defined(CONFIG_DRM_AMD_DC_DCN) 195 //These bitfields to be used starting with DCN 3.0 196 struct { 197 uint32_t dcc_256_64_64 : 1;//available in ASICs before DCN 3.0 (the worst compression case) 198 uint32_t dcc_128_128_uncontrained : 1; //available in ASICs before DCN 3.0 199 uint32_t dcc_256_128_128 : 1; //available starting with DCN 3.0 200 uint32_t dcc_256_256_unconstrained : 1; //available in ASICs before DCN 3.0 (the best compression case) 201 } dcc_controls; 202 #endif 203 }; 204 205 struct dc_surface_dcc_cap { 206 union { 207 struct { 208 struct dc_dcc_setting rgb; 209 } grph; 210 211 struct { 212 struct dc_dcc_setting luma; 213 struct dc_dcc_setting chroma; 214 } video; 215 }; 216 217 bool capable; 218 bool const_color_support; 219 }; 220 221 struct dc_static_screen_params { 222 struct { 223 bool force_trigger; 224 bool cursor_update; 225 bool surface_update; 226 bool overlay_update; 227 } triggers; 228 unsigned int num_frames; 229 }; 230 231 232 /* Surface update type is used by dc_update_surfaces_and_stream 233 * The update type is determined at the very beginning of the function based 234 * on parameters passed in and decides how much programming (or updating) is 235 * going to be done during the call. 236 * 237 * UPDATE_TYPE_FAST is used for really fast updates that do not require much 238 * logical calculations or hardware register programming. This update MUST be 239 * ISR safe on windows. Currently fast update will only be used to flip surface 240 * address. 241 * 242 * UPDATE_TYPE_MED is used for slower updates which require significant hw 243 * re-programming however do not affect bandwidth consumption or clock 244 * requirements. At present, this is the level at which front end updates 245 * that do not require us to run bw_calcs happen. These are in/out transfer func 246 * updates, viewport offset changes, recout size changes and pixel depth changes. 247 * This update can be done at ISR, but we want to minimize how often this happens. 248 * 249 * UPDATE_TYPE_FULL is slow. Really slow. This requires us to recalculate our 250 * bandwidth and clocks, possibly rearrange some pipes and reprogram anything front 251 * end related. Any time viewport dimensions, recout dimensions, scaling ratios or 252 * gamma need to be adjusted or pipe needs to be turned on (or disconnected) we do 253 * a full update. This cannot be done at ISR level and should be a rare event. 254 * Unless someone is stress testing mpo enter/exit, playing with colour or adjusting 255 * underscan we don't expect to see this call at all. 256 */ 257 258 enum surface_update_type { 259 UPDATE_TYPE_FAST, /* super fast, safe to execute in isr */ 260 UPDATE_TYPE_MED, /* ISR safe, most of programming needed, no bw/clk change*/ 261 UPDATE_TYPE_FULL, /* may need to shuffle resources */ 262 }; 263 264 /* Forward declaration*/ 265 struct dc; 266 struct dc_plane_state; 267 struct dc_state; 268 269 270 struct dc_cap_funcs { 271 bool (*get_dcc_compression_cap)(const struct dc *dc, 272 const struct dc_dcc_surface_param *input, 273 struct dc_surface_dcc_cap *output); 274 }; 275 276 struct link_training_settings; 277 278 279 /* Structure to hold configuration flags set by dm at dc creation. */ 280 struct dc_config { 281 bool gpu_vm_support; 282 bool disable_disp_pll_sharing; 283 bool fbc_support; 284 bool optimize_edp_link_rate; 285 bool disable_fractional_pwm; 286 bool allow_seamless_boot_optimization; 287 bool power_down_display_on_boot; 288 bool edp_not_connected; 289 bool force_enum_edp; 290 bool forced_clocks; 291 bool allow_lttpr_non_transparent_mode; 292 bool multi_mon_pp_mclk_switch; 293 bool disable_dmcu; 294 bool enable_4to1MPC; 295 #if defined(CONFIG_DRM_AMD_DC_DCN) 296 bool clamp_min_dcfclk; 297 #endif 298 }; 299 300 enum visual_confirm { 301 VISUAL_CONFIRM_DISABLE = 0, 302 VISUAL_CONFIRM_SURFACE = 1, 303 VISUAL_CONFIRM_HDR = 2, 304 VISUAL_CONFIRM_MPCTREE = 4, 305 VISUAL_CONFIRM_PSR = 5, 306 }; 307 308 enum dcc_option { 309 DCC_ENABLE = 0, 310 DCC_DISABLE = 1, 311 DCC_HALF_REQ_DISALBE = 2, 312 }; 313 314 enum pipe_split_policy { 315 MPC_SPLIT_DYNAMIC = 0, 316 MPC_SPLIT_AVOID = 1, 317 MPC_SPLIT_AVOID_MULT_DISP = 2, 318 }; 319 320 enum wm_report_mode { 321 WM_REPORT_DEFAULT = 0, 322 WM_REPORT_OVERRIDE = 1, 323 }; 324 enum dtm_pstate{ 325 dtm_level_p0 = 0,/*highest voltage*/ 326 dtm_level_p1, 327 dtm_level_p2, 328 dtm_level_p3, 329 dtm_level_p4,/*when active_display_count = 0*/ 330 }; 331 332 enum dcn_pwr_state { 333 DCN_PWR_STATE_UNKNOWN = -1, 334 DCN_PWR_STATE_MISSION_MODE = 0, 335 DCN_PWR_STATE_LOW_POWER = 3, 336 }; 337 338 /* 339 * For any clocks that may differ per pipe 340 * only the max is stored in this structure 341 */ 342 struct dc_clocks { 343 int dispclk_khz; 344 int dppclk_khz; 345 int disp_dpp_voltage_level_khz; 346 int dcfclk_khz; 347 int socclk_khz; 348 int dcfclk_deep_sleep_khz; 349 int fclk_khz; 350 int phyclk_khz; 351 int dramclk_khz; 352 bool p_state_change_support; 353 enum dcn_pwr_state pwr_state; 354 /* 355 * Elements below are not compared for the purposes of 356 * optimization required 357 */ 358 bool prev_p_state_change_support; 359 enum dtm_pstate dtm_level; 360 int max_supported_dppclk_khz; 361 int max_supported_dispclk_khz; 362 int bw_dppclk_khz; /*a copy of dppclk_khz*/ 363 int bw_dispclk_khz; 364 }; 365 366 struct dc_bw_validation_profile { 367 bool enable; 368 369 unsigned long long total_ticks; 370 unsigned long long voltage_level_ticks; 371 unsigned long long watermark_ticks; 372 unsigned long long rq_dlg_ticks; 373 374 unsigned long long total_count; 375 unsigned long long skip_fast_count; 376 unsigned long long skip_pass_count; 377 unsigned long long skip_fail_count; 378 }; 379 380 #define BW_VAL_TRACE_SETUP() \ 381 unsigned long long end_tick = 0; \ 382 unsigned long long voltage_level_tick = 0; \ 383 unsigned long long watermark_tick = 0; \ 384 unsigned long long start_tick = dc->debug.bw_val_profile.enable ? \ 385 dm_get_timestamp(dc->ctx) : 0 386 387 #define BW_VAL_TRACE_COUNT() \ 388 if (dc->debug.bw_val_profile.enable) \ 389 dc->debug.bw_val_profile.total_count++ 390 391 #define BW_VAL_TRACE_SKIP(status) \ 392 if (dc->debug.bw_val_profile.enable) { \ 393 if (!voltage_level_tick) \ 394 voltage_level_tick = dm_get_timestamp(dc->ctx); \ 395 dc->debug.bw_val_profile.skip_ ## status ## _count++; \ 396 } 397 398 #define BW_VAL_TRACE_END_VOLTAGE_LEVEL() \ 399 if (dc->debug.bw_val_profile.enable) \ 400 voltage_level_tick = dm_get_timestamp(dc->ctx) 401 402 #define BW_VAL_TRACE_END_WATERMARKS() \ 403 if (dc->debug.bw_val_profile.enable) \ 404 watermark_tick = dm_get_timestamp(dc->ctx) 405 406 #define BW_VAL_TRACE_FINISH() \ 407 if (dc->debug.bw_val_profile.enable) { \ 408 end_tick = dm_get_timestamp(dc->ctx); \ 409 dc->debug.bw_val_profile.total_ticks += end_tick - start_tick; \ 410 dc->debug.bw_val_profile.voltage_level_ticks += voltage_level_tick - start_tick; \ 411 if (watermark_tick) { \ 412 dc->debug.bw_val_profile.watermark_ticks += watermark_tick - voltage_level_tick; \ 413 dc->debug.bw_val_profile.rq_dlg_ticks += end_tick - watermark_tick; \ 414 } \ 415 } 416 417 union mem_low_power_enable_options { 418 struct { 419 bool mpc: 1; 420 bool optc: 1; 421 } bits; 422 uint32_t u32All; 423 }; 424 425 struct dc_debug_options { 426 enum visual_confirm visual_confirm; 427 bool sanity_checks; 428 bool max_disp_clk; 429 bool surface_trace; 430 bool timing_trace; 431 bool clock_trace; 432 bool validation_trace; 433 bool bandwidth_calcs_trace; 434 int max_downscale_src_width; 435 436 /* stutter efficiency related */ 437 bool disable_stutter; 438 bool use_max_lb; 439 enum dcc_option disable_dcc; 440 enum pipe_split_policy pipe_split_policy; 441 bool force_single_disp_pipe_split; 442 bool voltage_align_fclk; 443 444 bool disable_dfs_bypass; 445 bool disable_dpp_power_gate; 446 bool disable_hubp_power_gate; 447 bool disable_dsc_power_gate; 448 int dsc_min_slice_height_override; 449 int dsc_bpp_increment_div; 450 bool native422_support; 451 bool disable_pplib_wm_range; 452 enum wm_report_mode pplib_wm_report_mode; 453 unsigned int min_disp_clk_khz; 454 unsigned int min_dpp_clk_khz; 455 int sr_exit_time_dpm0_ns; 456 int sr_enter_plus_exit_time_dpm0_ns; 457 int sr_exit_time_ns; 458 int sr_enter_plus_exit_time_ns; 459 int urgent_latency_ns; 460 uint32_t underflow_assert_delay_us; 461 int percent_of_ideal_drambw; 462 int dram_clock_change_latency_ns; 463 bool optimized_watermark; 464 int always_scale; 465 bool disable_pplib_clock_request; 466 bool disable_clock_gate; 467 bool disable_mem_low_power; 468 bool disable_dmcu; 469 bool disable_psr; 470 bool force_abm_enable; 471 bool disable_stereo_support; 472 bool vsr_support; 473 bool performance_trace; 474 bool az_endpoint_mute_only; 475 bool always_use_regamma; 476 bool p010_mpo_support; 477 bool recovery_enabled; 478 bool avoid_vbios_exec_table; 479 bool scl_reset_length10; 480 bool hdmi20_disable; 481 bool skip_detection_link_training; 482 bool edid_read_retry_times; 483 bool remove_disconnect_edp; 484 unsigned int force_odm_combine; //bit vector based on otg inst 485 #if defined(CONFIG_DRM_AMD_DC_DCN) 486 unsigned int force_odm_combine_4to1; //bit vector based on otg inst 487 #endif 488 unsigned int force_fclk_khz; 489 bool enable_tri_buf; 490 bool dmub_offload_enabled; 491 bool dmcub_emulation; 492 #if defined(CONFIG_DRM_AMD_DC_DCN) 493 bool disable_idle_power_optimizations; 494 #endif 495 bool dmub_command_table; /* for testing only */ 496 struct dc_bw_validation_profile bw_val_profile; 497 bool disable_fec; 498 bool disable_48mhz_pwrdwn; 499 /* This forces a hard min on the DCFCLK requested to SMU/PP 500 * watermarks are not affected. 501 */ 502 unsigned int force_min_dcfclk_mhz; 503 #if defined(CONFIG_DRM_AMD_DC_DCN) 504 int dwb_fi_phase; 505 #endif 506 bool disable_timing_sync; 507 bool cm_in_bypass; 508 int force_clock_mode;/*every mode change.*/ 509 510 bool disable_dram_clock_change_vactive_support; 511 bool validate_dml_output; 512 bool enable_dmcub_surface_flip; 513 bool usbc_combo_phy_reset_wa; 514 bool disable_dsc; 515 bool enable_dram_clock_change_one_display_vactive; 516 bool force_ignore_link_settings; 517 union mem_low_power_enable_options enable_mem_low_power; 518 }; 519 520 struct dc_debug_data { 521 uint32_t ltFailCount; 522 uint32_t i2cErrorCount; 523 uint32_t auxErrorCount; 524 }; 525 526 struct dc_phy_addr_space_config { 527 struct { 528 uint64_t start_addr; 529 uint64_t end_addr; 530 uint64_t fb_top; 531 uint64_t fb_offset; 532 uint64_t fb_base; 533 uint64_t agp_top; 534 uint64_t agp_bot; 535 uint64_t agp_base; 536 } system_aperture; 537 538 struct { 539 uint64_t page_table_start_addr; 540 uint64_t page_table_end_addr; 541 uint64_t page_table_base_addr; 542 } gart_config; 543 544 bool valid; 545 bool is_hvm_enabled; 546 uint64_t page_table_default_page_addr; 547 }; 548 549 struct dc_virtual_addr_space_config { 550 uint64_t page_table_base_addr; 551 uint64_t page_table_start_addr; 552 uint64_t page_table_end_addr; 553 uint32_t page_table_block_size_in_bytes; 554 uint8_t page_table_depth; // 1 = 1 level, 2 = 2 level, etc. 0 = invalid 555 }; 556 557 struct dc_bounding_box_overrides { 558 int sr_exit_time_ns; 559 int sr_enter_plus_exit_time_ns; 560 int urgent_latency_ns; 561 int percent_of_ideal_drambw; 562 int dram_clock_change_latency_ns; 563 int dummy_clock_change_latency_ns; 564 /* This forces a hard min on the DCFCLK we use 565 * for DML. Unlike the debug option for forcing 566 * DCFCLK, this override affects watermark calculations 567 */ 568 int min_dcfclk_mhz; 569 }; 570 571 struct dc_state; 572 struct resource_pool; 573 struct dce_hwseq; 574 struct gpu_info_soc_bounding_box_v1_0; 575 struct dc { 576 struct dc_versions versions; 577 struct dc_caps caps; 578 struct dc_cap_funcs cap_funcs; 579 struct dc_config config; 580 struct dc_debug_options debug; 581 struct dc_bounding_box_overrides bb_overrides; 582 struct dc_bug_wa work_arounds; 583 struct dc_context *ctx; 584 struct dc_phy_addr_space_config vm_pa_config; 585 586 uint8_t link_count; 587 struct dc_link *links[MAX_PIPES * 2]; 588 589 struct dc_state *current_state; 590 struct resource_pool *res_pool; 591 592 struct clk_mgr *clk_mgr; 593 594 /* Display Engine Clock levels */ 595 struct dm_pp_clock_levels sclk_lvls; 596 597 /* Inputs into BW and WM calculations. */ 598 struct bw_calcs_dceip *bw_dceip; 599 struct bw_calcs_vbios *bw_vbios; 600 #ifdef CONFIG_DRM_AMD_DC_DCN 601 struct dcn_soc_bounding_box *dcn_soc; 602 struct dcn_ip_params *dcn_ip; 603 struct display_mode_lib dml; 604 #endif 605 606 /* HW functions */ 607 struct hw_sequencer_funcs hwss; 608 struct dce_hwseq *hwseq; 609 610 /* Require to optimize clocks and bandwidth for added/removed planes */ 611 bool optimized_required; 612 bool wm_optimized_required; 613 #if defined(CONFIG_DRM_AMD_DC_DCN) 614 bool idle_optimizations_allowed; 615 #endif 616 617 /* Require to maintain clocks and bandwidth for UEFI enabled HW */ 618 int optimize_seamless_boot_streams; 619 620 /* FBC compressor */ 621 struct compressor *fbc_compressor; 622 623 struct dc_debug_data debug_data; 624 struct dpcd_vendor_signature vendor_signature; 625 626 const char *build_id; 627 struct vm_helper *vm_helper; 628 const struct gpu_info_soc_bounding_box_v1_0 *soc_bounding_box; 629 }; 630 631 enum frame_buffer_mode { 632 FRAME_BUFFER_MODE_LOCAL_ONLY = 0, 633 FRAME_BUFFER_MODE_ZFB_ONLY, 634 FRAME_BUFFER_MODE_MIXED_ZFB_AND_LOCAL, 635 } ; 636 637 struct dchub_init_data { 638 int64_t zfb_phys_addr_base; 639 int64_t zfb_mc_base_addr; 640 uint64_t zfb_size_in_byte; 641 enum frame_buffer_mode fb_mode; 642 bool dchub_initialzied; 643 bool dchub_info_valid; 644 }; 645 646 struct dc_init_data { 647 struct hw_asic_id asic_id; 648 void *driver; /* ctx */ 649 struct cgs_device *cgs_device; 650 struct dc_bounding_box_overrides bb_overrides; 651 652 int num_virtual_links; 653 /* 654 * If 'vbios_override' not NULL, it will be called instead 655 * of the real VBIOS. Intended use is Diagnostics on FPGA. 656 */ 657 struct dc_bios *vbios_override; 658 enum dce_environment dce_environment; 659 660 struct dmub_offload_funcs *dmub_if; 661 struct dc_reg_helper_state *dmub_offload; 662 663 struct dc_config flags; 664 uint64_t log_mask; 665 666 /** 667 * gpu_info FW provided soc bounding box struct or 0 if not 668 * available in FW 669 */ 670 const struct gpu_info_soc_bounding_box_v1_0 *soc_bounding_box; 671 struct dpcd_vendor_signature vendor_signature; 672 #if defined(CONFIG_DRM_AMD_DC_DCN) 673 bool force_smu_not_present; 674 #endif 675 bool force_ignore_link_settings; 676 }; 677 678 struct dc_callback_init { 679 #ifdef CONFIG_DRM_AMD_DC_HDCP 680 struct cp_psp cp_psp; 681 #else 682 uint8_t reserved; 683 #endif 684 }; 685 686 struct dc *dc_create(const struct dc_init_data *init_params); 687 void dc_hardware_init(struct dc *dc); 688 689 int dc_get_vmid_use_vector(struct dc *dc); 690 void dc_setup_vm_context(struct dc *dc, struct dc_virtual_addr_space_config *va_config, int vmid); 691 /* Returns the number of vmids supported */ 692 int dc_setup_system_context(struct dc *dc, struct dc_phy_addr_space_config *pa_config); 693 void dc_init_callbacks(struct dc *dc, 694 const struct dc_callback_init *init_params); 695 void dc_deinit_callbacks(struct dc *dc); 696 void dc_destroy(struct dc **dc); 697 698 /******************************************************************************* 699 * Surface Interfaces 700 ******************************************************************************/ 701 702 enum { 703 TRANSFER_FUNC_POINTS = 1025 704 }; 705 706 struct dc_hdr_static_metadata { 707 /* display chromaticities and white point in units of 0.00001 */ 708 unsigned int chromaticity_green_x; 709 unsigned int chromaticity_green_y; 710 unsigned int chromaticity_blue_x; 711 unsigned int chromaticity_blue_y; 712 unsigned int chromaticity_red_x; 713 unsigned int chromaticity_red_y; 714 unsigned int chromaticity_white_point_x; 715 unsigned int chromaticity_white_point_y; 716 717 uint32_t min_luminance; 718 uint32_t max_luminance; 719 uint32_t maximum_content_light_level; 720 uint32_t maximum_frame_average_light_level; 721 }; 722 723 enum dc_transfer_func_type { 724 TF_TYPE_PREDEFINED, 725 TF_TYPE_DISTRIBUTED_POINTS, 726 TF_TYPE_BYPASS, 727 TF_TYPE_HWPWL 728 }; 729 730 struct dc_transfer_func_distributed_points { 731 struct fixed31_32 red[TRANSFER_FUNC_POINTS]; 732 struct fixed31_32 green[TRANSFER_FUNC_POINTS]; 733 struct fixed31_32 blue[TRANSFER_FUNC_POINTS]; 734 735 uint16_t end_exponent; 736 uint16_t x_point_at_y1_red; 737 uint16_t x_point_at_y1_green; 738 uint16_t x_point_at_y1_blue; 739 }; 740 741 enum dc_transfer_func_predefined { 742 TRANSFER_FUNCTION_SRGB, 743 TRANSFER_FUNCTION_BT709, 744 TRANSFER_FUNCTION_PQ, 745 TRANSFER_FUNCTION_LINEAR, 746 TRANSFER_FUNCTION_UNITY, 747 TRANSFER_FUNCTION_HLG, 748 TRANSFER_FUNCTION_HLG12, 749 TRANSFER_FUNCTION_GAMMA22, 750 TRANSFER_FUNCTION_GAMMA24, 751 TRANSFER_FUNCTION_GAMMA26 752 }; 753 754 755 struct dc_transfer_func { 756 struct kref refcount; 757 enum dc_transfer_func_type type; 758 enum dc_transfer_func_predefined tf; 759 /* FP16 1.0 reference level in nits, default is 80 nits, only for PQ*/ 760 uint32_t sdr_ref_white_level; 761 union { 762 struct pwl_params pwl; 763 struct dc_transfer_func_distributed_points tf_pts; 764 }; 765 }; 766 767 768 union dc_3dlut_state { 769 struct { 770 uint32_t initialized:1; /*if 3dlut is went through color module for initialization */ 771 uint32_t rmu_idx_valid:1; /*if mux settings are valid*/ 772 uint32_t rmu_mux_num:3; /*index of mux to use*/ 773 uint32_t mpc_rmu0_mux:4; /*select mpcc on mux, one of the following : mpcc0, mpcc1, mpcc2, mpcc3*/ 774 uint32_t mpc_rmu1_mux:4; 775 uint32_t mpc_rmu2_mux:4; 776 uint32_t reserved:15; 777 } bits; 778 uint32_t raw; 779 }; 780 781 782 struct dc_3dlut { 783 struct kref refcount; 784 struct tetrahedral_params lut_3d; 785 struct fixed31_32 hdr_multiplier; 786 union dc_3dlut_state state; 787 }; 788 /* 789 * This structure is filled in by dc_surface_get_status and contains 790 * the last requested address and the currently active address so the called 791 * can determine if there are any outstanding flips 792 */ 793 struct dc_plane_status { 794 struct dc_plane_address requested_address; 795 struct dc_plane_address current_address; 796 bool is_flip_pending; 797 bool is_right_eye; 798 }; 799 800 union surface_update_flags { 801 802 struct { 803 uint32_t addr_update:1; 804 /* Medium updates */ 805 uint32_t dcc_change:1; 806 uint32_t color_space_change:1; 807 uint32_t horizontal_mirror_change:1; 808 uint32_t per_pixel_alpha_change:1; 809 uint32_t global_alpha_change:1; 810 uint32_t hdr_mult:1; 811 uint32_t rotation_change:1; 812 uint32_t swizzle_change:1; 813 uint32_t scaling_change:1; 814 uint32_t position_change:1; 815 uint32_t in_transfer_func_change:1; 816 uint32_t input_csc_change:1; 817 uint32_t coeff_reduction_change:1; 818 uint32_t output_tf_change:1; 819 uint32_t pixel_format_change:1; 820 uint32_t plane_size_change:1; 821 uint32_t gamut_remap_change:1; 822 823 /* Full updates */ 824 uint32_t new_plane:1; 825 uint32_t bpp_change:1; 826 uint32_t gamma_change:1; 827 uint32_t bandwidth_change:1; 828 uint32_t clock_change:1; 829 uint32_t stereo_format_change:1; 830 uint32_t full_update:1; 831 } bits; 832 833 uint32_t raw; 834 }; 835 836 struct dc_plane_state { 837 struct dc_plane_address address; 838 struct dc_plane_flip_time time; 839 bool triplebuffer_flips; 840 struct scaling_taps scaling_quality; 841 struct rect src_rect; 842 struct rect dst_rect; 843 struct rect clip_rect; 844 845 struct plane_size plane_size; 846 union dc_tiling_info tiling_info; 847 848 struct dc_plane_dcc_param dcc; 849 850 struct dc_gamma *gamma_correction; 851 struct dc_transfer_func *in_transfer_func; 852 struct dc_bias_and_scale *bias_and_scale; 853 struct dc_csc_transform input_csc_color_matrix; 854 struct fixed31_32 coeff_reduction_factor; 855 struct fixed31_32 hdr_mult; 856 struct colorspace_transform gamut_remap_matrix; 857 858 // TODO: No longer used, remove 859 struct dc_hdr_static_metadata hdr_static_ctx; 860 861 enum dc_color_space color_space; 862 863 struct dc_3dlut *lut3d_func; 864 struct dc_transfer_func *in_shaper_func; 865 struct dc_transfer_func *blend_tf; 866 867 #if defined(CONFIG_DRM_AMD_DC_DCN) 868 struct dc_transfer_func *gamcor_tf; 869 #endif 870 enum surface_pixel_format format; 871 enum dc_rotation_angle rotation; 872 enum plane_stereo_format stereo_format; 873 874 bool is_tiling_rotated; 875 bool per_pixel_alpha; 876 bool global_alpha; 877 int global_alpha_value; 878 bool visible; 879 bool flip_immediate; 880 bool horizontal_mirror; 881 int layer_index; 882 883 union surface_update_flags update_flags; 884 /* private to DC core */ 885 struct dc_plane_status status; 886 struct dc_context *ctx; 887 888 /* HACK: Workaround for forcing full reprogramming under some conditions */ 889 bool force_full_update; 890 891 /* private to dc_surface.c */ 892 enum dc_irq_source irq_source; 893 struct kref refcount; 894 }; 895 896 struct dc_plane_info { 897 struct plane_size plane_size; 898 union dc_tiling_info tiling_info; 899 struct dc_plane_dcc_param dcc; 900 enum surface_pixel_format format; 901 enum dc_rotation_angle rotation; 902 enum plane_stereo_format stereo_format; 903 enum dc_color_space color_space; 904 bool horizontal_mirror; 905 bool visible; 906 bool per_pixel_alpha; 907 bool global_alpha; 908 int global_alpha_value; 909 bool input_csc_enabled; 910 int layer_index; 911 }; 912 913 struct dc_scaling_info { 914 struct rect src_rect; 915 struct rect dst_rect; 916 struct rect clip_rect; 917 struct scaling_taps scaling_quality; 918 }; 919 920 struct dc_surface_update { 921 struct dc_plane_state *surface; 922 923 /* isr safe update parameters. null means no updates */ 924 const struct dc_flip_addrs *flip_addr; 925 const struct dc_plane_info *plane_info; 926 const struct dc_scaling_info *scaling_info; 927 struct fixed31_32 hdr_mult; 928 /* following updates require alloc/sleep/spin that is not isr safe, 929 * null means no updates 930 */ 931 const struct dc_gamma *gamma; 932 const struct dc_transfer_func *in_transfer_func; 933 934 const struct dc_csc_transform *input_csc_color_matrix; 935 const struct fixed31_32 *coeff_reduction_factor; 936 const struct dc_transfer_func *func_shaper; 937 const struct dc_3dlut *lut3d_func; 938 const struct dc_transfer_func *blend_tf; 939 const struct colorspace_transform *gamut_remap_matrix; 940 }; 941 942 /* 943 * Create a new surface with default parameters; 944 */ 945 struct dc_plane_state *dc_create_plane_state(struct dc *dc); 946 const struct dc_plane_status *dc_plane_get_status( 947 const struct dc_plane_state *plane_state); 948 949 void dc_plane_state_retain(struct dc_plane_state *plane_state); 950 void dc_plane_state_release(struct dc_plane_state *plane_state); 951 952 void dc_gamma_retain(struct dc_gamma *dc_gamma); 953 void dc_gamma_release(struct dc_gamma **dc_gamma); 954 struct dc_gamma *dc_create_gamma(void); 955 956 void dc_transfer_func_retain(struct dc_transfer_func *dc_tf); 957 void dc_transfer_func_release(struct dc_transfer_func *dc_tf); 958 struct dc_transfer_func *dc_create_transfer_func(void); 959 960 struct dc_3dlut *dc_create_3dlut_func(void); 961 void dc_3dlut_func_release(struct dc_3dlut *lut); 962 void dc_3dlut_func_retain(struct dc_3dlut *lut); 963 /* 964 * This structure holds a surface address. There could be multiple addresses 965 * in cases such as Stereo 3D, Planar YUV, etc. Other per-flip attributes such 966 * as frame durations and DCC format can also be set. 967 */ 968 struct dc_flip_addrs { 969 struct dc_plane_address address; 970 unsigned int flip_timestamp_in_us; 971 bool flip_immediate; 972 /* TODO: add flip duration for FreeSync */ 973 bool triplebuffer_flips; 974 }; 975 976 void dc_post_update_surfaces_to_stream( 977 struct dc *dc); 978 979 #include "dc_stream.h" 980 981 /* 982 * Structure to store surface/stream associations for validation 983 */ 984 struct dc_validation_set { 985 struct dc_stream_state *stream; 986 struct dc_plane_state *plane_states[MAX_SURFACES]; 987 uint8_t plane_count; 988 }; 989 990 bool dc_validate_seamless_boot_timing(const struct dc *dc, 991 const struct dc_sink *sink, 992 struct dc_crtc_timing *crtc_timing); 993 994 enum dc_status dc_validate_plane(struct dc *dc, const struct dc_plane_state *plane_state); 995 996 void get_clock_requirements_for_state(struct dc_state *state, struct AsicStateEx *info); 997 998 bool dc_set_generic_gpio_for_stereo(bool enable, 999 struct gpio_service *gpio_service); 1000 1001 /* 1002 * fast_validate: we return after determining if we can support the new state, 1003 * but before we populate the programming info 1004 */ 1005 enum dc_status dc_validate_global_state( 1006 struct dc *dc, 1007 struct dc_state *new_ctx, 1008 bool fast_validate); 1009 1010 1011 void dc_resource_state_construct( 1012 const struct dc *dc, 1013 struct dc_state *dst_ctx); 1014 1015 #if defined(CONFIG_DRM_AMD_DC_DCN) 1016 bool dc_acquire_release_mpc_3dlut( 1017 struct dc *dc, bool acquire, 1018 struct dc_stream_state *stream, 1019 struct dc_3dlut **lut, 1020 struct dc_transfer_func **shaper); 1021 #endif 1022 1023 void dc_resource_state_copy_construct( 1024 const struct dc_state *src_ctx, 1025 struct dc_state *dst_ctx); 1026 1027 void dc_resource_state_copy_construct_current( 1028 const struct dc *dc, 1029 struct dc_state *dst_ctx); 1030 1031 void dc_resource_state_destruct(struct dc_state *context); 1032 1033 bool dc_resource_is_dsc_encoding_supported(const struct dc *dc); 1034 1035 /* 1036 * TODO update to make it about validation sets 1037 * Set up streams and links associated to drive sinks 1038 * The streams parameter is an absolute set of all active streams. 1039 * 1040 * After this call: 1041 * Phy, Encoder, Timing Generator are programmed and enabled. 1042 * New streams are enabled with blank stream; no memory read. 1043 */ 1044 bool dc_commit_state(struct dc *dc, struct dc_state *context); 1045 1046 void dc_power_down_on_boot(struct dc *dc); 1047 1048 struct dc_state *dc_create_state(struct dc *dc); 1049 struct dc_state *dc_copy_state(struct dc_state *src_ctx); 1050 void dc_retain_state(struct dc_state *context); 1051 void dc_release_state(struct dc_state *context); 1052 1053 /******************************************************************************* 1054 * Link Interfaces 1055 ******************************************************************************/ 1056 1057 struct dpcd_caps { 1058 union dpcd_rev dpcd_rev; 1059 union max_lane_count max_ln_count; 1060 union max_down_spread max_down_spread; 1061 union dprx_feature dprx_feature; 1062 1063 /* valid only for eDP v1.4 or higher*/ 1064 uint8_t edp_supported_link_rates_count; 1065 enum dc_link_rate edp_supported_link_rates[8]; 1066 1067 /* dongle type (DP converter, CV smart dongle) */ 1068 enum display_dongle_type dongle_type; 1069 /* branch device or sink device */ 1070 bool is_branch_dev; 1071 /* Dongle's downstream count. */ 1072 union sink_count sink_count; 1073 /* If dongle_type == DISPLAY_DONGLE_DP_HDMI_CONVERTER, 1074 indicates 'Frame Sequential-to-lllFrame Pack' conversion capability.*/ 1075 struct dc_dongle_caps dongle_caps; 1076 1077 uint32_t sink_dev_id; 1078 int8_t sink_dev_id_str[6]; 1079 int8_t sink_hw_revision; 1080 int8_t sink_fw_revision[2]; 1081 1082 uint32_t branch_dev_id; 1083 int8_t branch_dev_name[6]; 1084 int8_t branch_hw_revision; 1085 int8_t branch_fw_revision[2]; 1086 1087 bool allow_invalid_MSA_timing_param; 1088 bool panel_mode_edp; 1089 bool dpcd_display_control_capable; 1090 bool ext_receiver_cap_field_present; 1091 union dpcd_fec_capability fec_cap; 1092 struct dpcd_dsc_capabilities dsc_caps; 1093 struct dc_lttpr_caps lttpr_caps; 1094 struct psr_caps psr_caps; 1095 1096 }; 1097 1098 union dpcd_sink_ext_caps { 1099 struct { 1100 /* 0 - Sink supports backlight adjust via PWM during SDR/HDR mode 1101 * 1 - Sink supports backlight adjust via AUX during SDR/HDR mode. 1102 */ 1103 uint8_t sdr_aux_backlight_control : 1; 1104 uint8_t hdr_aux_backlight_control : 1; 1105 uint8_t reserved_1 : 2; 1106 uint8_t oled : 1; 1107 uint8_t reserved : 3; 1108 } bits; 1109 uint8_t raw; 1110 }; 1111 1112 #if defined(CONFIG_DRM_AMD_DC_HDCP) 1113 union hdcp_rx_caps { 1114 struct { 1115 uint8_t version; 1116 uint8_t reserved; 1117 struct { 1118 uint8_t repeater : 1; 1119 uint8_t hdcp_capable : 1; 1120 uint8_t reserved : 6; 1121 } byte0; 1122 } fields; 1123 uint8_t raw[3]; 1124 }; 1125 1126 union hdcp_bcaps { 1127 struct { 1128 uint8_t HDCP_CAPABLE:1; 1129 uint8_t REPEATER:1; 1130 uint8_t RESERVED:6; 1131 } bits; 1132 uint8_t raw; 1133 }; 1134 1135 struct hdcp_caps { 1136 union hdcp_rx_caps rx_caps; 1137 union hdcp_bcaps bcaps; 1138 }; 1139 #endif 1140 1141 #include "dc_link.h" 1142 1143 #if defined(CONFIG_DRM_AMD_DC_DCN) 1144 uint32_t dc_get_opp_for_plane(struct dc *dc, struct dc_plane_state *plane); 1145 1146 #endif 1147 /******************************************************************************* 1148 * Sink Interfaces - A sink corresponds to a display output device 1149 ******************************************************************************/ 1150 1151 struct dc_container_id { 1152 // 128bit GUID in binary form 1153 unsigned char guid[16]; 1154 // 8 byte port ID -> ELD.PortID 1155 unsigned int portId[2]; 1156 // 128bit GUID in binary formufacturer name -> ELD.ManufacturerName 1157 unsigned short manufacturerName; 1158 // 2 byte product code -> ELD.ProductCode 1159 unsigned short productCode; 1160 }; 1161 1162 1163 struct dc_sink_dsc_caps { 1164 // 'true' if these are virtual DPCD's DSC caps (immediately upstream of sink in MST topology), 1165 // 'false' if they are sink's DSC caps 1166 bool is_virtual_dpcd_dsc; 1167 struct dsc_dec_dpcd_caps dsc_dec_caps; 1168 }; 1169 1170 struct dc_sink_fec_caps { 1171 bool is_rx_fec_supported; 1172 bool is_topology_fec_supported; 1173 }; 1174 1175 /* 1176 * The sink structure contains EDID and other display device properties 1177 */ 1178 struct dc_sink { 1179 enum signal_type sink_signal; 1180 struct dc_edid dc_edid; /* raw edid */ 1181 struct dc_edid_caps edid_caps; /* parse display caps */ 1182 struct dc_container_id *dc_container_id; 1183 uint32_t dongle_max_pix_clk; 1184 void *priv; 1185 struct stereo_3d_features features_3d[TIMING_3D_FORMAT_MAX]; 1186 bool converter_disable_audio; 1187 1188 struct dc_sink_dsc_caps dsc_caps; 1189 struct dc_sink_fec_caps fec_caps; 1190 1191 bool is_vsc_sdp_colorimetry_supported; 1192 1193 /* private to DC core */ 1194 struct dc_link *link; 1195 struct dc_context *ctx; 1196 1197 uint32_t sink_id; 1198 1199 /* private to dc_sink.c */ 1200 // refcount must be the last member in dc_sink, since we want the 1201 // sink structure to be logically cloneable up to (but not including) 1202 // refcount 1203 struct kref refcount; 1204 }; 1205 1206 void dc_sink_retain(struct dc_sink *sink); 1207 void dc_sink_release(struct dc_sink *sink); 1208 1209 struct dc_sink_init_data { 1210 enum signal_type sink_signal; 1211 struct dc_link *link; 1212 uint32_t dongle_max_pix_clk; 1213 bool converter_disable_audio; 1214 }; 1215 1216 struct dc_sink *dc_sink_create(const struct dc_sink_init_data *init_params); 1217 1218 /* Newer interfaces */ 1219 struct dc_cursor { 1220 struct dc_plane_address address; 1221 struct dc_cursor_attributes attributes; 1222 }; 1223 1224 1225 /******************************************************************************* 1226 * Interrupt interfaces 1227 ******************************************************************************/ 1228 enum dc_irq_source dc_interrupt_to_irq_source( 1229 struct dc *dc, 1230 uint32_t src_id, 1231 uint32_t ext_id); 1232 bool dc_interrupt_set(struct dc *dc, enum dc_irq_source src, bool enable); 1233 void dc_interrupt_ack(struct dc *dc, enum dc_irq_source src); 1234 enum dc_irq_source dc_get_hpd_irq_source_at_index( 1235 struct dc *dc, uint32_t link_index); 1236 1237 /******************************************************************************* 1238 * Power Interfaces 1239 ******************************************************************************/ 1240 1241 void dc_set_power_state( 1242 struct dc *dc, 1243 enum dc_acpi_cm_power_state power_state); 1244 void dc_resume(struct dc *dc); 1245 1246 void dc_power_down_on_boot(struct dc *dc); 1247 1248 #if defined(CONFIG_DRM_AMD_DC_HDCP) 1249 /* 1250 * HDCP Interfaces 1251 */ 1252 enum hdcp_message_status dc_process_hdcp_msg( 1253 enum signal_type signal, 1254 struct dc_link *link, 1255 struct hdcp_protection_message *message_info); 1256 #endif 1257 bool dc_is_dmcu_initialized(struct dc *dc); 1258 1259 enum dc_status dc_set_clock(struct dc *dc, enum dc_clock_type clock_type, uint32_t clk_khz, uint32_t stepping); 1260 void dc_get_clock(struct dc *dc, enum dc_clock_type clock_type, struct dc_clock_config *clock_cfg); 1261 #if defined(CONFIG_DRM_AMD_DC_DCN) 1262 1263 bool dc_is_plane_eligible_for_idle_optimizations(struct dc *dc, 1264 struct dc_plane_state *plane); 1265 1266 void dc_allow_idle_optimizations(struct dc *dc, bool allow); 1267 1268 /* 1269 * blank all streams, and set min and max memory clock to 1270 * lowest and highest DPM level, respectively 1271 */ 1272 void dc_unlock_memory_clock_frequency(struct dc *dc); 1273 1274 /* 1275 * set min memory clock to the min required for current mode, 1276 * max to maxDPM, and unblank streams 1277 */ 1278 void dc_lock_memory_clock_frequency(struct dc *dc); 1279 1280 /* cleanup on driver unload */ 1281 void dc_hardware_release(struct dc *dc); 1282 1283 #endif 1284 1285 bool dc_set_psr_allow_active(struct dc *dc, bool enable); 1286 1287 /******************************************************************************* 1288 * DSC Interfaces 1289 ******************************************************************************/ 1290 #include "dc_dsc.h" 1291 #endif /* DC_INTERFACE_H_ */ 1292