1 /* 2 * Copyright 2012-14 Advanced Micro Devices, Inc. 3 * 4 * Permission is hereby granted, free of charge, to any person obtaining a 5 * copy of this software and associated documentation files (the "Software"), 6 * to deal in the Software without restriction, including without limitation 7 * the rights to use, copy, modify, merge, publish, distribute, sublicense, 8 * and/or sell copies of the Software, and to permit persons to whom the 9 * Software is furnished to do so, subject to the following conditions: 10 * 11 * The above copyright notice and this permission notice shall be included in 12 * all copies or substantial portions of the Software. 13 * 14 * THE SOFTWARE IS PROVIDED "AS IS", WITHOUT WARRANTY OF ANY KIND, EXPRESS OR 15 * IMPLIED, INCLUDING BUT NOT LIMITED TO THE WARRANTIES OF MERCHANTABILITY, 16 * FITNESS FOR A PARTICULAR PURPOSE AND NONINFRINGEMENT. IN NO EVENT SHALL 17 * THE COPYRIGHT HOLDER(S) OR AUTHOR(S) BE LIABLE FOR ANY CLAIM, DAMAGES OR 18 * OTHER LIABILITY, WHETHER IN AN ACTION OF CONTRACT, TORT OR OTHERWISE, 19 * ARISING FROM, OUT OF OR IN CONNECTION WITH THE SOFTWARE OR THE USE OR 20 * OTHER DEALINGS IN THE SOFTWARE. 21 * 22 * Authors: AMD 23 * 24 */ 25 26 #ifndef DC_INTERFACE_H_ 27 #define DC_INTERFACE_H_ 28 29 #include "dc_types.h" 30 #include "grph_object_defs.h" 31 #include "logger_types.h" 32 #include "gpio_types.h" 33 #include "link_service_types.h" 34 #include "grph_object_ctrl_defs.h" 35 #include <inc/hw/opp.h> 36 37 #include "inc/hw_sequencer.h" 38 #include "inc/compressor.h" 39 #include "dml/display_mode_lib.h" 40 41 #define DC_VER "3.1.28" 42 43 #define MAX_SURFACES 3 44 #define MAX_STREAMS 6 45 #define MAX_SINKS_PER_LINK 4 46 47 48 /******************************************************************************* 49 * Display Core Interfaces 50 ******************************************************************************/ 51 struct dc_caps { 52 uint32_t max_streams; 53 uint32_t max_links; 54 uint32_t max_audios; 55 uint32_t max_slave_planes; 56 uint32_t max_planes; 57 uint32_t max_downscale_ratio; 58 uint32_t i2c_speed_in_khz; 59 unsigned int max_cursor_size; 60 unsigned int max_video_width; 61 int linear_pitch_alignment; 62 bool dcc_const_color; 63 bool dynamic_audio; 64 bool is_apu; 65 bool dual_link_dvi; 66 }; 67 68 struct dc_dcc_surface_param { 69 struct dc_size surface_size; 70 enum surface_pixel_format format; 71 enum swizzle_mode_values swizzle_mode; 72 enum dc_scan_direction scan; 73 }; 74 75 struct dc_dcc_setting { 76 unsigned int max_compressed_blk_size; 77 unsigned int max_uncompressed_blk_size; 78 bool independent_64b_blks; 79 }; 80 81 struct dc_surface_dcc_cap { 82 union { 83 struct { 84 struct dc_dcc_setting rgb; 85 } grph; 86 87 struct { 88 struct dc_dcc_setting luma; 89 struct dc_dcc_setting chroma; 90 } video; 91 }; 92 93 bool capable; 94 bool const_color_support; 95 }; 96 97 struct dc_static_screen_events { 98 bool cursor_update; 99 bool surface_update; 100 bool overlay_update; 101 }; 102 103 104 /* Surface update type is used by dc_update_surfaces_and_stream 105 * The update type is determined at the very beginning of the function based 106 * on parameters passed in and decides how much programming (or updating) is 107 * going to be done during the call. 108 * 109 * UPDATE_TYPE_FAST is used for really fast updates that do not require much 110 * logical calculations or hardware register programming. This update MUST be 111 * ISR safe on windows. Currently fast update will only be used to flip surface 112 * address. 113 * 114 * UPDATE_TYPE_MED is used for slower updates which require significant hw 115 * re-programming however do not affect bandwidth consumption or clock 116 * requirements. At present, this is the level at which front end updates 117 * that do not require us to run bw_calcs happen. These are in/out transfer func 118 * updates, viewport offset changes, recout size changes and pixel depth changes. 119 * This update can be done at ISR, but we want to minimize how often this happens. 120 * 121 * UPDATE_TYPE_FULL is slow. Really slow. This requires us to recalculate our 122 * bandwidth and clocks, possibly rearrange some pipes and reprogram anything front 123 * end related. Any time viewport dimensions, recout dimensions, scaling ratios or 124 * gamma need to be adjusted or pipe needs to be turned on (or disconnected) we do 125 * a full update. This cannot be done at ISR level and should be a rare event. 126 * Unless someone is stress testing mpo enter/exit, playing with colour or adjusting 127 * underscan we don't expect to see this call at all. 128 */ 129 130 enum surface_update_type { 131 UPDATE_TYPE_FAST, /* super fast, safe to execute in isr */ 132 UPDATE_TYPE_MED, /* ISR safe, most of programming needed, no bw/clk change*/ 133 UPDATE_TYPE_FULL, /* may need to shuffle resources */ 134 }; 135 136 /* Forward declaration*/ 137 struct dc; 138 struct dc_plane_state; 139 struct dc_state; 140 141 142 struct dc_cap_funcs { 143 bool (*get_dcc_compression_cap)(const struct dc *dc, 144 const struct dc_dcc_surface_param *input, 145 struct dc_surface_dcc_cap *output); 146 }; 147 148 struct link_training_settings; 149 150 151 /* Structure to hold configuration flags set by dm at dc creation. */ 152 struct dc_config { 153 bool gpu_vm_support; 154 bool disable_disp_pll_sharing; 155 }; 156 157 enum dcc_option { 158 DCC_ENABLE = 0, 159 DCC_DISABLE = 1, 160 DCC_HALF_REQ_DISALBE = 2, 161 }; 162 163 enum pipe_split_policy { 164 MPC_SPLIT_DYNAMIC = 0, 165 MPC_SPLIT_AVOID = 1, 166 MPC_SPLIT_AVOID_MULT_DISP = 2, 167 }; 168 169 enum wm_report_mode { 170 WM_REPORT_DEFAULT = 0, 171 WM_REPORT_OVERRIDE = 1, 172 }; 173 174 struct dc_debug { 175 bool surface_visual_confirm; 176 bool sanity_checks; 177 bool max_disp_clk; 178 bool surface_trace; 179 bool timing_trace; 180 bool clock_trace; 181 bool validation_trace; 182 183 /* stutter efficiency related */ 184 bool disable_stutter; 185 bool use_max_lb; 186 enum dcc_option disable_dcc; 187 enum pipe_split_policy pipe_split_policy; 188 bool force_single_disp_pipe_split; 189 bool voltage_align_fclk; 190 191 bool disable_dfs_bypass; 192 bool disable_dpp_power_gate; 193 bool disable_hubp_power_gate; 194 bool disable_pplib_wm_range; 195 enum wm_report_mode pplib_wm_report_mode; 196 unsigned int min_disp_clk_khz; 197 int sr_exit_time_dpm0_ns; 198 int sr_enter_plus_exit_time_dpm0_ns; 199 int sr_exit_time_ns; 200 int sr_enter_plus_exit_time_ns; 201 int urgent_latency_ns; 202 int percent_of_ideal_drambw; 203 int dram_clock_change_latency_ns; 204 int always_scale; 205 bool disable_pplib_clock_request; 206 bool disable_clock_gate; 207 bool disable_dmcu; 208 bool disable_psr; 209 bool force_abm_enable; 210 bool disable_hbup_pg; 211 bool disable_dpp_pg; 212 bool disable_stereo_support; 213 bool vsr_support; 214 bool performance_trace; 215 }; 216 struct dc_state; 217 struct resource_pool; 218 struct dce_hwseq; 219 struct dc { 220 struct dc_caps caps; 221 struct dc_cap_funcs cap_funcs; 222 struct dc_config config; 223 struct dc_debug debug; 224 225 struct dc_context *ctx; 226 227 uint8_t link_count; 228 struct dc_link *links[MAX_PIPES * 2]; 229 230 struct dc_state *current_state; 231 struct resource_pool *res_pool; 232 233 /* Display Engine Clock levels */ 234 struct dm_pp_clock_levels sclk_lvls; 235 236 /* Inputs into BW and WM calculations. */ 237 struct bw_calcs_dceip *bw_dceip; 238 struct bw_calcs_vbios *bw_vbios; 239 #ifdef CONFIG_DRM_AMD_DC_DCN1_0 240 struct dcn_soc_bounding_box *dcn_soc; 241 struct dcn_ip_params *dcn_ip; 242 struct display_mode_lib dml; 243 #endif 244 245 /* HW functions */ 246 struct hw_sequencer_funcs hwss; 247 struct dce_hwseq *hwseq; 248 249 /* temp store of dm_pp_display_configuration 250 * to compare to see if display config changed 251 */ 252 struct dm_pp_display_configuration prev_display_config; 253 254 bool optimized_required; 255 256 /* FBC compressor */ 257 #if defined(CONFIG_DRM_AMD_DC_FBC) 258 struct compressor *fbc_compressor; 259 #endif 260 }; 261 262 enum frame_buffer_mode { 263 FRAME_BUFFER_MODE_LOCAL_ONLY = 0, 264 FRAME_BUFFER_MODE_ZFB_ONLY, 265 FRAME_BUFFER_MODE_MIXED_ZFB_AND_LOCAL, 266 } ; 267 268 struct dchub_init_data { 269 int64_t zfb_phys_addr_base; 270 int64_t zfb_mc_base_addr; 271 uint64_t zfb_size_in_byte; 272 enum frame_buffer_mode fb_mode; 273 bool dchub_initialzied; 274 bool dchub_info_valid; 275 }; 276 277 struct dc_init_data { 278 struct hw_asic_id asic_id; 279 void *driver; /* ctx */ 280 struct cgs_device *cgs_device; 281 282 int num_virtual_links; 283 /* 284 * If 'vbios_override' not NULL, it will be called instead 285 * of the real VBIOS. Intended use is Diagnostics on FPGA. 286 */ 287 struct dc_bios *vbios_override; 288 enum dce_environment dce_environment; 289 290 struct dc_config flags; 291 uint32_t log_mask; 292 }; 293 294 struct dc *dc_create(const struct dc_init_data *init_params); 295 296 void dc_destroy(struct dc **dc); 297 298 /******************************************************************************* 299 * Surface Interfaces 300 ******************************************************************************/ 301 302 enum { 303 TRANSFER_FUNC_POINTS = 1025 304 }; 305 306 // Moved here from color module for linux 307 enum color_transfer_func { 308 transfer_func_unknown, 309 transfer_func_srgb, 310 transfer_func_bt709, 311 transfer_func_pq2084, 312 transfer_func_pq2084_interim, 313 transfer_func_linear_0_1, 314 transfer_func_linear_0_125, 315 transfer_func_dolbyvision, 316 transfer_func_gamma_22, 317 transfer_func_gamma_26 318 }; 319 320 struct dc_hdr_static_metadata { 321 /* display chromaticities and white point in units of 0.00001 */ 322 unsigned int chromaticity_green_x; 323 unsigned int chromaticity_green_y; 324 unsigned int chromaticity_blue_x; 325 unsigned int chromaticity_blue_y; 326 unsigned int chromaticity_red_x; 327 unsigned int chromaticity_red_y; 328 unsigned int chromaticity_white_point_x; 329 unsigned int chromaticity_white_point_y; 330 331 uint32_t min_luminance; 332 uint32_t max_luminance; 333 uint32_t maximum_content_light_level; 334 uint32_t maximum_frame_average_light_level; 335 336 bool hdr_supported; 337 bool is_hdr; 338 }; 339 340 enum dc_transfer_func_type { 341 TF_TYPE_PREDEFINED, 342 TF_TYPE_DISTRIBUTED_POINTS, 343 TF_TYPE_BYPASS, 344 }; 345 346 struct dc_transfer_func_distributed_points { 347 struct fixed31_32 red[TRANSFER_FUNC_POINTS]; 348 struct fixed31_32 green[TRANSFER_FUNC_POINTS]; 349 struct fixed31_32 blue[TRANSFER_FUNC_POINTS]; 350 351 uint16_t end_exponent; 352 uint16_t x_point_at_y1_red; 353 uint16_t x_point_at_y1_green; 354 uint16_t x_point_at_y1_blue; 355 }; 356 357 enum dc_transfer_func_predefined { 358 TRANSFER_FUNCTION_SRGB, 359 TRANSFER_FUNCTION_BT709, 360 TRANSFER_FUNCTION_PQ, 361 TRANSFER_FUNCTION_LINEAR, 362 TRANSFER_FUNCTION_UNITY, 363 }; 364 365 struct dc_transfer_func { 366 struct kref refcount; 367 struct dc_transfer_func_distributed_points tf_pts; 368 enum dc_transfer_func_type type; 369 enum dc_transfer_func_predefined tf; 370 /* FP16 1.0 reference level in nits, default is 80 nits, only for PQ*/ 371 uint32_t sdr_ref_white_level; 372 struct dc_context *ctx; 373 }; 374 375 /* 376 * This structure is filled in by dc_surface_get_status and contains 377 * the last requested address and the currently active address so the called 378 * can determine if there are any outstanding flips 379 */ 380 struct dc_plane_status { 381 struct dc_plane_address requested_address; 382 struct dc_plane_address current_address; 383 bool is_flip_pending; 384 bool is_right_eye; 385 }; 386 387 union surface_update_flags { 388 389 struct { 390 /* Medium updates */ 391 uint32_t dcc_change:1; 392 uint32_t color_space_change:1; 393 uint32_t input_tf_change:1; 394 uint32_t horizontal_mirror_change:1; 395 uint32_t per_pixel_alpha_change:1; 396 uint32_t rotation_change:1; 397 uint32_t swizzle_change:1; 398 uint32_t scaling_change:1; 399 uint32_t position_change:1; 400 uint32_t in_transfer_func_change:1; 401 uint32_t input_csc_change:1; 402 uint32_t output_tf_change:1; 403 404 /* Full updates */ 405 uint32_t new_plane:1; 406 uint32_t bpp_change:1; 407 uint32_t gamma_change:1; 408 uint32_t bandwidth_change:1; 409 uint32_t clock_change:1; 410 uint32_t stereo_format_change:1; 411 uint32_t full_update:1; 412 } bits; 413 414 uint32_t raw; 415 }; 416 417 struct dc_plane_state { 418 struct dc_plane_address address; 419 struct scaling_taps scaling_quality; 420 struct rect src_rect; 421 struct rect dst_rect; 422 struct rect clip_rect; 423 424 union plane_size plane_size; 425 union dc_tiling_info tiling_info; 426 427 struct dc_plane_dcc_param dcc; 428 429 struct dc_gamma *gamma_correction; 430 struct dc_transfer_func *in_transfer_func; 431 struct dc_bias_and_scale *bias_and_scale; 432 struct csc_transform input_csc_color_matrix; 433 struct fixed31_32 coeff_reduction_factor; 434 uint32_t sdr_white_level; 435 436 // TODO: No longer used, remove 437 struct dc_hdr_static_metadata hdr_static_ctx; 438 439 enum dc_color_space color_space; 440 enum color_transfer_func input_tf; 441 442 enum surface_pixel_format format; 443 enum dc_rotation_angle rotation; 444 enum plane_stereo_format stereo_format; 445 446 bool is_tiling_rotated; 447 bool per_pixel_alpha; 448 bool visible; 449 bool flip_immediate; 450 bool horizontal_mirror; 451 452 union surface_update_flags update_flags; 453 /* private to DC core */ 454 struct dc_plane_status status; 455 struct dc_context *ctx; 456 457 /* private to dc_surface.c */ 458 enum dc_irq_source irq_source; 459 struct kref refcount; 460 }; 461 462 struct dc_plane_info { 463 union plane_size plane_size; 464 union dc_tiling_info tiling_info; 465 struct dc_plane_dcc_param dcc; 466 enum surface_pixel_format format; 467 enum dc_rotation_angle rotation; 468 enum plane_stereo_format stereo_format; 469 enum dc_color_space color_space; 470 enum color_transfer_func input_tf; 471 unsigned int sdr_white_level; 472 bool horizontal_mirror; 473 bool visible; 474 bool per_pixel_alpha; 475 bool input_csc_enabled; 476 }; 477 478 struct dc_scaling_info { 479 struct rect src_rect; 480 struct rect dst_rect; 481 struct rect clip_rect; 482 struct scaling_taps scaling_quality; 483 }; 484 485 struct dc_surface_update { 486 struct dc_plane_state *surface; 487 488 /* isr safe update parameters. null means no updates */ 489 struct dc_flip_addrs *flip_addr; 490 struct dc_plane_info *plane_info; 491 struct dc_scaling_info *scaling_info; 492 493 /* following updates require alloc/sleep/spin that is not isr safe, 494 * null means no updates 495 */ 496 /* gamma TO BE REMOVED */ 497 struct dc_gamma *gamma; 498 enum color_transfer_func color_input_tf; 499 enum color_transfer_func color_output_tf; 500 struct dc_transfer_func *in_transfer_func; 501 502 struct csc_transform *input_csc_color_matrix; 503 struct fixed31_32 *coeff_reduction_factor; 504 }; 505 506 /* 507 * Create a new surface with default parameters; 508 */ 509 struct dc_plane_state *dc_create_plane_state(struct dc *dc); 510 const struct dc_plane_status *dc_plane_get_status( 511 const struct dc_plane_state *plane_state); 512 513 void dc_plane_state_retain(struct dc_plane_state *plane_state); 514 void dc_plane_state_release(struct dc_plane_state *plane_state); 515 516 void dc_gamma_retain(struct dc_gamma *dc_gamma); 517 void dc_gamma_release(struct dc_gamma **dc_gamma); 518 struct dc_gamma *dc_create_gamma(void); 519 520 void dc_transfer_func_retain(struct dc_transfer_func *dc_tf); 521 void dc_transfer_func_release(struct dc_transfer_func *dc_tf); 522 struct dc_transfer_func *dc_create_transfer_func(void); 523 524 /* 525 * This structure holds a surface address. There could be multiple addresses 526 * in cases such as Stereo 3D, Planar YUV, etc. Other per-flip attributes such 527 * as frame durations and DCC format can also be set. 528 */ 529 struct dc_flip_addrs { 530 struct dc_plane_address address; 531 bool flip_immediate; 532 /* TODO: add flip duration for FreeSync */ 533 }; 534 535 bool dc_post_update_surfaces_to_stream( 536 struct dc *dc); 537 538 #include "dc_stream.h" 539 540 /* 541 * Structure to store surface/stream associations for validation 542 */ 543 struct dc_validation_set { 544 struct dc_stream_state *stream; 545 struct dc_plane_state *plane_states[MAX_SURFACES]; 546 uint8_t plane_count; 547 }; 548 549 enum dc_status dc_validate_plane(struct dc *dc, const struct dc_plane_state *plane_state); 550 551 enum dc_status dc_validate_global_state( 552 struct dc *dc, 553 struct dc_state *new_ctx); 554 555 556 void dc_resource_state_construct( 557 const struct dc *dc, 558 struct dc_state *dst_ctx); 559 560 void dc_resource_state_copy_construct( 561 const struct dc_state *src_ctx, 562 struct dc_state *dst_ctx); 563 564 void dc_resource_state_copy_construct_current( 565 const struct dc *dc, 566 struct dc_state *dst_ctx); 567 568 void dc_resource_state_destruct(struct dc_state *context); 569 570 /* 571 * TODO update to make it about validation sets 572 * Set up streams and links associated to drive sinks 573 * The streams parameter is an absolute set of all active streams. 574 * 575 * After this call: 576 * Phy, Encoder, Timing Generator are programmed and enabled. 577 * New streams are enabled with blank stream; no memory read. 578 */ 579 bool dc_commit_state(struct dc *dc, struct dc_state *context); 580 581 582 struct dc_state *dc_create_state(void); 583 void dc_retain_state(struct dc_state *context); 584 void dc_release_state(struct dc_state *context); 585 586 /******************************************************************************* 587 * Link Interfaces 588 ******************************************************************************/ 589 590 struct dpcd_caps { 591 union dpcd_rev dpcd_rev; 592 union max_lane_count max_ln_count; 593 union max_down_spread max_down_spread; 594 595 /* dongle type (DP converter, CV smart dongle) */ 596 enum display_dongle_type dongle_type; 597 /* Dongle's downstream count. */ 598 union sink_count sink_count; 599 /* If dongle_type == DISPLAY_DONGLE_DP_HDMI_CONVERTER, 600 indicates 'Frame Sequential-to-lllFrame Pack' conversion capability.*/ 601 struct dc_dongle_caps dongle_caps; 602 603 uint32_t sink_dev_id; 604 uint32_t branch_dev_id; 605 int8_t branch_dev_name[6]; 606 int8_t branch_hw_revision; 607 608 bool allow_invalid_MSA_timing_param; 609 bool panel_mode_edp; 610 bool dpcd_display_control_capable; 611 }; 612 613 #include "dc_link.h" 614 615 /******************************************************************************* 616 * Sink Interfaces - A sink corresponds to a display output device 617 ******************************************************************************/ 618 619 struct dc_container_id { 620 // 128bit GUID in binary form 621 unsigned char guid[16]; 622 // 8 byte port ID -> ELD.PortID 623 unsigned int portId[2]; 624 // 128bit GUID in binary formufacturer name -> ELD.ManufacturerName 625 unsigned short manufacturerName; 626 // 2 byte product code -> ELD.ProductCode 627 unsigned short productCode; 628 }; 629 630 631 632 /* 633 * The sink structure contains EDID and other display device properties 634 */ 635 struct dc_sink { 636 enum signal_type sink_signal; 637 struct dc_edid dc_edid; /* raw edid */ 638 struct dc_edid_caps edid_caps; /* parse display caps */ 639 struct dc_container_id *dc_container_id; 640 uint32_t dongle_max_pix_clk; 641 void *priv; 642 struct stereo_3d_features features_3d[TIMING_3D_FORMAT_MAX]; 643 bool converter_disable_audio; 644 645 /* private to DC core */ 646 struct dc_link *link; 647 struct dc_context *ctx; 648 649 /* private to dc_sink.c */ 650 struct kref refcount; 651 652 }; 653 654 void dc_sink_retain(struct dc_sink *sink); 655 void dc_sink_release(struct dc_sink *sink); 656 657 struct dc_sink_init_data { 658 enum signal_type sink_signal; 659 struct dc_link *link; 660 uint32_t dongle_max_pix_clk; 661 bool converter_disable_audio; 662 }; 663 664 struct dc_sink *dc_sink_create(const struct dc_sink_init_data *init_params); 665 666 /* Newer interfaces */ 667 struct dc_cursor { 668 struct dc_plane_address address; 669 struct dc_cursor_attributes attributes; 670 }; 671 672 /******************************************************************************* 673 * Interrupt interfaces 674 ******************************************************************************/ 675 enum dc_irq_source dc_interrupt_to_irq_source( 676 struct dc *dc, 677 uint32_t src_id, 678 uint32_t ext_id); 679 void dc_interrupt_set(struct dc *dc, enum dc_irq_source src, bool enable); 680 void dc_interrupt_ack(struct dc *dc, enum dc_irq_source src); 681 enum dc_irq_source dc_get_hpd_irq_source_at_index( 682 struct dc *dc, uint32_t link_index); 683 684 /******************************************************************************* 685 * Power Interfaces 686 ******************************************************************************/ 687 688 void dc_set_power_state( 689 struct dc *dc, 690 enum dc_acpi_cm_power_state power_state); 691 void dc_resume(struct dc *dc); 692 693 #endif /* DC_INTERFACE_H_ */ 694