1 /* 2 * Copyright 2012-14 Advanced Micro Devices, Inc. 3 * 4 * Permission is hereby granted, free of charge, to any person obtaining a 5 * copy of this software and associated documentation files (the "Software"), 6 * to deal in the Software without restriction, including without limitation 7 * the rights to use, copy, modify, merge, publish, distribute, sublicense, 8 * and/or sell copies of the Software, and to permit persons to whom the 9 * Software is furnished to do so, subject to the following conditions: 10 * 11 * The above copyright notice and this permission notice shall be included in 12 * all copies or substantial portions of the Software. 13 * 14 * THE SOFTWARE IS PROVIDED "AS IS", WITHOUT WARRANTY OF ANY KIND, EXPRESS OR 15 * IMPLIED, INCLUDING BUT NOT LIMITED TO THE WARRANTIES OF MERCHANTABILITY, 16 * FITNESS FOR A PARTICULAR PURPOSE AND NONINFRINGEMENT. IN NO EVENT SHALL 17 * THE COPYRIGHT HOLDER(S) OR AUTHOR(S) BE LIABLE FOR ANY CLAIM, DAMAGES OR 18 * OTHER LIABILITY, WHETHER IN AN ACTION OF CONTRACT, TORT OR OTHERWISE, 19 * ARISING FROM, OUT OF OR IN CONNECTION WITH THE SOFTWARE OR THE USE OR 20 * OTHER DEALINGS IN THE SOFTWARE. 21 * 22 * Authors: AMD 23 * 24 */ 25 26 #ifndef DC_INTERFACE_H_ 27 #define DC_INTERFACE_H_ 28 29 #include "dc_types.h" 30 #include "grph_object_defs.h" 31 #include "logger_types.h" 32 #include "gpio_types.h" 33 #include "link_service_types.h" 34 #include "grph_object_ctrl_defs.h" 35 #include <inc/hw/opp.h> 36 37 #include "inc/hw_sequencer.h" 38 #include "inc/compressor.h" 39 #include "inc/hw/dmcu.h" 40 #include "dml/display_mode_lib.h" 41 42 #define DC_VER "3.2.27" 43 44 #define MAX_SURFACES 3 45 #define MAX_PLANES 6 46 #define MAX_STREAMS 6 47 #define MAX_SINKS_PER_LINK 4 48 49 /******************************************************************************* 50 * Display Core Interfaces 51 ******************************************************************************/ 52 struct dc_versions { 53 const char *dc_ver; 54 struct dmcu_version dmcu_version; 55 }; 56 57 enum dc_plane_type { 58 DC_PLANE_TYPE_INVALID, 59 DC_PLANE_TYPE_DCE_RGB, 60 DC_PLANE_TYPE_DCE_UNDERLAY, 61 DC_PLANE_TYPE_DCN_UNIVERSAL, 62 }; 63 64 struct dc_plane_cap { 65 enum dc_plane_type type; 66 uint32_t blends_with_above : 1; 67 uint32_t blends_with_below : 1; 68 uint32_t per_pixel_alpha : 1; 69 struct { 70 uint32_t argb8888 : 1; 71 uint32_t nv12 : 1; 72 uint32_t fp16 : 1; 73 } pixel_format_support; 74 // max upscaling factor x1000 75 // upscaling factors are always >= 1 76 // for example, 1080p -> 8K is 4.0, or 4000 raw value 77 struct { 78 uint32_t argb8888; 79 uint32_t nv12; 80 uint32_t fp16; 81 } max_upscale_factor; 82 // max downscale factor x1000 83 // downscale factors are always <= 1 84 // for example, 8K -> 1080p is 0.25, or 250 raw value 85 struct { 86 uint32_t argb8888; 87 uint32_t nv12; 88 uint32_t fp16; 89 } max_downscale_factor; 90 }; 91 92 struct dc_caps { 93 uint32_t max_streams; 94 uint32_t max_links; 95 uint32_t max_audios; 96 uint32_t max_slave_planes; 97 uint32_t max_planes; 98 uint32_t max_downscale_ratio; 99 uint32_t i2c_speed_in_khz; 100 uint32_t dmdata_alloc_size; 101 unsigned int max_cursor_size; 102 unsigned int max_video_width; 103 int linear_pitch_alignment; 104 bool dcc_const_color; 105 bool dynamic_audio; 106 bool is_apu; 107 bool dual_link_dvi; 108 bool post_blend_color_processing; 109 bool force_dp_tps4_for_cp2520; 110 bool disable_dp_clk_share; 111 bool psp_setup_panel_mode; 112 struct dc_plane_cap planes[MAX_PLANES]; 113 }; 114 115 struct dc_dcc_surface_param { 116 struct dc_size surface_size; 117 enum surface_pixel_format format; 118 enum swizzle_mode_values swizzle_mode; 119 enum dc_scan_direction scan; 120 }; 121 122 struct dc_dcc_setting { 123 unsigned int max_compressed_blk_size; 124 unsigned int max_uncompressed_blk_size; 125 bool independent_64b_blks; 126 }; 127 128 struct dc_surface_dcc_cap { 129 union { 130 struct { 131 struct dc_dcc_setting rgb; 132 } grph; 133 134 struct { 135 struct dc_dcc_setting luma; 136 struct dc_dcc_setting chroma; 137 } video; 138 }; 139 140 bool capable; 141 bool const_color_support; 142 }; 143 144 struct dc_static_screen_events { 145 bool force_trigger; 146 bool cursor_update; 147 bool surface_update; 148 bool overlay_update; 149 }; 150 151 152 /* Surface update type is used by dc_update_surfaces_and_stream 153 * The update type is determined at the very beginning of the function based 154 * on parameters passed in and decides how much programming (or updating) is 155 * going to be done during the call. 156 * 157 * UPDATE_TYPE_FAST is used for really fast updates that do not require much 158 * logical calculations or hardware register programming. This update MUST be 159 * ISR safe on windows. Currently fast update will only be used to flip surface 160 * address. 161 * 162 * UPDATE_TYPE_MED is used for slower updates which require significant hw 163 * re-programming however do not affect bandwidth consumption or clock 164 * requirements. At present, this is the level at which front end updates 165 * that do not require us to run bw_calcs happen. These are in/out transfer func 166 * updates, viewport offset changes, recout size changes and pixel depth changes. 167 * This update can be done at ISR, but we want to minimize how often this happens. 168 * 169 * UPDATE_TYPE_FULL is slow. Really slow. This requires us to recalculate our 170 * bandwidth and clocks, possibly rearrange some pipes and reprogram anything front 171 * end related. Any time viewport dimensions, recout dimensions, scaling ratios or 172 * gamma need to be adjusted or pipe needs to be turned on (or disconnected) we do 173 * a full update. This cannot be done at ISR level and should be a rare event. 174 * Unless someone is stress testing mpo enter/exit, playing with colour or adjusting 175 * underscan we don't expect to see this call at all. 176 */ 177 178 enum surface_update_type { 179 UPDATE_TYPE_FAST, /* super fast, safe to execute in isr */ 180 UPDATE_TYPE_MED, /* ISR safe, most of programming needed, no bw/clk change*/ 181 UPDATE_TYPE_FULL, /* may need to shuffle resources */ 182 }; 183 184 /* Forward declaration*/ 185 struct dc; 186 struct dc_plane_state; 187 struct dc_state; 188 189 190 struct dc_cap_funcs { 191 bool (*get_dcc_compression_cap)(const struct dc *dc, 192 const struct dc_dcc_surface_param *input, 193 struct dc_surface_dcc_cap *output); 194 }; 195 196 struct link_training_settings; 197 198 199 /* Structure to hold configuration flags set by dm at dc creation. */ 200 struct dc_config { 201 bool gpu_vm_support; 202 bool disable_disp_pll_sharing; 203 bool fbc_support; 204 bool optimize_edp_link_rate; 205 bool disable_fractional_pwm; 206 bool allow_seamless_boot_optimization; 207 bool power_down_display_on_boot; 208 }; 209 210 enum visual_confirm { 211 VISUAL_CONFIRM_DISABLE = 0, 212 VISUAL_CONFIRM_SURFACE = 1, 213 VISUAL_CONFIRM_HDR = 2, 214 }; 215 216 enum dcc_option { 217 DCC_ENABLE = 0, 218 DCC_DISABLE = 1, 219 DCC_HALF_REQ_DISALBE = 2, 220 }; 221 222 enum pipe_split_policy { 223 MPC_SPLIT_DYNAMIC = 0, 224 MPC_SPLIT_AVOID = 1, 225 MPC_SPLIT_AVOID_MULT_DISP = 2, 226 }; 227 228 enum wm_report_mode { 229 WM_REPORT_DEFAULT = 0, 230 WM_REPORT_OVERRIDE = 1, 231 }; 232 233 /* 234 * For any clocks that may differ per pipe 235 * only the max is stored in this structure 236 */ 237 struct dc_clocks { 238 int dispclk_khz; 239 int max_supported_dppclk_khz; 240 int dppclk_khz; 241 int dcfclk_khz; 242 int socclk_khz; 243 int dcfclk_deep_sleep_khz; 244 int fclk_khz; 245 int phyclk_khz; 246 int dramclk_khz; 247 bool p_state_change_support; 248 }; 249 250 struct dc_bw_validation_profile { 251 bool enable; 252 253 unsigned long long total_ticks; 254 unsigned long long voltage_level_ticks; 255 unsigned long long watermark_ticks; 256 unsigned long long rq_dlg_ticks; 257 258 unsigned long long total_count; 259 unsigned long long skip_fast_count; 260 unsigned long long skip_pass_count; 261 unsigned long long skip_fail_count; 262 }; 263 264 #define BW_VAL_TRACE_SETUP() \ 265 unsigned long long end_tick = 0; \ 266 unsigned long long voltage_level_tick = 0; \ 267 unsigned long long watermark_tick = 0; \ 268 unsigned long long start_tick = dc->debug.bw_val_profile.enable ? \ 269 dm_get_timestamp(dc->ctx) : 0 270 271 #define BW_VAL_TRACE_COUNT() \ 272 if (dc->debug.bw_val_profile.enable) \ 273 dc->debug.bw_val_profile.total_count++ 274 275 #define BW_VAL_TRACE_SKIP(status) \ 276 if (dc->debug.bw_val_profile.enable) { \ 277 if (!voltage_level_tick) \ 278 voltage_level_tick = dm_get_timestamp(dc->ctx); \ 279 dc->debug.bw_val_profile.skip_ ## status ## _count++; \ 280 } 281 282 #define BW_VAL_TRACE_END_VOLTAGE_LEVEL() \ 283 if (dc->debug.bw_val_profile.enable) \ 284 voltage_level_tick = dm_get_timestamp(dc->ctx) 285 286 #define BW_VAL_TRACE_END_WATERMARKS() \ 287 if (dc->debug.bw_val_profile.enable) \ 288 watermark_tick = dm_get_timestamp(dc->ctx) 289 290 #define BW_VAL_TRACE_FINISH() \ 291 if (dc->debug.bw_val_profile.enable) { \ 292 end_tick = dm_get_timestamp(dc->ctx); \ 293 dc->debug.bw_val_profile.total_ticks += end_tick - start_tick; \ 294 dc->debug.bw_val_profile.voltage_level_ticks += voltage_level_tick - start_tick; \ 295 if (watermark_tick) { \ 296 dc->debug.bw_val_profile.watermark_ticks += watermark_tick - voltage_level_tick; \ 297 dc->debug.bw_val_profile.rq_dlg_ticks += end_tick - watermark_tick; \ 298 } \ 299 } 300 301 struct dc_debug_options { 302 enum visual_confirm visual_confirm; 303 bool sanity_checks; 304 bool max_disp_clk; 305 bool surface_trace; 306 bool timing_trace; 307 bool clock_trace; 308 bool validation_trace; 309 bool bandwidth_calcs_trace; 310 int max_downscale_src_width; 311 312 /* stutter efficiency related */ 313 bool disable_stutter; 314 bool use_max_lb; 315 enum dcc_option disable_dcc; 316 enum pipe_split_policy pipe_split_policy; 317 bool force_single_disp_pipe_split; 318 bool voltage_align_fclk; 319 320 bool disable_dfs_bypass; 321 bool disable_dpp_power_gate; 322 bool disable_hubp_power_gate; 323 bool disable_pplib_wm_range; 324 enum wm_report_mode pplib_wm_report_mode; 325 unsigned int min_disp_clk_khz; 326 int sr_exit_time_dpm0_ns; 327 int sr_enter_plus_exit_time_dpm0_ns; 328 int sr_exit_time_ns; 329 int sr_enter_plus_exit_time_ns; 330 int urgent_latency_ns; 331 int percent_of_ideal_drambw; 332 int dram_clock_change_latency_ns; 333 bool optimized_watermark; 334 int always_scale; 335 bool disable_pplib_clock_request; 336 bool disable_clock_gate; 337 bool disable_dmcu; 338 bool disable_psr; 339 bool force_abm_enable; 340 bool disable_stereo_support; 341 bool vsr_support; 342 bool performance_trace; 343 bool az_endpoint_mute_only; 344 bool always_use_regamma; 345 bool p010_mpo_support; 346 bool recovery_enabled; 347 bool avoid_vbios_exec_table; 348 bool scl_reset_length10; 349 bool hdmi20_disable; 350 bool skip_detection_link_training; 351 unsigned int force_odm_combine; //bit vector based on otg inst 352 unsigned int force_fclk_khz; 353 bool disable_tri_buf; 354 struct dc_bw_validation_profile bw_val_profile; 355 }; 356 357 struct dc_debug_data { 358 uint32_t ltFailCount; 359 uint32_t i2cErrorCount; 360 uint32_t auxErrorCount; 361 }; 362 363 struct dc_bounding_box_overrides { 364 int sr_exit_time_ns; 365 int sr_enter_plus_exit_time_ns; 366 int urgent_latency_ns; 367 int percent_of_ideal_drambw; 368 int dram_clock_change_latency_ns; 369 }; 370 371 struct dc_state; 372 struct resource_pool; 373 struct dce_hwseq; 374 struct dc { 375 struct dc_versions versions; 376 struct dc_caps caps; 377 struct dc_cap_funcs cap_funcs; 378 struct dc_config config; 379 struct dc_debug_options debug; 380 struct dc_bounding_box_overrides bb_overrides; 381 struct dc_context *ctx; 382 383 uint8_t link_count; 384 struct dc_link *links[MAX_PIPES * 2]; 385 386 struct dc_state *current_state; 387 struct resource_pool *res_pool; 388 389 /* Display Engine Clock levels */ 390 struct dm_pp_clock_levels sclk_lvls; 391 392 /* Inputs into BW and WM calculations. */ 393 struct bw_calcs_dceip *bw_dceip; 394 struct bw_calcs_vbios *bw_vbios; 395 #ifdef CONFIG_DRM_AMD_DC_DCN1_0 396 struct dcn_soc_bounding_box *dcn_soc; 397 struct dcn_ip_params *dcn_ip; 398 struct display_mode_lib dml; 399 #endif 400 401 /* HW functions */ 402 struct hw_sequencer_funcs hwss; 403 struct dce_hwseq *hwseq; 404 405 /* Require to optimize clocks and bandwidth for added/removed planes */ 406 bool optimized_required; 407 408 /* Require to maintain clocks and bandwidth for UEFI enabled HW */ 409 bool optimize_seamless_boot; 410 411 /* FBC compressor */ 412 struct compressor *fbc_compressor; 413 414 struct dc_debug_data debug_data; 415 416 const char *build_id; 417 }; 418 419 enum frame_buffer_mode { 420 FRAME_BUFFER_MODE_LOCAL_ONLY = 0, 421 FRAME_BUFFER_MODE_ZFB_ONLY, 422 FRAME_BUFFER_MODE_MIXED_ZFB_AND_LOCAL, 423 } ; 424 425 struct dchub_init_data { 426 int64_t zfb_phys_addr_base; 427 int64_t zfb_mc_base_addr; 428 uint64_t zfb_size_in_byte; 429 enum frame_buffer_mode fb_mode; 430 bool dchub_initialzied; 431 bool dchub_info_valid; 432 }; 433 434 struct dc_init_data { 435 struct hw_asic_id asic_id; 436 void *driver; /* ctx */ 437 struct cgs_device *cgs_device; 438 struct dc_bounding_box_overrides bb_overrides; 439 440 int num_virtual_links; 441 /* 442 * If 'vbios_override' not NULL, it will be called instead 443 * of the real VBIOS. Intended use is Diagnostics on FPGA. 444 */ 445 struct dc_bios *vbios_override; 446 enum dce_environment dce_environment; 447 448 struct dc_config flags; 449 uint32_t log_mask; 450 }; 451 452 struct dc_callback_init { 453 uint8_t reserved; 454 }; 455 456 struct dc *dc_create(const struct dc_init_data *init_params); 457 void dc_init_callbacks(struct dc *dc, 458 const struct dc_callback_init *init_params); 459 void dc_destroy(struct dc **dc); 460 461 /******************************************************************************* 462 * Surface Interfaces 463 ******************************************************************************/ 464 465 enum { 466 TRANSFER_FUNC_POINTS = 1025 467 }; 468 469 struct dc_hdr_static_metadata { 470 /* display chromaticities and white point in units of 0.00001 */ 471 unsigned int chromaticity_green_x; 472 unsigned int chromaticity_green_y; 473 unsigned int chromaticity_blue_x; 474 unsigned int chromaticity_blue_y; 475 unsigned int chromaticity_red_x; 476 unsigned int chromaticity_red_y; 477 unsigned int chromaticity_white_point_x; 478 unsigned int chromaticity_white_point_y; 479 480 uint32_t min_luminance; 481 uint32_t max_luminance; 482 uint32_t maximum_content_light_level; 483 uint32_t maximum_frame_average_light_level; 484 }; 485 486 enum dc_transfer_func_type { 487 TF_TYPE_PREDEFINED, 488 TF_TYPE_DISTRIBUTED_POINTS, 489 TF_TYPE_BYPASS, 490 TF_TYPE_HWPWL 491 }; 492 493 struct dc_transfer_func_distributed_points { 494 struct fixed31_32 red[TRANSFER_FUNC_POINTS]; 495 struct fixed31_32 green[TRANSFER_FUNC_POINTS]; 496 struct fixed31_32 blue[TRANSFER_FUNC_POINTS]; 497 498 uint16_t end_exponent; 499 uint16_t x_point_at_y1_red; 500 uint16_t x_point_at_y1_green; 501 uint16_t x_point_at_y1_blue; 502 }; 503 504 enum dc_transfer_func_predefined { 505 TRANSFER_FUNCTION_SRGB, 506 TRANSFER_FUNCTION_BT709, 507 TRANSFER_FUNCTION_PQ, 508 TRANSFER_FUNCTION_LINEAR, 509 TRANSFER_FUNCTION_UNITY, 510 TRANSFER_FUNCTION_HLG, 511 TRANSFER_FUNCTION_HLG12, 512 TRANSFER_FUNCTION_GAMMA22 513 }; 514 515 struct dc_transfer_func { 516 struct kref refcount; 517 enum dc_transfer_func_type type; 518 enum dc_transfer_func_predefined tf; 519 /* FP16 1.0 reference level in nits, default is 80 nits, only for PQ*/ 520 uint32_t sdr_ref_white_level; 521 struct dc_context *ctx; 522 union { 523 struct pwl_params pwl; 524 struct dc_transfer_func_distributed_points tf_pts; 525 }; 526 }; 527 528 /* 529 * This structure is filled in by dc_surface_get_status and contains 530 * the last requested address and the currently active address so the called 531 * can determine if there are any outstanding flips 532 */ 533 struct dc_plane_status { 534 struct dc_plane_address requested_address; 535 struct dc_plane_address current_address; 536 bool is_flip_pending; 537 bool is_right_eye; 538 }; 539 540 union surface_update_flags { 541 542 struct { 543 /* Medium updates */ 544 uint32_t dcc_change:1; 545 uint32_t color_space_change:1; 546 uint32_t horizontal_mirror_change:1; 547 uint32_t per_pixel_alpha_change:1; 548 uint32_t global_alpha_change:1; 549 uint32_t rotation_change:1; 550 uint32_t swizzle_change:1; 551 uint32_t scaling_change:1; 552 uint32_t position_change:1; 553 uint32_t in_transfer_func_change:1; 554 uint32_t input_csc_change:1; 555 uint32_t coeff_reduction_change:1; 556 uint32_t output_tf_change:1; 557 uint32_t pixel_format_change:1; 558 uint32_t plane_size_change:1; 559 560 /* Full updates */ 561 uint32_t new_plane:1; 562 uint32_t bpp_change:1; 563 uint32_t gamma_change:1; 564 uint32_t bandwidth_change:1; 565 uint32_t clock_change:1; 566 uint32_t stereo_format_change:1; 567 uint32_t full_update:1; 568 } bits; 569 570 uint32_t raw; 571 }; 572 573 struct dc_plane_state { 574 struct dc_plane_address address; 575 struct dc_plane_flip_time time; 576 struct scaling_taps scaling_quality; 577 struct rect src_rect; 578 struct rect dst_rect; 579 struct rect clip_rect; 580 581 union plane_size plane_size; 582 union dc_tiling_info tiling_info; 583 584 struct dc_plane_dcc_param dcc; 585 586 struct dc_gamma *gamma_correction; 587 struct dc_transfer_func *in_transfer_func; 588 struct dc_bias_and_scale *bias_and_scale; 589 struct dc_csc_transform input_csc_color_matrix; 590 struct fixed31_32 coeff_reduction_factor; 591 uint32_t sdr_white_level; 592 593 // TODO: No longer used, remove 594 struct dc_hdr_static_metadata hdr_static_ctx; 595 596 enum dc_color_space color_space; 597 598 enum surface_pixel_format format; 599 enum dc_rotation_angle rotation; 600 enum plane_stereo_format stereo_format; 601 602 bool is_tiling_rotated; 603 bool per_pixel_alpha; 604 bool global_alpha; 605 int global_alpha_value; 606 bool visible; 607 bool flip_immediate; 608 bool horizontal_mirror; 609 610 union surface_update_flags update_flags; 611 /* private to DC core */ 612 struct dc_plane_status status; 613 struct dc_context *ctx; 614 615 /* HACK: Workaround for forcing full reprogramming under some conditions */ 616 bool force_full_update; 617 618 /* private to dc_surface.c */ 619 enum dc_irq_source irq_source; 620 struct kref refcount; 621 }; 622 623 struct dc_plane_info { 624 union plane_size plane_size; 625 union dc_tiling_info tiling_info; 626 struct dc_plane_dcc_param dcc; 627 enum surface_pixel_format format; 628 enum dc_rotation_angle rotation; 629 enum plane_stereo_format stereo_format; 630 enum dc_color_space color_space; 631 unsigned int sdr_white_level; 632 bool horizontal_mirror; 633 bool visible; 634 bool per_pixel_alpha; 635 bool global_alpha; 636 int global_alpha_value; 637 bool input_csc_enabled; 638 }; 639 640 struct dc_scaling_info { 641 struct rect src_rect; 642 struct rect dst_rect; 643 struct rect clip_rect; 644 struct scaling_taps scaling_quality; 645 }; 646 647 struct dc_surface_update { 648 struct dc_plane_state *surface; 649 650 /* isr safe update parameters. null means no updates */ 651 const struct dc_flip_addrs *flip_addr; 652 const struct dc_plane_info *plane_info; 653 const struct dc_scaling_info *scaling_info; 654 655 /* following updates require alloc/sleep/spin that is not isr safe, 656 * null means no updates 657 */ 658 const struct dc_gamma *gamma; 659 const struct dc_transfer_func *in_transfer_func; 660 661 const struct dc_csc_transform *input_csc_color_matrix; 662 const struct fixed31_32 *coeff_reduction_factor; 663 }; 664 665 /* 666 * Create a new surface with default parameters; 667 */ 668 struct dc_plane_state *dc_create_plane_state(struct dc *dc); 669 const struct dc_plane_status *dc_plane_get_status( 670 const struct dc_plane_state *plane_state); 671 672 void dc_plane_state_retain(struct dc_plane_state *plane_state); 673 void dc_plane_state_release(struct dc_plane_state *plane_state); 674 675 void dc_gamma_retain(struct dc_gamma *dc_gamma); 676 void dc_gamma_release(struct dc_gamma **dc_gamma); 677 struct dc_gamma *dc_create_gamma(void); 678 679 void dc_transfer_func_retain(struct dc_transfer_func *dc_tf); 680 void dc_transfer_func_release(struct dc_transfer_func *dc_tf); 681 struct dc_transfer_func *dc_create_transfer_func(void); 682 683 /* 684 * This structure holds a surface address. There could be multiple addresses 685 * in cases such as Stereo 3D, Planar YUV, etc. Other per-flip attributes such 686 * as frame durations and DCC format can also be set. 687 */ 688 struct dc_flip_addrs { 689 struct dc_plane_address address; 690 unsigned int flip_timestamp_in_us; 691 bool flip_immediate; 692 /* TODO: add flip duration for FreeSync */ 693 }; 694 695 bool dc_post_update_surfaces_to_stream( 696 struct dc *dc); 697 698 #include "dc_stream.h" 699 700 /* 701 * Structure to store surface/stream associations for validation 702 */ 703 struct dc_validation_set { 704 struct dc_stream_state *stream; 705 struct dc_plane_state *plane_states[MAX_SURFACES]; 706 uint8_t plane_count; 707 }; 708 709 bool dc_validate_seamless_boot_timing(const struct dc *dc, 710 const struct dc_sink *sink, 711 struct dc_crtc_timing *crtc_timing); 712 713 enum dc_status dc_validate_plane(struct dc *dc, const struct dc_plane_state *plane_state); 714 715 void get_clock_requirements_for_state(struct dc_state *state, struct AsicStateEx *info); 716 717 /* 718 * fast_validate: we return after determining if we can support the new state, 719 * but before we populate the programming info 720 */ 721 enum dc_status dc_validate_global_state( 722 struct dc *dc, 723 struct dc_state *new_ctx, 724 bool fast_validate); 725 726 727 void dc_resource_state_construct( 728 const struct dc *dc, 729 struct dc_state *dst_ctx); 730 731 void dc_resource_state_copy_construct( 732 const struct dc_state *src_ctx, 733 struct dc_state *dst_ctx); 734 735 void dc_resource_state_copy_construct_current( 736 const struct dc *dc, 737 struct dc_state *dst_ctx); 738 739 void dc_resource_state_destruct(struct dc_state *context); 740 741 /* 742 * TODO update to make it about validation sets 743 * Set up streams and links associated to drive sinks 744 * The streams parameter is an absolute set of all active streams. 745 * 746 * After this call: 747 * Phy, Encoder, Timing Generator are programmed and enabled. 748 * New streams are enabled with blank stream; no memory read. 749 */ 750 bool dc_commit_state(struct dc *dc, struct dc_state *context); 751 752 753 struct dc_state *dc_create_state(struct dc *dc); 754 struct dc_state *dc_copy_state(struct dc_state *src_ctx); 755 void dc_retain_state(struct dc_state *context); 756 void dc_release_state(struct dc_state *context); 757 758 /******************************************************************************* 759 * Link Interfaces 760 ******************************************************************************/ 761 762 struct dpcd_caps { 763 union dpcd_rev dpcd_rev; 764 union max_lane_count max_ln_count; 765 union max_down_spread max_down_spread; 766 union dprx_feature dprx_feature; 767 768 /* valid only for eDP v1.4 or higher*/ 769 uint8_t edp_supported_link_rates_count; 770 enum dc_link_rate edp_supported_link_rates[8]; 771 772 /* dongle type (DP converter, CV smart dongle) */ 773 enum display_dongle_type dongle_type; 774 /* branch device or sink device */ 775 bool is_branch_dev; 776 /* Dongle's downstream count. */ 777 union sink_count sink_count; 778 /* If dongle_type == DISPLAY_DONGLE_DP_HDMI_CONVERTER, 779 indicates 'Frame Sequential-to-lllFrame Pack' conversion capability.*/ 780 struct dc_dongle_caps dongle_caps; 781 782 uint32_t sink_dev_id; 783 int8_t sink_dev_id_str[6]; 784 int8_t sink_hw_revision; 785 int8_t sink_fw_revision[2]; 786 787 uint32_t branch_dev_id; 788 int8_t branch_dev_name[6]; 789 int8_t branch_hw_revision; 790 int8_t branch_fw_revision[2]; 791 792 bool allow_invalid_MSA_timing_param; 793 bool panel_mode_edp; 794 bool dpcd_display_control_capable; 795 bool ext_receiver_cap_field_present; 796 }; 797 798 #include "dc_link.h" 799 800 /******************************************************************************* 801 * Sink Interfaces - A sink corresponds to a display output device 802 ******************************************************************************/ 803 804 struct dc_container_id { 805 // 128bit GUID in binary form 806 unsigned char guid[16]; 807 // 8 byte port ID -> ELD.PortID 808 unsigned int portId[2]; 809 // 128bit GUID in binary formufacturer name -> ELD.ManufacturerName 810 unsigned short manufacturerName; 811 // 2 byte product code -> ELD.ProductCode 812 unsigned short productCode; 813 }; 814 815 816 817 /* 818 * The sink structure contains EDID and other display device properties 819 */ 820 struct dc_sink { 821 enum signal_type sink_signal; 822 struct dc_edid dc_edid; /* raw edid */ 823 struct dc_edid_caps edid_caps; /* parse display caps */ 824 struct dc_container_id *dc_container_id; 825 uint32_t dongle_max_pix_clk; 826 void *priv; 827 struct stereo_3d_features features_3d[TIMING_3D_FORMAT_MAX]; 828 bool converter_disable_audio; 829 830 /* private to DC core */ 831 struct dc_link *link; 832 struct dc_context *ctx; 833 834 uint32_t sink_id; 835 836 /* private to dc_sink.c */ 837 // refcount must be the last member in dc_sink, since we want the 838 // sink structure to be logically cloneable up to (but not including) 839 // refcount 840 struct kref refcount; 841 }; 842 843 void dc_sink_retain(struct dc_sink *sink); 844 void dc_sink_release(struct dc_sink *sink); 845 846 struct dc_sink_init_data { 847 enum signal_type sink_signal; 848 struct dc_link *link; 849 uint32_t dongle_max_pix_clk; 850 bool converter_disable_audio; 851 }; 852 853 struct dc_sink *dc_sink_create(const struct dc_sink_init_data *init_params); 854 855 /* Newer interfaces */ 856 struct dc_cursor { 857 struct dc_plane_address address; 858 struct dc_cursor_attributes attributes; 859 }; 860 861 862 /******************************************************************************* 863 * Interrupt interfaces 864 ******************************************************************************/ 865 enum dc_irq_source dc_interrupt_to_irq_source( 866 struct dc *dc, 867 uint32_t src_id, 868 uint32_t ext_id); 869 bool dc_interrupt_set(struct dc *dc, enum dc_irq_source src, bool enable); 870 void dc_interrupt_ack(struct dc *dc, enum dc_irq_source src); 871 enum dc_irq_source dc_get_hpd_irq_source_at_index( 872 struct dc *dc, uint32_t link_index); 873 874 /******************************************************************************* 875 * Power Interfaces 876 ******************************************************************************/ 877 878 void dc_set_power_state( 879 struct dc *dc, 880 enum dc_acpi_cm_power_state power_state); 881 void dc_resume(struct dc *dc); 882 unsigned int dc_get_current_backlight_pwm(struct dc *dc); 883 unsigned int dc_get_target_backlight_pwm(struct dc *dc); 884 885 bool dc_is_dmcu_initialized(struct dc *dc); 886 887 #endif /* DC_INTERFACE_H_ */ 888