1 /* 2 * Copyright 2012-14 Advanced Micro Devices, Inc. 3 * 4 * Permission is hereby granted, free of charge, to any person obtaining a 5 * copy of this software and associated documentation files (the "Software"), 6 * to deal in the Software without restriction, including without limitation 7 * the rights to use, copy, modify, merge, publish, distribute, sublicense, 8 * and/or sell copies of the Software, and to permit persons to whom the 9 * Software is furnished to do so, subject to the following conditions: 10 * 11 * The above copyright notice and this permission notice shall be included in 12 * all copies or substantial portions of the Software. 13 * 14 * THE SOFTWARE IS PROVIDED "AS IS", WITHOUT WARRANTY OF ANY KIND, EXPRESS OR 15 * IMPLIED, INCLUDING BUT NOT LIMITED TO THE WARRANTIES OF MERCHANTABILITY, 16 * FITNESS FOR A PARTICULAR PURPOSE AND NONINFRINGEMENT. IN NO EVENT SHALL 17 * THE COPYRIGHT HOLDER(S) OR AUTHOR(S) BE LIABLE FOR ANY CLAIM, DAMAGES OR 18 * OTHER LIABILITY, WHETHER IN AN ACTION OF CONTRACT, TORT OR OTHERWISE, 19 * ARISING FROM, OUT OF OR IN CONNECTION WITH THE SOFTWARE OR THE USE OR 20 * OTHER DEALINGS IN THE SOFTWARE. 21 * 22 * Authors: AMD 23 * 24 */ 25 26 #ifndef DC_INTERFACE_H_ 27 #define DC_INTERFACE_H_ 28 29 #include "dc_types.h" 30 #include "grph_object_defs.h" 31 #include "logger_types.h" 32 #if defined(CONFIG_DRM_AMD_DC_HDCP) 33 #include "hdcp_types.h" 34 #endif 35 #include "gpio_types.h" 36 #include "link_service_types.h" 37 #include "grph_object_ctrl_defs.h" 38 #include <inc/hw/opp.h> 39 40 #include "inc/hw_sequencer.h" 41 #include "inc/compressor.h" 42 #include "inc/hw/dmcu.h" 43 #include "dml/display_mode_lib.h" 44 45 /* forward declaration */ 46 struct aux_payload; 47 struct set_config_cmd_payload; 48 struct dmub_notification; 49 50 #define DC_VER "3.2.212" 51 52 #define MAX_SURFACES 3 53 #define MAX_PLANES 6 54 #define MAX_STREAMS 6 55 #define MAX_SINKS_PER_LINK 4 56 #define MIN_VIEWPORT_SIZE 12 57 #define MAX_NUM_EDP 2 58 59 /* Display Core Interfaces */ 60 struct dc_versions { 61 const char *dc_ver; 62 struct dmcu_version dmcu_version; 63 }; 64 65 enum dp_protocol_version { 66 DP_VERSION_1_4, 67 }; 68 69 enum dc_plane_type { 70 DC_PLANE_TYPE_INVALID, 71 DC_PLANE_TYPE_DCE_RGB, 72 DC_PLANE_TYPE_DCE_UNDERLAY, 73 DC_PLANE_TYPE_DCN_UNIVERSAL, 74 }; 75 76 // Sizes defined as multiples of 64KB 77 enum det_size { 78 DET_SIZE_DEFAULT = 0, 79 DET_SIZE_192KB = 3, 80 DET_SIZE_256KB = 4, 81 DET_SIZE_320KB = 5, 82 DET_SIZE_384KB = 6 83 }; 84 85 86 struct dc_plane_cap { 87 enum dc_plane_type type; 88 uint32_t blends_with_above : 1; 89 uint32_t blends_with_below : 1; 90 uint32_t per_pixel_alpha : 1; 91 struct { 92 uint32_t argb8888 : 1; 93 uint32_t nv12 : 1; 94 uint32_t fp16 : 1; 95 uint32_t p010 : 1; 96 uint32_t ayuv : 1; 97 } pixel_format_support; 98 // max upscaling factor x1000 99 // upscaling factors are always >= 1 100 // for example, 1080p -> 8K is 4.0, or 4000 raw value 101 struct { 102 uint32_t argb8888; 103 uint32_t nv12; 104 uint32_t fp16; 105 } max_upscale_factor; 106 // max downscale factor x1000 107 // downscale factors are always <= 1 108 // for example, 8K -> 1080p is 0.25, or 250 raw value 109 struct { 110 uint32_t argb8888; 111 uint32_t nv12; 112 uint32_t fp16; 113 } max_downscale_factor; 114 // minimal width/height 115 uint32_t min_width; 116 uint32_t min_height; 117 }; 118 119 /** 120 * DOC: color-management-caps 121 * 122 * **Color management caps (DPP and MPC)** 123 * 124 * Modules/color calculates various color operations which are translated to 125 * abstracted HW. DCE 5-12 had almost no important changes, but starting with 126 * DCN1, every new generation comes with fairly major differences in color 127 * pipeline. Therefore, we abstract color pipe capabilities so modules/DM can 128 * decide mapping to HW block based on logical capabilities. 129 */ 130 131 /** 132 * struct rom_curve_caps - predefined transfer function caps for degamma and regamma 133 * @srgb: RGB color space transfer func 134 * @bt2020: BT.2020 transfer func 135 * @gamma2_2: standard gamma 136 * @pq: perceptual quantizer transfer function 137 * @hlg: hybrid log–gamma transfer function 138 */ 139 struct rom_curve_caps { 140 uint16_t srgb : 1; 141 uint16_t bt2020 : 1; 142 uint16_t gamma2_2 : 1; 143 uint16_t pq : 1; 144 uint16_t hlg : 1; 145 }; 146 147 /** 148 * struct dpp_color_caps - color pipeline capabilities for display pipe and 149 * plane blocks 150 * 151 * @dcn_arch: all DCE generations treated the same 152 * @input_lut_shared: shared with DGAM. Input LUT is different than most LUTs, 153 * just plain 256-entry lookup 154 * @icsc: input color space conversion 155 * @dgam_ram: programmable degamma LUT 156 * @post_csc: post color space conversion, before gamut remap 157 * @gamma_corr: degamma correction 158 * @hw_3d_lut: 3D LUT support. It implies a shaper LUT before. It may be shared 159 * with MPC by setting mpc:shared_3d_lut flag 160 * @ogam_ram: programmable out/blend gamma LUT 161 * @ocsc: output color space conversion 162 * @dgam_rom_for_yuv: pre-defined degamma LUT for YUV planes 163 * @dgam_rom_caps: pre-definied curve caps for degamma 1D LUT 164 * @ogam_rom_caps: pre-definied curve caps for regamma 1D LUT 165 * 166 * Note: hdr_mult and gamut remap (CTM) are always available in DPP (in that order) 167 */ 168 struct dpp_color_caps { 169 uint16_t dcn_arch : 1; 170 uint16_t input_lut_shared : 1; 171 uint16_t icsc : 1; 172 uint16_t dgam_ram : 1; 173 uint16_t post_csc : 1; 174 uint16_t gamma_corr : 1; 175 uint16_t hw_3d_lut : 1; 176 uint16_t ogam_ram : 1; 177 uint16_t ocsc : 1; 178 uint16_t dgam_rom_for_yuv : 1; 179 struct rom_curve_caps dgam_rom_caps; 180 struct rom_curve_caps ogam_rom_caps; 181 }; 182 183 /** 184 * struct mpc_color_caps - color pipeline capabilities for multiple pipe and 185 * plane combined blocks 186 * 187 * @gamut_remap: color transformation matrix 188 * @ogam_ram: programmable out gamma LUT 189 * @ocsc: output color space conversion matrix 190 * @num_3dluts: MPC 3D LUT; always assumes a preceding shaper LUT 191 * @shared_3d_lut: shared 3D LUT flag. Can be either DPP or MPC, but single 192 * instance 193 * @ogam_rom_caps: pre-definied curve caps for regamma 1D LUT 194 */ 195 struct mpc_color_caps { 196 uint16_t gamut_remap : 1; 197 uint16_t ogam_ram : 1; 198 uint16_t ocsc : 1; 199 uint16_t num_3dluts : 3; 200 uint16_t shared_3d_lut:1; 201 struct rom_curve_caps ogam_rom_caps; 202 }; 203 204 /** 205 * struct dc_color_caps - color pipes capabilities for DPP and MPC hw blocks 206 * @dpp: color pipes caps for DPP 207 * @mpc: color pipes caps for MPC 208 */ 209 struct dc_color_caps { 210 struct dpp_color_caps dpp; 211 struct mpc_color_caps mpc; 212 }; 213 214 struct dc_dmub_caps { 215 bool psr; 216 bool mclk_sw; 217 }; 218 219 struct dc_caps { 220 uint32_t max_streams; 221 uint32_t max_links; 222 uint32_t max_audios; 223 uint32_t max_slave_planes; 224 uint32_t max_slave_yuv_planes; 225 uint32_t max_slave_rgb_planes; 226 uint32_t max_planes; 227 uint32_t max_downscale_ratio; 228 uint32_t i2c_speed_in_khz; 229 uint32_t i2c_speed_in_khz_hdcp; 230 uint32_t dmdata_alloc_size; 231 unsigned int max_cursor_size; 232 unsigned int max_video_width; 233 unsigned int min_horizontal_blanking_period; 234 int linear_pitch_alignment; 235 bool dcc_const_color; 236 bool dynamic_audio; 237 bool is_apu; 238 bool dual_link_dvi; 239 bool post_blend_color_processing; 240 bool force_dp_tps4_for_cp2520; 241 bool disable_dp_clk_share; 242 bool psp_setup_panel_mode; 243 bool extended_aux_timeout_support; 244 bool dmcub_support; 245 bool zstate_support; 246 uint32_t num_of_internal_disp; 247 enum dp_protocol_version max_dp_protocol_version; 248 unsigned int mall_size_per_mem_channel; 249 unsigned int mall_size_total; 250 unsigned int cursor_cache_size; 251 struct dc_plane_cap planes[MAX_PLANES]; 252 struct dc_color_caps color; 253 struct dc_dmub_caps dmub_caps; 254 bool dp_hpo; 255 bool dp_hdmi21_pcon_support; 256 bool edp_dsc_support; 257 bool vbios_lttpr_aware; 258 bool vbios_lttpr_enable; 259 uint32_t max_otg_num; 260 uint32_t max_cab_allocation_bytes; 261 uint32_t cache_line_size; 262 uint32_t cache_num_ways; 263 uint16_t subvp_fw_processing_delay_us; 264 uint8_t subvp_drr_max_vblank_margin_us; 265 uint16_t subvp_prefetch_end_to_mall_start_us; 266 uint8_t subvp_swath_height_margin_lines; // subvp start line must be aligned to 2 x swath height 267 uint16_t subvp_pstate_allow_width_us; 268 uint16_t subvp_vertical_int_margin_us; 269 bool seamless_odm; 270 }; 271 272 struct dc_bug_wa { 273 bool no_connect_phy_config; 274 bool dedcn20_305_wa; 275 bool skip_clock_update; 276 bool lt_early_cr_pattern; 277 }; 278 279 struct dc_dcc_surface_param { 280 struct dc_size surface_size; 281 enum surface_pixel_format format; 282 enum swizzle_mode_values swizzle_mode; 283 enum dc_scan_direction scan; 284 }; 285 286 struct dc_dcc_setting { 287 unsigned int max_compressed_blk_size; 288 unsigned int max_uncompressed_blk_size; 289 bool independent_64b_blks; 290 //These bitfields to be used starting with DCN 291 struct { 292 uint32_t dcc_256_64_64 : 1;//available in ASICs before DCN (the worst compression case) 293 uint32_t dcc_128_128_uncontrained : 1; //available in ASICs before DCN 294 uint32_t dcc_256_128_128 : 1; //available starting with DCN 295 uint32_t dcc_256_256_unconstrained : 1; //available in ASICs before DCN (the best compression case) 296 } dcc_controls; 297 }; 298 299 struct dc_surface_dcc_cap { 300 union { 301 struct { 302 struct dc_dcc_setting rgb; 303 } grph; 304 305 struct { 306 struct dc_dcc_setting luma; 307 struct dc_dcc_setting chroma; 308 } video; 309 }; 310 311 bool capable; 312 bool const_color_support; 313 }; 314 315 struct dc_static_screen_params { 316 struct { 317 bool force_trigger; 318 bool cursor_update; 319 bool surface_update; 320 bool overlay_update; 321 } triggers; 322 unsigned int num_frames; 323 }; 324 325 326 /* Surface update type is used by dc_update_surfaces_and_stream 327 * The update type is determined at the very beginning of the function based 328 * on parameters passed in and decides how much programming (or updating) is 329 * going to be done during the call. 330 * 331 * UPDATE_TYPE_FAST is used for really fast updates that do not require much 332 * logical calculations or hardware register programming. This update MUST be 333 * ISR safe on windows. Currently fast update will only be used to flip surface 334 * address. 335 * 336 * UPDATE_TYPE_MED is used for slower updates which require significant hw 337 * re-programming however do not affect bandwidth consumption or clock 338 * requirements. At present, this is the level at which front end updates 339 * that do not require us to run bw_calcs happen. These are in/out transfer func 340 * updates, viewport offset changes, recout size changes and pixel depth changes. 341 * This update can be done at ISR, but we want to minimize how often this happens. 342 * 343 * UPDATE_TYPE_FULL is slow. Really slow. This requires us to recalculate our 344 * bandwidth and clocks, possibly rearrange some pipes and reprogram anything front 345 * end related. Any time viewport dimensions, recout dimensions, scaling ratios or 346 * gamma need to be adjusted or pipe needs to be turned on (or disconnected) we do 347 * a full update. This cannot be done at ISR level and should be a rare event. 348 * Unless someone is stress testing mpo enter/exit, playing with colour or adjusting 349 * underscan we don't expect to see this call at all. 350 */ 351 352 enum surface_update_type { 353 UPDATE_TYPE_FAST, /* super fast, safe to execute in isr */ 354 UPDATE_TYPE_MED, /* ISR safe, most of programming needed, no bw/clk change*/ 355 UPDATE_TYPE_FULL, /* may need to shuffle resources */ 356 }; 357 358 /* Forward declaration*/ 359 struct dc; 360 struct dc_plane_state; 361 struct dc_state; 362 363 364 struct dc_cap_funcs { 365 bool (*get_dcc_compression_cap)(const struct dc *dc, 366 const struct dc_dcc_surface_param *input, 367 struct dc_surface_dcc_cap *output); 368 }; 369 370 struct link_training_settings; 371 372 union allow_lttpr_non_transparent_mode { 373 struct { 374 bool DP1_4A : 1; 375 bool DP2_0 : 1; 376 } bits; 377 unsigned char raw; 378 }; 379 380 /* Structure to hold configuration flags set by dm at dc creation. */ 381 struct dc_config { 382 bool gpu_vm_support; 383 bool disable_disp_pll_sharing; 384 bool fbc_support; 385 bool disable_fractional_pwm; 386 bool allow_seamless_boot_optimization; 387 bool seamless_boot_edp_requested; 388 bool edp_not_connected; 389 bool edp_no_power_sequencing; 390 bool force_enum_edp; 391 bool forced_clocks; 392 union allow_lttpr_non_transparent_mode allow_lttpr_non_transparent_mode; 393 bool multi_mon_pp_mclk_switch; 394 bool disable_dmcu; 395 bool enable_4to1MPC; 396 bool enable_windowed_mpo_odm; 397 bool forceHBR2CP2520; // Used for switching between test patterns TPS4 and CP2520 398 uint32_t allow_edp_hotplug_detection; 399 bool clamp_min_dcfclk; 400 uint64_t vblank_alignment_dto_params; 401 uint8_t vblank_alignment_max_frame_time_diff; 402 bool is_asymmetric_memory; 403 bool is_single_rank_dimm; 404 bool is_vmin_only_asic; 405 bool use_pipe_ctx_sync_logic; 406 bool ignore_dpref_ss; 407 bool enable_mipi_converter_optimization; 408 bool use_default_clock_table; 409 bool force_bios_enable_lttpr; 410 uint8_t force_bios_fixed_vs; 411 int sdpif_request_limit_words_per_umc; 412 413 }; 414 415 enum visual_confirm { 416 VISUAL_CONFIRM_DISABLE = 0, 417 VISUAL_CONFIRM_SURFACE = 1, 418 VISUAL_CONFIRM_HDR = 2, 419 VISUAL_CONFIRM_MPCTREE = 4, 420 VISUAL_CONFIRM_PSR = 5, 421 VISUAL_CONFIRM_SWAPCHAIN = 6, 422 VISUAL_CONFIRM_FAMS = 7, 423 VISUAL_CONFIRM_SWIZZLE = 9, 424 VISUAL_CONFIRM_SUBVP = 14, 425 }; 426 427 enum dc_psr_power_opts { 428 psr_power_opt_invalid = 0x0, 429 psr_power_opt_smu_opt_static_screen = 0x1, 430 psr_power_opt_z10_static_screen = 0x10, 431 psr_power_opt_ds_disable_allow = 0x100, 432 }; 433 434 enum dml_hostvm_override_opts { 435 DML_HOSTVM_NO_OVERRIDE = 0x0, 436 DML_HOSTVM_OVERRIDE_FALSE = 0x1, 437 DML_HOSTVM_OVERRIDE_TRUE = 0x2, 438 }; 439 440 enum dcc_option { 441 DCC_ENABLE = 0, 442 DCC_DISABLE = 1, 443 DCC_HALF_REQ_DISALBE = 2, 444 }; 445 446 /** 447 * enum pipe_split_policy - Pipe split strategy supported by DCN 448 * 449 * This enum is used to define the pipe split policy supported by DCN. By 450 * default, DC favors MPC_SPLIT_DYNAMIC. 451 */ 452 enum pipe_split_policy { 453 /** 454 * @MPC_SPLIT_DYNAMIC: DC will automatically decide how to split the 455 * pipe in order to bring the best trade-off between performance and 456 * power consumption. This is the recommended option. 457 */ 458 MPC_SPLIT_DYNAMIC = 0, 459 460 /** 461 * @MPC_SPLIT_AVOID: Avoid pipe split, which means that DC will not 462 * try any sort of split optimization. 463 */ 464 MPC_SPLIT_AVOID = 1, 465 466 /** 467 * @MPC_SPLIT_AVOID_MULT_DISP: With this option, DC will only try to 468 * optimize the pipe utilization when using a single display; if the 469 * user connects to a second display, DC will avoid pipe split. 470 */ 471 MPC_SPLIT_AVOID_MULT_DISP = 2, 472 }; 473 474 enum wm_report_mode { 475 WM_REPORT_DEFAULT = 0, 476 WM_REPORT_OVERRIDE = 1, 477 }; 478 enum dtm_pstate{ 479 dtm_level_p0 = 0,/*highest voltage*/ 480 dtm_level_p1, 481 dtm_level_p2, 482 dtm_level_p3, 483 dtm_level_p4,/*when active_display_count = 0*/ 484 }; 485 486 enum dcn_pwr_state { 487 DCN_PWR_STATE_UNKNOWN = -1, 488 DCN_PWR_STATE_MISSION_MODE = 0, 489 DCN_PWR_STATE_LOW_POWER = 3, 490 }; 491 492 enum dcn_zstate_support_state { 493 DCN_ZSTATE_SUPPORT_UNKNOWN, 494 DCN_ZSTATE_SUPPORT_ALLOW, 495 DCN_ZSTATE_SUPPORT_ALLOW_Z10_ONLY, 496 DCN_ZSTATE_SUPPORT_DISALLOW, 497 }; 498 499 /** 500 * struct dc_clocks - DC pipe clocks 501 * 502 * For any clocks that may differ per pipe only the max is stored in this 503 * structure 504 */ 505 struct dc_clocks { 506 int dispclk_khz; 507 int actual_dispclk_khz; 508 int dppclk_khz; 509 int actual_dppclk_khz; 510 int disp_dpp_voltage_level_khz; 511 int dcfclk_khz; 512 int socclk_khz; 513 int dcfclk_deep_sleep_khz; 514 int fclk_khz; 515 int phyclk_khz; 516 int dramclk_khz; 517 bool p_state_change_support; 518 enum dcn_zstate_support_state zstate_support; 519 bool dtbclk_en; 520 int ref_dtbclk_khz; 521 bool fclk_p_state_change_support; 522 enum dcn_pwr_state pwr_state; 523 /* 524 * Elements below are not compared for the purposes of 525 * optimization required 526 */ 527 bool prev_p_state_change_support; 528 bool fclk_prev_p_state_change_support; 529 int num_ways; 530 531 /* 532 * @fw_based_mclk_switching 533 * 534 * DC has a mechanism that leverage the variable refresh rate to switch 535 * memory clock in cases that we have a large latency to achieve the 536 * memory clock change and a short vblank window. DC has some 537 * requirements to enable this feature, and this field describes if the 538 * system support or not such a feature. 539 */ 540 bool fw_based_mclk_switching; 541 bool fw_based_mclk_switching_shut_down; 542 int prev_num_ways; 543 enum dtm_pstate dtm_level; 544 int max_supported_dppclk_khz; 545 int max_supported_dispclk_khz; 546 int bw_dppclk_khz; /*a copy of dppclk_khz*/ 547 int bw_dispclk_khz; 548 }; 549 550 struct dc_bw_validation_profile { 551 bool enable; 552 553 unsigned long long total_ticks; 554 unsigned long long voltage_level_ticks; 555 unsigned long long watermark_ticks; 556 unsigned long long rq_dlg_ticks; 557 558 unsigned long long total_count; 559 unsigned long long skip_fast_count; 560 unsigned long long skip_pass_count; 561 unsigned long long skip_fail_count; 562 }; 563 564 #define BW_VAL_TRACE_SETUP() \ 565 unsigned long long end_tick = 0; \ 566 unsigned long long voltage_level_tick = 0; \ 567 unsigned long long watermark_tick = 0; \ 568 unsigned long long start_tick = dc->debug.bw_val_profile.enable ? \ 569 dm_get_timestamp(dc->ctx) : 0 570 571 #define BW_VAL_TRACE_COUNT() \ 572 if (dc->debug.bw_val_profile.enable) \ 573 dc->debug.bw_val_profile.total_count++ 574 575 #define BW_VAL_TRACE_SKIP(status) \ 576 if (dc->debug.bw_val_profile.enable) { \ 577 if (!voltage_level_tick) \ 578 voltage_level_tick = dm_get_timestamp(dc->ctx); \ 579 dc->debug.bw_val_profile.skip_ ## status ## _count++; \ 580 } 581 582 #define BW_VAL_TRACE_END_VOLTAGE_LEVEL() \ 583 if (dc->debug.bw_val_profile.enable) \ 584 voltage_level_tick = dm_get_timestamp(dc->ctx) 585 586 #define BW_VAL_TRACE_END_WATERMARKS() \ 587 if (dc->debug.bw_val_profile.enable) \ 588 watermark_tick = dm_get_timestamp(dc->ctx) 589 590 #define BW_VAL_TRACE_FINISH() \ 591 if (dc->debug.bw_val_profile.enable) { \ 592 end_tick = dm_get_timestamp(dc->ctx); \ 593 dc->debug.bw_val_profile.total_ticks += end_tick - start_tick; \ 594 dc->debug.bw_val_profile.voltage_level_ticks += voltage_level_tick - start_tick; \ 595 if (watermark_tick) { \ 596 dc->debug.bw_val_profile.watermark_ticks += watermark_tick - voltage_level_tick; \ 597 dc->debug.bw_val_profile.rq_dlg_ticks += end_tick - watermark_tick; \ 598 } \ 599 } 600 601 union mem_low_power_enable_options { 602 struct { 603 bool vga: 1; 604 bool i2c: 1; 605 bool dmcu: 1; 606 bool dscl: 1; 607 bool cm: 1; 608 bool mpc: 1; 609 bool optc: 1; 610 bool vpg: 1; 611 bool afmt: 1; 612 } bits; 613 uint32_t u32All; 614 }; 615 616 union root_clock_optimization_options { 617 struct { 618 bool dpp: 1; 619 bool dsc: 1; 620 bool hdmistream: 1; 621 bool hdmichar: 1; 622 bool dpstream: 1; 623 bool symclk32_se: 1; 624 bool symclk32_le: 1; 625 bool symclk_fe: 1; 626 bool physymclk: 1; 627 bool dpiasymclk: 1; 628 uint32_t reserved: 22; 629 } bits; 630 uint32_t u32All; 631 }; 632 633 union dpia_debug_options { 634 struct { 635 uint32_t disable_dpia:1; /* bit 0 */ 636 uint32_t force_non_lttpr:1; /* bit 1 */ 637 uint32_t extend_aux_rd_interval:1; /* bit 2 */ 638 uint32_t disable_mst_dsc_work_around:1; /* bit 3 */ 639 uint32_t enable_force_tbt3_work_around:1; /* bit 4 */ 640 uint32_t reserved:27; 641 } bits; 642 uint32_t raw; 643 }; 644 645 /* AUX wake work around options 646 * 0: enable/disable work around 647 * 1: use default timeout LINK_AUX_WAKE_TIMEOUT_MS 648 * 15-2: reserved 649 * 31-16: timeout in ms 650 */ 651 union aux_wake_wa_options { 652 struct { 653 uint32_t enable_wa : 1; 654 uint32_t use_default_timeout : 1; 655 uint32_t rsvd: 14; 656 uint32_t timeout_ms : 16; 657 } bits; 658 uint32_t raw; 659 }; 660 661 struct dc_debug_data { 662 uint32_t ltFailCount; 663 uint32_t i2cErrorCount; 664 uint32_t auxErrorCount; 665 }; 666 667 struct dc_phy_addr_space_config { 668 struct { 669 uint64_t start_addr; 670 uint64_t end_addr; 671 uint64_t fb_top; 672 uint64_t fb_offset; 673 uint64_t fb_base; 674 uint64_t agp_top; 675 uint64_t agp_bot; 676 uint64_t agp_base; 677 } system_aperture; 678 679 struct { 680 uint64_t page_table_start_addr; 681 uint64_t page_table_end_addr; 682 uint64_t page_table_base_addr; 683 bool base_addr_is_mc_addr; 684 } gart_config; 685 686 bool valid; 687 bool is_hvm_enabled; 688 uint64_t page_table_default_page_addr; 689 }; 690 691 struct dc_virtual_addr_space_config { 692 uint64_t page_table_base_addr; 693 uint64_t page_table_start_addr; 694 uint64_t page_table_end_addr; 695 uint32_t page_table_block_size_in_bytes; 696 uint8_t page_table_depth; // 1 = 1 level, 2 = 2 level, etc. 0 = invalid 697 }; 698 699 struct dc_bounding_box_overrides { 700 int sr_exit_time_ns; 701 int sr_enter_plus_exit_time_ns; 702 int urgent_latency_ns; 703 int percent_of_ideal_drambw; 704 int dram_clock_change_latency_ns; 705 int dummy_clock_change_latency_ns; 706 int fclk_clock_change_latency_ns; 707 /* This forces a hard min on the DCFCLK we use 708 * for DML. Unlike the debug option for forcing 709 * DCFCLK, this override affects watermark calculations 710 */ 711 int min_dcfclk_mhz; 712 }; 713 714 struct dc_state; 715 struct resource_pool; 716 struct dce_hwseq; 717 718 /** 719 * struct dc_debug_options - DC debug struct 720 * 721 * This struct provides a simple mechanism for developers to change some 722 * configurations, enable/disable features, and activate extra debug options. 723 * This can be very handy to narrow down whether some specific feature is 724 * causing an issue or not. 725 */ 726 struct dc_debug_options { 727 bool native422_support; 728 bool disable_dsc; 729 enum visual_confirm visual_confirm; 730 int visual_confirm_rect_height; 731 732 bool sanity_checks; 733 bool max_disp_clk; 734 bool surface_trace; 735 bool timing_trace; 736 bool clock_trace; 737 bool validation_trace; 738 bool bandwidth_calcs_trace; 739 int max_downscale_src_width; 740 741 /* stutter efficiency related */ 742 bool disable_stutter; 743 bool use_max_lb; 744 enum dcc_option disable_dcc; 745 746 /** 747 * @pipe_split_policy: Define which pipe split policy is used by the 748 * display core. 749 */ 750 enum pipe_split_policy pipe_split_policy; 751 bool force_single_disp_pipe_split; 752 bool voltage_align_fclk; 753 bool disable_min_fclk; 754 755 bool disable_dfs_bypass; 756 bool disable_dpp_power_gate; 757 bool disable_hubp_power_gate; 758 bool disable_dsc_power_gate; 759 int dsc_min_slice_height_override; 760 int dsc_bpp_increment_div; 761 bool disable_pplib_wm_range; 762 enum wm_report_mode pplib_wm_report_mode; 763 unsigned int min_disp_clk_khz; 764 unsigned int min_dpp_clk_khz; 765 unsigned int min_dram_clk_khz; 766 int sr_exit_time_dpm0_ns; 767 int sr_enter_plus_exit_time_dpm0_ns; 768 int sr_exit_time_ns; 769 int sr_enter_plus_exit_time_ns; 770 int urgent_latency_ns; 771 uint32_t underflow_assert_delay_us; 772 int percent_of_ideal_drambw; 773 int dram_clock_change_latency_ns; 774 bool optimized_watermark; 775 int always_scale; 776 bool disable_pplib_clock_request; 777 bool disable_clock_gate; 778 bool disable_mem_low_power; 779 bool pstate_enabled; 780 bool disable_dmcu; 781 bool force_abm_enable; 782 bool disable_stereo_support; 783 bool vsr_support; 784 bool performance_trace; 785 bool az_endpoint_mute_only; 786 bool always_use_regamma; 787 bool recovery_enabled; 788 bool avoid_vbios_exec_table; 789 bool scl_reset_length10; 790 bool hdmi20_disable; 791 bool skip_detection_link_training; 792 uint32_t edid_read_retry_times; 793 unsigned int force_odm_combine; //bit vector based on otg inst 794 unsigned int seamless_boot_odm_combine; 795 unsigned int force_odm_combine_4to1; //bit vector based on otg inst 796 bool disable_z9_mpc; 797 unsigned int force_fclk_khz; 798 bool enable_tri_buf; 799 bool dmub_offload_enabled; 800 bool dmcub_emulation; 801 bool disable_idle_power_optimizations; 802 unsigned int mall_size_override; 803 unsigned int mall_additional_timer_percent; 804 bool mall_error_as_fatal; 805 bool dmub_command_table; /* for testing only */ 806 struct dc_bw_validation_profile bw_val_profile; 807 bool disable_fec; 808 bool disable_48mhz_pwrdwn; 809 /* This forces a hard min on the DCFCLK requested to SMU/PP 810 * watermarks are not affected. 811 */ 812 unsigned int force_min_dcfclk_mhz; 813 int dwb_fi_phase; 814 bool disable_timing_sync; 815 bool cm_in_bypass; 816 int force_clock_mode;/*every mode change.*/ 817 818 bool disable_dram_clock_change_vactive_support; 819 bool validate_dml_output; 820 bool enable_dmcub_surface_flip; 821 bool usbc_combo_phy_reset_wa; 822 bool enable_dram_clock_change_one_display_vactive; 823 /* TODO - remove once tested */ 824 bool legacy_dp2_lt; 825 bool set_mst_en_for_sst; 826 bool disable_uhbr; 827 bool force_dp2_lt_fallback_method; 828 bool ignore_cable_id; 829 union mem_low_power_enable_options enable_mem_low_power; 830 union root_clock_optimization_options root_clock_optimization; 831 bool hpo_optimization; 832 bool force_vblank_alignment; 833 834 /* Enable dmub aux for legacy ddc */ 835 bool enable_dmub_aux_for_legacy_ddc; 836 bool disable_fams; 837 /* FEC/PSR1 sequence enable delay in 100us */ 838 uint8_t fec_enable_delay_in100us; 839 bool enable_driver_sequence_debug; 840 enum det_size crb_alloc_policy; 841 int crb_alloc_policy_min_disp_count; 842 bool disable_z10; 843 bool enable_z9_disable_interface; 844 union dpia_debug_options dpia_debug; 845 bool disable_fixed_vs_aux_timeout_wa; 846 bool force_disable_subvp; 847 bool force_subvp_mclk_switch; 848 bool allow_sw_cursor_fallback; 849 unsigned int force_subvp_num_ways; 850 unsigned int force_mall_ss_num_ways; 851 bool alloc_extra_way_for_cursor; 852 bool force_usr_allow; 853 /* uses value at boot and disables switch */ 854 bool disable_dtb_ref_clk_switch; 855 uint32_t fixed_vs_aux_delay_config_wa; 856 bool extended_blank_optimization; 857 union aux_wake_wa_options aux_wake_wa; 858 uint32_t mst_start_top_delay; 859 uint8_t psr_power_use_phy_fsm; 860 enum dml_hostvm_override_opts dml_hostvm_override; 861 bool dml_disallow_alternate_prefetch_modes; 862 bool use_legacy_soc_bb_mechanism; 863 bool exit_idle_opt_for_cursor_updates; 864 bool enable_single_display_2to1_odm_policy; 865 bool enable_double_buffered_dsc_pg_support; 866 bool enable_dp_dig_pixel_rate_div_policy; 867 enum lttpr_mode lttpr_mode_override; 868 unsigned int dsc_delay_factor_wa_x1000; 869 unsigned int min_prefetch_in_strobe_ns; 870 }; 871 872 struct gpu_info_soc_bounding_box_v1_0; 873 struct dc { 874 struct dc_debug_options debug; 875 struct dc_versions versions; 876 struct dc_caps caps; 877 struct dc_cap_funcs cap_funcs; 878 struct dc_config config; 879 struct dc_bounding_box_overrides bb_overrides; 880 struct dc_bug_wa work_arounds; 881 struct dc_context *ctx; 882 struct dc_phy_addr_space_config vm_pa_config; 883 884 uint8_t link_count; 885 struct dc_link *links[MAX_PIPES * 2]; 886 887 struct dc_state *current_state; 888 struct resource_pool *res_pool; 889 890 struct clk_mgr *clk_mgr; 891 892 /* Display Engine Clock levels */ 893 struct dm_pp_clock_levels sclk_lvls; 894 895 /* Inputs into BW and WM calculations. */ 896 struct bw_calcs_dceip *bw_dceip; 897 struct bw_calcs_vbios *bw_vbios; 898 struct dcn_soc_bounding_box *dcn_soc; 899 struct dcn_ip_params *dcn_ip; 900 struct display_mode_lib dml; 901 902 /* HW functions */ 903 struct hw_sequencer_funcs hwss; 904 struct dce_hwseq *hwseq; 905 906 /* Require to optimize clocks and bandwidth for added/removed planes */ 907 bool optimized_required; 908 bool wm_optimized_required; 909 bool idle_optimizations_allowed; 910 bool enable_c20_dtm_b0; 911 912 /* Require to maintain clocks and bandwidth for UEFI enabled HW */ 913 914 /* FBC compressor */ 915 struct compressor *fbc_compressor; 916 917 struct dc_debug_data debug_data; 918 struct dpcd_vendor_signature vendor_signature; 919 920 const char *build_id; 921 struct vm_helper *vm_helper; 922 923 uint32_t *dcn_reg_offsets; 924 uint32_t *nbio_reg_offsets; 925 926 /* Scratch memory */ 927 struct { 928 struct { 929 /* 930 * For matching clock_limits table in driver with table 931 * from PMFW. 932 */ 933 struct _vcs_dpi_voltage_scaling_st clock_limits[DC__VOLTAGE_STATES]; 934 } update_bw_bounding_box; 935 } scratch; 936 }; 937 938 enum frame_buffer_mode { 939 FRAME_BUFFER_MODE_LOCAL_ONLY = 0, 940 FRAME_BUFFER_MODE_ZFB_ONLY, 941 FRAME_BUFFER_MODE_MIXED_ZFB_AND_LOCAL, 942 } ; 943 944 struct dchub_init_data { 945 int64_t zfb_phys_addr_base; 946 int64_t zfb_mc_base_addr; 947 uint64_t zfb_size_in_byte; 948 enum frame_buffer_mode fb_mode; 949 bool dchub_initialzied; 950 bool dchub_info_valid; 951 }; 952 953 struct dc_init_data { 954 struct hw_asic_id asic_id; 955 void *driver; /* ctx */ 956 struct cgs_device *cgs_device; 957 struct dc_bounding_box_overrides bb_overrides; 958 959 int num_virtual_links; 960 /* 961 * If 'vbios_override' not NULL, it will be called instead 962 * of the real VBIOS. Intended use is Diagnostics on FPGA. 963 */ 964 struct dc_bios *vbios_override; 965 enum dce_environment dce_environment; 966 967 struct dmub_offload_funcs *dmub_if; 968 struct dc_reg_helper_state *dmub_offload; 969 970 struct dc_config flags; 971 uint64_t log_mask; 972 973 struct dpcd_vendor_signature vendor_signature; 974 bool force_smu_not_present; 975 /* 976 * IP offset for run time initializaion of register addresses 977 * 978 * DCN3.5+ will fail dc_create() if these fields are null for them. They are 979 * applicable starting with DCN32/321 and are not used for ASICs upstreamed 980 * before them. 981 */ 982 uint32_t *dcn_reg_offsets; 983 uint32_t *nbio_reg_offsets; 984 }; 985 986 struct dc_callback_init { 987 #ifdef CONFIG_DRM_AMD_DC_HDCP 988 struct cp_psp cp_psp; 989 #else 990 uint8_t reserved; 991 #endif 992 }; 993 994 struct dc *dc_create(const struct dc_init_data *init_params); 995 void dc_hardware_init(struct dc *dc); 996 997 int dc_get_vmid_use_vector(struct dc *dc); 998 void dc_setup_vm_context(struct dc *dc, struct dc_virtual_addr_space_config *va_config, int vmid); 999 /* Returns the number of vmids supported */ 1000 int dc_setup_system_context(struct dc *dc, struct dc_phy_addr_space_config *pa_config); 1001 void dc_init_callbacks(struct dc *dc, 1002 const struct dc_callback_init *init_params); 1003 void dc_deinit_callbacks(struct dc *dc); 1004 void dc_destroy(struct dc **dc); 1005 1006 /* Surface Interfaces */ 1007 1008 enum { 1009 TRANSFER_FUNC_POINTS = 1025 1010 }; 1011 1012 struct dc_hdr_static_metadata { 1013 /* display chromaticities and white point in units of 0.00001 */ 1014 unsigned int chromaticity_green_x; 1015 unsigned int chromaticity_green_y; 1016 unsigned int chromaticity_blue_x; 1017 unsigned int chromaticity_blue_y; 1018 unsigned int chromaticity_red_x; 1019 unsigned int chromaticity_red_y; 1020 unsigned int chromaticity_white_point_x; 1021 unsigned int chromaticity_white_point_y; 1022 1023 uint32_t min_luminance; 1024 uint32_t max_luminance; 1025 uint32_t maximum_content_light_level; 1026 uint32_t maximum_frame_average_light_level; 1027 }; 1028 1029 enum dc_transfer_func_type { 1030 TF_TYPE_PREDEFINED, 1031 TF_TYPE_DISTRIBUTED_POINTS, 1032 TF_TYPE_BYPASS, 1033 TF_TYPE_HWPWL 1034 }; 1035 1036 struct dc_transfer_func_distributed_points { 1037 struct fixed31_32 red[TRANSFER_FUNC_POINTS]; 1038 struct fixed31_32 green[TRANSFER_FUNC_POINTS]; 1039 struct fixed31_32 blue[TRANSFER_FUNC_POINTS]; 1040 1041 uint16_t end_exponent; 1042 uint16_t x_point_at_y1_red; 1043 uint16_t x_point_at_y1_green; 1044 uint16_t x_point_at_y1_blue; 1045 }; 1046 1047 enum dc_transfer_func_predefined { 1048 TRANSFER_FUNCTION_SRGB, 1049 TRANSFER_FUNCTION_BT709, 1050 TRANSFER_FUNCTION_PQ, 1051 TRANSFER_FUNCTION_LINEAR, 1052 TRANSFER_FUNCTION_UNITY, 1053 TRANSFER_FUNCTION_HLG, 1054 TRANSFER_FUNCTION_HLG12, 1055 TRANSFER_FUNCTION_GAMMA22, 1056 TRANSFER_FUNCTION_GAMMA24, 1057 TRANSFER_FUNCTION_GAMMA26 1058 }; 1059 1060 1061 struct dc_transfer_func { 1062 struct kref refcount; 1063 enum dc_transfer_func_type type; 1064 enum dc_transfer_func_predefined tf; 1065 /* FP16 1.0 reference level in nits, default is 80 nits, only for PQ*/ 1066 uint32_t sdr_ref_white_level; 1067 union { 1068 struct pwl_params pwl; 1069 struct dc_transfer_func_distributed_points tf_pts; 1070 }; 1071 }; 1072 1073 1074 union dc_3dlut_state { 1075 struct { 1076 uint32_t initialized:1; /*if 3dlut is went through color module for initialization */ 1077 uint32_t rmu_idx_valid:1; /*if mux settings are valid*/ 1078 uint32_t rmu_mux_num:3; /*index of mux to use*/ 1079 uint32_t mpc_rmu0_mux:4; /*select mpcc on mux, one of the following : mpcc0, mpcc1, mpcc2, mpcc3*/ 1080 uint32_t mpc_rmu1_mux:4; 1081 uint32_t mpc_rmu2_mux:4; 1082 uint32_t reserved:15; 1083 } bits; 1084 uint32_t raw; 1085 }; 1086 1087 1088 struct dc_3dlut { 1089 struct kref refcount; 1090 struct tetrahedral_params lut_3d; 1091 struct fixed31_32 hdr_multiplier; 1092 union dc_3dlut_state state; 1093 }; 1094 /* 1095 * This structure is filled in by dc_surface_get_status and contains 1096 * the last requested address and the currently active address so the called 1097 * can determine if there are any outstanding flips 1098 */ 1099 struct dc_plane_status { 1100 struct dc_plane_address requested_address; 1101 struct dc_plane_address current_address; 1102 bool is_flip_pending; 1103 bool is_right_eye; 1104 }; 1105 1106 union surface_update_flags { 1107 1108 struct { 1109 uint32_t addr_update:1; 1110 /* Medium updates */ 1111 uint32_t dcc_change:1; 1112 uint32_t color_space_change:1; 1113 uint32_t horizontal_mirror_change:1; 1114 uint32_t per_pixel_alpha_change:1; 1115 uint32_t global_alpha_change:1; 1116 uint32_t hdr_mult:1; 1117 uint32_t rotation_change:1; 1118 uint32_t swizzle_change:1; 1119 uint32_t scaling_change:1; 1120 uint32_t position_change:1; 1121 uint32_t in_transfer_func_change:1; 1122 uint32_t input_csc_change:1; 1123 uint32_t coeff_reduction_change:1; 1124 uint32_t output_tf_change:1; 1125 uint32_t pixel_format_change:1; 1126 uint32_t plane_size_change:1; 1127 uint32_t gamut_remap_change:1; 1128 1129 /* Full updates */ 1130 uint32_t new_plane:1; 1131 uint32_t bpp_change:1; 1132 uint32_t gamma_change:1; 1133 uint32_t bandwidth_change:1; 1134 uint32_t clock_change:1; 1135 uint32_t stereo_format_change:1; 1136 uint32_t lut_3d:1; 1137 uint32_t tmz_changed:1; 1138 uint32_t full_update:1; 1139 } bits; 1140 1141 uint32_t raw; 1142 }; 1143 1144 struct dc_plane_state { 1145 struct dc_plane_address address; 1146 struct dc_plane_flip_time time; 1147 bool triplebuffer_flips; 1148 struct scaling_taps scaling_quality; 1149 struct rect src_rect; 1150 struct rect dst_rect; 1151 struct rect clip_rect; 1152 1153 struct plane_size plane_size; 1154 union dc_tiling_info tiling_info; 1155 1156 struct dc_plane_dcc_param dcc; 1157 1158 struct dc_gamma *gamma_correction; 1159 struct dc_transfer_func *in_transfer_func; 1160 struct dc_bias_and_scale *bias_and_scale; 1161 struct dc_csc_transform input_csc_color_matrix; 1162 struct fixed31_32 coeff_reduction_factor; 1163 struct fixed31_32 hdr_mult; 1164 struct colorspace_transform gamut_remap_matrix; 1165 1166 // TODO: No longer used, remove 1167 struct dc_hdr_static_metadata hdr_static_ctx; 1168 1169 enum dc_color_space color_space; 1170 1171 struct dc_3dlut *lut3d_func; 1172 struct dc_transfer_func *in_shaper_func; 1173 struct dc_transfer_func *blend_tf; 1174 1175 struct dc_transfer_func *gamcor_tf; 1176 enum surface_pixel_format format; 1177 enum dc_rotation_angle rotation; 1178 enum plane_stereo_format stereo_format; 1179 1180 bool is_tiling_rotated; 1181 bool per_pixel_alpha; 1182 bool pre_multiplied_alpha; 1183 bool global_alpha; 1184 int global_alpha_value; 1185 bool visible; 1186 bool flip_immediate; 1187 bool horizontal_mirror; 1188 int layer_index; 1189 1190 union surface_update_flags update_flags; 1191 bool flip_int_enabled; 1192 bool skip_manual_trigger; 1193 1194 /* private to DC core */ 1195 struct dc_plane_status status; 1196 struct dc_context *ctx; 1197 1198 /* HACK: Workaround for forcing full reprogramming under some conditions */ 1199 bool force_full_update; 1200 1201 bool is_phantom; // TODO: Change mall_stream_config into mall_plane_config instead 1202 1203 /* private to dc_surface.c */ 1204 enum dc_irq_source irq_source; 1205 struct kref refcount; 1206 struct tg_color visual_confirm_color; 1207 1208 bool is_statically_allocated; 1209 }; 1210 1211 struct dc_plane_info { 1212 struct plane_size plane_size; 1213 union dc_tiling_info tiling_info; 1214 struct dc_plane_dcc_param dcc; 1215 enum surface_pixel_format format; 1216 enum dc_rotation_angle rotation; 1217 enum plane_stereo_format stereo_format; 1218 enum dc_color_space color_space; 1219 bool horizontal_mirror; 1220 bool visible; 1221 bool per_pixel_alpha; 1222 bool pre_multiplied_alpha; 1223 bool global_alpha; 1224 int global_alpha_value; 1225 bool input_csc_enabled; 1226 int layer_index; 1227 }; 1228 1229 struct dc_scaling_info { 1230 struct rect src_rect; 1231 struct rect dst_rect; 1232 struct rect clip_rect; 1233 struct scaling_taps scaling_quality; 1234 }; 1235 1236 struct dc_surface_update { 1237 struct dc_plane_state *surface; 1238 1239 /* isr safe update parameters. null means no updates */ 1240 const struct dc_flip_addrs *flip_addr; 1241 const struct dc_plane_info *plane_info; 1242 const struct dc_scaling_info *scaling_info; 1243 struct fixed31_32 hdr_mult; 1244 /* following updates require alloc/sleep/spin that is not isr safe, 1245 * null means no updates 1246 */ 1247 const struct dc_gamma *gamma; 1248 const struct dc_transfer_func *in_transfer_func; 1249 1250 const struct dc_csc_transform *input_csc_color_matrix; 1251 const struct fixed31_32 *coeff_reduction_factor; 1252 const struct dc_transfer_func *func_shaper; 1253 const struct dc_3dlut *lut3d_func; 1254 const struct dc_transfer_func *blend_tf; 1255 const struct colorspace_transform *gamut_remap_matrix; 1256 }; 1257 1258 /* 1259 * Create a new surface with default parameters; 1260 */ 1261 struct dc_plane_state *dc_create_plane_state(struct dc *dc); 1262 const struct dc_plane_status *dc_plane_get_status( 1263 const struct dc_plane_state *plane_state); 1264 1265 void dc_plane_state_retain(struct dc_plane_state *plane_state); 1266 void dc_plane_state_release(struct dc_plane_state *plane_state); 1267 1268 void dc_gamma_retain(struct dc_gamma *dc_gamma); 1269 void dc_gamma_release(struct dc_gamma **dc_gamma); 1270 struct dc_gamma *dc_create_gamma(void); 1271 1272 void dc_transfer_func_retain(struct dc_transfer_func *dc_tf); 1273 void dc_transfer_func_release(struct dc_transfer_func *dc_tf); 1274 struct dc_transfer_func *dc_create_transfer_func(void); 1275 1276 struct dc_3dlut *dc_create_3dlut_func(void); 1277 void dc_3dlut_func_release(struct dc_3dlut *lut); 1278 void dc_3dlut_func_retain(struct dc_3dlut *lut); 1279 1280 void dc_post_update_surfaces_to_stream( 1281 struct dc *dc); 1282 1283 #include "dc_stream.h" 1284 1285 /** 1286 * struct dc_validation_set - Struct to store surface/stream associations for validation 1287 */ 1288 struct dc_validation_set { 1289 /** 1290 * @stream: Stream state properties 1291 */ 1292 struct dc_stream_state *stream; 1293 1294 /** 1295 * @plane_state: Surface state 1296 */ 1297 struct dc_plane_state *plane_states[MAX_SURFACES]; 1298 1299 /** 1300 * @plane_count: Total of active planes 1301 */ 1302 uint8_t plane_count; 1303 }; 1304 1305 bool dc_validate_boot_timing(const struct dc *dc, 1306 const struct dc_sink *sink, 1307 struct dc_crtc_timing *crtc_timing); 1308 1309 enum dc_status dc_validate_plane(struct dc *dc, const struct dc_plane_state *plane_state); 1310 1311 void get_clock_requirements_for_state(struct dc_state *state, struct AsicStateEx *info); 1312 1313 enum dc_status dc_validate_with_context(struct dc *dc, 1314 const struct dc_validation_set set[], 1315 int set_count, 1316 struct dc_state *context, 1317 bool fast_validate); 1318 1319 bool dc_set_generic_gpio_for_stereo(bool enable, 1320 struct gpio_service *gpio_service); 1321 1322 /* 1323 * fast_validate: we return after determining if we can support the new state, 1324 * but before we populate the programming info 1325 */ 1326 enum dc_status dc_validate_global_state( 1327 struct dc *dc, 1328 struct dc_state *new_ctx, 1329 bool fast_validate); 1330 1331 1332 void dc_resource_state_construct( 1333 const struct dc *dc, 1334 struct dc_state *dst_ctx); 1335 1336 bool dc_acquire_release_mpc_3dlut( 1337 struct dc *dc, bool acquire, 1338 struct dc_stream_state *stream, 1339 struct dc_3dlut **lut, 1340 struct dc_transfer_func **shaper); 1341 1342 void dc_resource_state_copy_construct( 1343 const struct dc_state *src_ctx, 1344 struct dc_state *dst_ctx); 1345 1346 void dc_resource_state_copy_construct_current( 1347 const struct dc *dc, 1348 struct dc_state *dst_ctx); 1349 1350 void dc_resource_state_destruct(struct dc_state *context); 1351 1352 bool dc_resource_is_dsc_encoding_supported(const struct dc *dc); 1353 1354 enum dc_status dc_commit_streams(struct dc *dc, 1355 struct dc_stream_state *streams[], 1356 uint8_t stream_count); 1357 1358 /* TODO: When the transition to the new commit sequence is done, remove this 1359 * function in favor of dc_commit_streams. */ 1360 bool dc_commit_state(struct dc *dc, struct dc_state *context); 1361 1362 struct dc_state *dc_create_state(struct dc *dc); 1363 struct dc_state *dc_copy_state(struct dc_state *src_ctx); 1364 void dc_retain_state(struct dc_state *context); 1365 void dc_release_state(struct dc_state *context); 1366 1367 /* Link Interfaces */ 1368 1369 struct dpcd_caps { 1370 union dpcd_rev dpcd_rev; 1371 union max_lane_count max_ln_count; 1372 union max_down_spread max_down_spread; 1373 union dprx_feature dprx_feature; 1374 1375 /* valid only for eDP v1.4 or higher*/ 1376 uint8_t edp_supported_link_rates_count; 1377 enum dc_link_rate edp_supported_link_rates[8]; 1378 1379 /* dongle type (DP converter, CV smart dongle) */ 1380 enum display_dongle_type dongle_type; 1381 bool is_dongle_type_one; 1382 /* branch device or sink device */ 1383 bool is_branch_dev; 1384 /* Dongle's downstream count. */ 1385 union sink_count sink_count; 1386 bool is_mst_capable; 1387 /* If dongle_type == DISPLAY_DONGLE_DP_HDMI_CONVERTER, 1388 indicates 'Frame Sequential-to-lllFrame Pack' conversion capability.*/ 1389 struct dc_dongle_caps dongle_caps; 1390 1391 uint32_t sink_dev_id; 1392 int8_t sink_dev_id_str[6]; 1393 int8_t sink_hw_revision; 1394 int8_t sink_fw_revision[2]; 1395 1396 uint32_t branch_dev_id; 1397 int8_t branch_dev_name[6]; 1398 int8_t branch_hw_revision; 1399 int8_t branch_fw_revision[2]; 1400 1401 bool allow_invalid_MSA_timing_param; 1402 bool panel_mode_edp; 1403 bool dpcd_display_control_capable; 1404 bool ext_receiver_cap_field_present; 1405 bool set_power_state_capable_edp; 1406 bool dynamic_backlight_capable_edp; 1407 union dpcd_fec_capability fec_cap; 1408 struct dpcd_dsc_capabilities dsc_caps; 1409 struct dc_lttpr_caps lttpr_caps; 1410 struct dpcd_usb4_dp_tunneling_info usb4_dp_tun_info; 1411 1412 union dp_128b_132b_supported_link_rates dp_128b_132b_supported_link_rates; 1413 union dp_main_line_channel_coding_cap channel_coding_cap; 1414 union dp_sink_video_fallback_formats fallback_formats; 1415 union dp_fec_capability1 fec_cap1; 1416 union dp_cable_id cable_id; 1417 uint8_t edp_rev; 1418 union edp_alpm_caps alpm_caps; 1419 struct edp_psr_info psr_info; 1420 }; 1421 1422 union dpcd_sink_ext_caps { 1423 struct { 1424 /* 0 - Sink supports backlight adjust via PWM during SDR/HDR mode 1425 * 1 - Sink supports backlight adjust via AUX during SDR/HDR mode. 1426 */ 1427 uint8_t sdr_aux_backlight_control : 1; 1428 uint8_t hdr_aux_backlight_control : 1; 1429 uint8_t reserved_1 : 2; 1430 uint8_t oled : 1; 1431 uint8_t reserved : 3; 1432 } bits; 1433 uint8_t raw; 1434 }; 1435 1436 #if defined(CONFIG_DRM_AMD_DC_HDCP) 1437 union hdcp_rx_caps { 1438 struct { 1439 uint8_t version; 1440 uint8_t reserved; 1441 struct { 1442 uint8_t repeater : 1; 1443 uint8_t hdcp_capable : 1; 1444 uint8_t reserved : 6; 1445 } byte0; 1446 } fields; 1447 uint8_t raw[3]; 1448 }; 1449 1450 union hdcp_bcaps { 1451 struct { 1452 uint8_t HDCP_CAPABLE:1; 1453 uint8_t REPEATER:1; 1454 uint8_t RESERVED:6; 1455 } bits; 1456 uint8_t raw; 1457 }; 1458 1459 struct hdcp_caps { 1460 union hdcp_rx_caps rx_caps; 1461 union hdcp_bcaps bcaps; 1462 }; 1463 #endif 1464 1465 #include "dc_link.h" 1466 1467 uint32_t dc_get_opp_for_plane(struct dc *dc, struct dc_plane_state *plane); 1468 1469 /* Sink Interfaces - A sink corresponds to a display output device */ 1470 1471 struct dc_container_id { 1472 // 128bit GUID in binary form 1473 unsigned char guid[16]; 1474 // 8 byte port ID -> ELD.PortID 1475 unsigned int portId[2]; 1476 // 128bit GUID in binary formufacturer name -> ELD.ManufacturerName 1477 unsigned short manufacturerName; 1478 // 2 byte product code -> ELD.ProductCode 1479 unsigned short productCode; 1480 }; 1481 1482 1483 struct dc_sink_dsc_caps { 1484 // 'true' if these are virtual DPCD's DSC caps (immediately upstream of sink in MST topology), 1485 // 'false' if they are sink's DSC caps 1486 bool is_virtual_dpcd_dsc; 1487 #if defined(CONFIG_DRM_AMD_DC_DCN) 1488 // 'true' if MST topology supports DSC passthrough for sink 1489 // 'false' if MST topology does not support DSC passthrough 1490 bool is_dsc_passthrough_supported; 1491 #endif 1492 struct dsc_dec_dpcd_caps dsc_dec_caps; 1493 }; 1494 1495 struct dc_sink_fec_caps { 1496 bool is_rx_fec_supported; 1497 bool is_topology_fec_supported; 1498 }; 1499 1500 /* 1501 * The sink structure contains EDID and other display device properties 1502 */ 1503 struct dc_sink { 1504 enum signal_type sink_signal; 1505 struct dc_edid dc_edid; /* raw edid */ 1506 struct dc_edid_caps edid_caps; /* parse display caps */ 1507 struct dc_container_id *dc_container_id; 1508 uint32_t dongle_max_pix_clk; 1509 void *priv; 1510 struct stereo_3d_features features_3d[TIMING_3D_FORMAT_MAX]; 1511 bool converter_disable_audio; 1512 1513 struct dc_sink_dsc_caps dsc_caps; 1514 struct dc_sink_fec_caps fec_caps; 1515 1516 bool is_vsc_sdp_colorimetry_supported; 1517 1518 /* private to DC core */ 1519 struct dc_link *link; 1520 struct dc_context *ctx; 1521 1522 uint32_t sink_id; 1523 1524 /* private to dc_sink.c */ 1525 // refcount must be the last member in dc_sink, since we want the 1526 // sink structure to be logically cloneable up to (but not including) 1527 // refcount 1528 struct kref refcount; 1529 }; 1530 1531 void dc_sink_retain(struct dc_sink *sink); 1532 void dc_sink_release(struct dc_sink *sink); 1533 1534 struct dc_sink_init_data { 1535 enum signal_type sink_signal; 1536 struct dc_link *link; 1537 uint32_t dongle_max_pix_clk; 1538 bool converter_disable_audio; 1539 }; 1540 1541 bool dc_extended_blank_supported(struct dc *dc); 1542 1543 struct dc_sink *dc_sink_create(const struct dc_sink_init_data *init_params); 1544 1545 /* Newer interfaces */ 1546 struct dc_cursor { 1547 struct dc_plane_address address; 1548 struct dc_cursor_attributes attributes; 1549 }; 1550 1551 1552 /* Interrupt interfaces */ 1553 enum dc_irq_source dc_interrupt_to_irq_source( 1554 struct dc *dc, 1555 uint32_t src_id, 1556 uint32_t ext_id); 1557 bool dc_interrupt_set(struct dc *dc, enum dc_irq_source src, bool enable); 1558 void dc_interrupt_ack(struct dc *dc, enum dc_irq_source src); 1559 enum dc_irq_source dc_get_hpd_irq_source_at_index( 1560 struct dc *dc, uint32_t link_index); 1561 1562 void dc_notify_vsync_int_state(struct dc *dc, struct dc_stream_state *stream, bool enable); 1563 1564 /* Power Interfaces */ 1565 1566 void dc_set_power_state( 1567 struct dc *dc, 1568 enum dc_acpi_cm_power_state power_state); 1569 void dc_resume(struct dc *dc); 1570 1571 void dc_power_down_on_boot(struct dc *dc); 1572 1573 #if defined(CONFIG_DRM_AMD_DC_HDCP) 1574 /* 1575 * HDCP Interfaces 1576 */ 1577 enum hdcp_message_status dc_process_hdcp_msg( 1578 enum signal_type signal, 1579 struct dc_link *link, 1580 struct hdcp_protection_message *message_info); 1581 #endif 1582 bool dc_is_dmcu_initialized(struct dc *dc); 1583 1584 enum dc_status dc_set_clock(struct dc *dc, enum dc_clock_type clock_type, uint32_t clk_khz, uint32_t stepping); 1585 void dc_get_clock(struct dc *dc, enum dc_clock_type clock_type, struct dc_clock_config *clock_cfg); 1586 1587 bool dc_is_plane_eligible_for_idle_optimizations(struct dc *dc, struct dc_plane_state *plane, 1588 struct dc_cursor_attributes *cursor_attr); 1589 1590 void dc_allow_idle_optimizations(struct dc *dc, bool allow); 1591 1592 /* set min and max memory clock to lowest and highest DPM level, respectively */ 1593 void dc_unlock_memory_clock_frequency(struct dc *dc); 1594 1595 /* set min memory clock to the min required for current mode, max to maxDPM */ 1596 void dc_lock_memory_clock_frequency(struct dc *dc); 1597 1598 /* set soft max for memclk, to be used for AC/DC switching clock limitations */ 1599 void dc_enable_dcmode_clk_limit(struct dc *dc, bool enable); 1600 1601 /* cleanup on driver unload */ 1602 void dc_hardware_release(struct dc *dc); 1603 1604 /* disables fw based mclk switch */ 1605 void dc_mclk_switch_using_fw_based_vblank_stretch_shut_down(struct dc *dc); 1606 1607 bool dc_set_psr_allow_active(struct dc *dc, bool enable); 1608 void dc_z10_restore(const struct dc *dc); 1609 void dc_z10_save_init(struct dc *dc); 1610 1611 bool dc_is_dmub_outbox_supported(struct dc *dc); 1612 bool dc_enable_dmub_notifications(struct dc *dc); 1613 1614 void dc_enable_dmub_outbox(struct dc *dc); 1615 1616 bool dc_process_dmub_aux_transfer_async(struct dc *dc, 1617 uint32_t link_index, 1618 struct aux_payload *payload); 1619 1620 /* Get dc link index from dpia port index */ 1621 uint8_t get_link_index_from_dpia_port_index(const struct dc *dc, 1622 uint8_t dpia_port_index); 1623 1624 bool dc_process_dmub_set_config_async(struct dc *dc, 1625 uint32_t link_index, 1626 struct set_config_cmd_payload *payload, 1627 struct dmub_notification *notify); 1628 1629 enum dc_status dc_process_dmub_set_mst_slots(const struct dc *dc, 1630 uint32_t link_index, 1631 uint8_t mst_alloc_slots, 1632 uint8_t *mst_slots_in_use); 1633 1634 void dc_process_dmub_dpia_hpd_int_enable(const struct dc *dc, 1635 uint32_t hpd_int_enable); 1636 1637 /* DSC Interfaces */ 1638 #include "dc_dsc.h" 1639 1640 /* Disable acc mode Interfaces */ 1641 void dc_disable_accelerated_mode(struct dc *dc); 1642 1643 #endif /* DC_INTERFACE_H_ */ 1644