1 /* 2 * Copyright 2012-14 Advanced Micro Devices, Inc. 3 * 4 * Permission is hereby granted, free of charge, to any person obtaining a 5 * copy of this software and associated documentation files (the "Software"), 6 * to deal in the Software without restriction, including without limitation 7 * the rights to use, copy, modify, merge, publish, distribute, sublicense, 8 * and/or sell copies of the Software, and to permit persons to whom the 9 * Software is furnished to do so, subject to the following conditions: 10 * 11 * The above copyright notice and this permission notice shall be included in 12 * all copies or substantial portions of the Software. 13 * 14 * THE SOFTWARE IS PROVIDED "AS IS", WITHOUT WARRANTY OF ANY KIND, EXPRESS OR 15 * IMPLIED, INCLUDING BUT NOT LIMITED TO THE WARRANTIES OF MERCHANTABILITY, 16 * FITNESS FOR A PARTICULAR PURPOSE AND NONINFRINGEMENT. IN NO EVENT SHALL 17 * THE COPYRIGHT HOLDER(S) OR AUTHOR(S) BE LIABLE FOR ANY CLAIM, DAMAGES OR 18 * OTHER LIABILITY, WHETHER IN AN ACTION OF CONTRACT, TORT OR OTHERWISE, 19 * ARISING FROM, OUT OF OR IN CONNECTION WITH THE SOFTWARE OR THE USE OR 20 * OTHER DEALINGS IN THE SOFTWARE. 21 * 22 * Authors: AMD 23 * 24 */ 25 26 #ifndef DC_INTERFACE_H_ 27 #define DC_INTERFACE_H_ 28 29 #include "dc_types.h" 30 #include "grph_object_defs.h" 31 #include "logger_types.h" 32 #if defined(CONFIG_DRM_AMD_DC_HDCP) 33 #include "hdcp_types.h" 34 #endif 35 #include "gpio_types.h" 36 #include "link_service_types.h" 37 #include "grph_object_ctrl_defs.h" 38 #include <inc/hw/opp.h> 39 40 #include "inc/hw_sequencer.h" 41 #include "inc/compressor.h" 42 #include "inc/hw/dmcu.h" 43 #include "dml/display_mode_lib.h" 44 45 /* forward declaration */ 46 struct aux_payload; 47 48 #define DC_VER "3.2.149" 49 50 #define MAX_SURFACES 3 51 #define MAX_PLANES 6 52 #define MAX_STREAMS 6 53 #define MAX_SINKS_PER_LINK 4 54 #define MIN_VIEWPORT_SIZE 12 55 #define MAX_NUM_EDP 2 56 57 /******************************************************************************* 58 * Display Core Interfaces 59 ******************************************************************************/ 60 struct dc_versions { 61 const char *dc_ver; 62 struct dmcu_version dmcu_version; 63 }; 64 65 enum dp_protocol_version { 66 DP_VERSION_1_4, 67 }; 68 69 enum dc_plane_type { 70 DC_PLANE_TYPE_INVALID, 71 DC_PLANE_TYPE_DCE_RGB, 72 DC_PLANE_TYPE_DCE_UNDERLAY, 73 DC_PLANE_TYPE_DCN_UNIVERSAL, 74 }; 75 76 struct dc_plane_cap { 77 enum dc_plane_type type; 78 uint32_t blends_with_above : 1; 79 uint32_t blends_with_below : 1; 80 uint32_t per_pixel_alpha : 1; 81 struct { 82 uint32_t argb8888 : 1; 83 uint32_t nv12 : 1; 84 uint32_t fp16 : 1; 85 uint32_t p010 : 1; 86 uint32_t ayuv : 1; 87 } pixel_format_support; 88 // max upscaling factor x1000 89 // upscaling factors are always >= 1 90 // for example, 1080p -> 8K is 4.0, or 4000 raw value 91 struct { 92 uint32_t argb8888; 93 uint32_t nv12; 94 uint32_t fp16; 95 } max_upscale_factor; 96 // max downscale factor x1000 97 // downscale factors are always <= 1 98 // for example, 8K -> 1080p is 0.25, or 250 raw value 99 struct { 100 uint32_t argb8888; 101 uint32_t nv12; 102 uint32_t fp16; 103 } max_downscale_factor; 104 // minimal width/height 105 uint32_t min_width; 106 uint32_t min_height; 107 }; 108 109 // Color management caps (DPP and MPC) 110 struct rom_curve_caps { 111 uint16_t srgb : 1; 112 uint16_t bt2020 : 1; 113 uint16_t gamma2_2 : 1; 114 uint16_t pq : 1; 115 uint16_t hlg : 1; 116 }; 117 118 struct dpp_color_caps { 119 uint16_t dcn_arch : 1; // all DCE generations treated the same 120 // input lut is different than most LUTs, just plain 256-entry lookup 121 uint16_t input_lut_shared : 1; // shared with DGAM 122 uint16_t icsc : 1; 123 uint16_t dgam_ram : 1; 124 uint16_t post_csc : 1; // before gamut remap 125 uint16_t gamma_corr : 1; 126 127 // hdr_mult and gamut remap always available in DPP (in that order) 128 // 3d lut implies shaper LUT, 129 // it may be shared with MPC - check MPC:shared_3d_lut flag 130 uint16_t hw_3d_lut : 1; 131 uint16_t ogam_ram : 1; // blnd gam 132 uint16_t ocsc : 1; 133 uint16_t dgam_rom_for_yuv : 1; 134 struct rom_curve_caps dgam_rom_caps; 135 struct rom_curve_caps ogam_rom_caps; 136 }; 137 138 struct mpc_color_caps { 139 uint16_t gamut_remap : 1; 140 uint16_t ogam_ram : 1; 141 uint16_t ocsc : 1; 142 uint16_t num_3dluts : 3; //3d lut always assumes a preceding shaper LUT 143 uint16_t shared_3d_lut:1; //can be in either DPP or MPC, but single instance 144 145 struct rom_curve_caps ogam_rom_caps; 146 }; 147 148 struct dc_color_caps { 149 struct dpp_color_caps dpp; 150 struct mpc_color_caps mpc; 151 }; 152 153 struct dc_caps { 154 uint32_t max_streams; 155 uint32_t max_links; 156 uint32_t max_audios; 157 uint32_t max_slave_planes; 158 uint32_t max_slave_yuv_planes; 159 uint32_t max_slave_rgb_planes; 160 uint32_t max_planes; 161 uint32_t max_downscale_ratio; 162 uint32_t i2c_speed_in_khz; 163 uint32_t i2c_speed_in_khz_hdcp; 164 uint32_t dmdata_alloc_size; 165 unsigned int max_cursor_size; 166 unsigned int max_video_width; 167 unsigned int min_horizontal_blanking_period; 168 int linear_pitch_alignment; 169 bool dcc_const_color; 170 bool dynamic_audio; 171 bool is_apu; 172 bool dual_link_dvi; 173 bool post_blend_color_processing; 174 bool force_dp_tps4_for_cp2520; 175 bool disable_dp_clk_share; 176 bool psp_setup_panel_mode; 177 bool extended_aux_timeout_support; 178 bool dmcub_support; 179 uint32_t num_of_internal_disp; 180 enum dp_protocol_version max_dp_protocol_version; 181 unsigned int mall_size_per_mem_channel; 182 unsigned int mall_size_total; 183 unsigned int cursor_cache_size; 184 struct dc_plane_cap planes[MAX_PLANES]; 185 struct dc_color_caps color; 186 bool vbios_lttpr_aware; 187 bool vbios_lttpr_enable; 188 }; 189 190 struct dc_bug_wa { 191 bool no_connect_phy_config; 192 bool dedcn20_305_wa; 193 bool skip_clock_update; 194 bool lt_early_cr_pattern; 195 }; 196 197 struct dc_dcc_surface_param { 198 struct dc_size surface_size; 199 enum surface_pixel_format format; 200 enum swizzle_mode_values swizzle_mode; 201 enum dc_scan_direction scan; 202 }; 203 204 struct dc_dcc_setting { 205 unsigned int max_compressed_blk_size; 206 unsigned int max_uncompressed_blk_size; 207 bool independent_64b_blks; 208 #if defined(CONFIG_DRM_AMD_DC_DCN) 209 //These bitfields to be used starting with DCN 3.0 210 struct { 211 uint32_t dcc_256_64_64 : 1;//available in ASICs before DCN 3.0 (the worst compression case) 212 uint32_t dcc_128_128_uncontrained : 1; //available in ASICs before DCN 3.0 213 uint32_t dcc_256_128_128 : 1; //available starting with DCN 3.0 214 uint32_t dcc_256_256_unconstrained : 1; //available in ASICs before DCN 3.0 (the best compression case) 215 } dcc_controls; 216 #endif 217 }; 218 219 struct dc_surface_dcc_cap { 220 union { 221 struct { 222 struct dc_dcc_setting rgb; 223 } grph; 224 225 struct { 226 struct dc_dcc_setting luma; 227 struct dc_dcc_setting chroma; 228 } video; 229 }; 230 231 bool capable; 232 bool const_color_support; 233 }; 234 235 struct dc_static_screen_params { 236 struct { 237 bool force_trigger; 238 bool cursor_update; 239 bool surface_update; 240 bool overlay_update; 241 } triggers; 242 unsigned int num_frames; 243 }; 244 245 246 /* Surface update type is used by dc_update_surfaces_and_stream 247 * The update type is determined at the very beginning of the function based 248 * on parameters passed in and decides how much programming (or updating) is 249 * going to be done during the call. 250 * 251 * UPDATE_TYPE_FAST is used for really fast updates that do not require much 252 * logical calculations or hardware register programming. This update MUST be 253 * ISR safe on windows. Currently fast update will only be used to flip surface 254 * address. 255 * 256 * UPDATE_TYPE_MED is used for slower updates which require significant hw 257 * re-programming however do not affect bandwidth consumption or clock 258 * requirements. At present, this is the level at which front end updates 259 * that do not require us to run bw_calcs happen. These are in/out transfer func 260 * updates, viewport offset changes, recout size changes and pixel depth changes. 261 * This update can be done at ISR, but we want to minimize how often this happens. 262 * 263 * UPDATE_TYPE_FULL is slow. Really slow. This requires us to recalculate our 264 * bandwidth and clocks, possibly rearrange some pipes and reprogram anything front 265 * end related. Any time viewport dimensions, recout dimensions, scaling ratios or 266 * gamma need to be adjusted or pipe needs to be turned on (or disconnected) we do 267 * a full update. This cannot be done at ISR level and should be a rare event. 268 * Unless someone is stress testing mpo enter/exit, playing with colour or adjusting 269 * underscan we don't expect to see this call at all. 270 */ 271 272 enum surface_update_type { 273 UPDATE_TYPE_FAST, /* super fast, safe to execute in isr */ 274 UPDATE_TYPE_MED, /* ISR safe, most of programming needed, no bw/clk change*/ 275 UPDATE_TYPE_FULL, /* may need to shuffle resources */ 276 }; 277 278 /* Forward declaration*/ 279 struct dc; 280 struct dc_plane_state; 281 struct dc_state; 282 283 284 struct dc_cap_funcs { 285 bool (*get_dcc_compression_cap)(const struct dc *dc, 286 const struct dc_dcc_surface_param *input, 287 struct dc_surface_dcc_cap *output); 288 }; 289 290 struct link_training_settings; 291 292 293 /* Structure to hold configuration flags set by dm at dc creation. */ 294 struct dc_config { 295 bool gpu_vm_support; 296 bool disable_disp_pll_sharing; 297 bool fbc_support; 298 bool disable_fractional_pwm; 299 bool allow_seamless_boot_optimization; 300 bool power_down_display_on_boot; 301 bool edp_not_connected; 302 bool edp_no_power_sequencing; 303 bool force_enum_edp; 304 bool forced_clocks; 305 bool allow_lttpr_non_transparent_mode; 306 bool multi_mon_pp_mclk_switch; 307 bool disable_dmcu; 308 bool enable_4to1MPC; 309 bool allow_edp_hotplug_detection; 310 #if defined(CONFIG_DRM_AMD_DC_DCN) 311 bool clamp_min_dcfclk; 312 #endif 313 uint64_t vblank_alignment_dto_params; 314 uint8_t vblank_alignment_max_frame_time_diff; 315 bool is_asymmetric_memory; 316 bool is_single_rank_dimm; 317 }; 318 319 enum visual_confirm { 320 VISUAL_CONFIRM_DISABLE = 0, 321 VISUAL_CONFIRM_SURFACE = 1, 322 VISUAL_CONFIRM_HDR = 2, 323 VISUAL_CONFIRM_MPCTREE = 4, 324 VISUAL_CONFIRM_PSR = 5, 325 VISUAL_CONFIRM_SWIZZLE = 9, 326 }; 327 328 enum dcc_option { 329 DCC_ENABLE = 0, 330 DCC_DISABLE = 1, 331 DCC_HALF_REQ_DISALBE = 2, 332 }; 333 334 enum pipe_split_policy { 335 MPC_SPLIT_DYNAMIC = 0, 336 MPC_SPLIT_AVOID = 1, 337 MPC_SPLIT_AVOID_MULT_DISP = 2, 338 }; 339 340 enum wm_report_mode { 341 WM_REPORT_DEFAULT = 0, 342 WM_REPORT_OVERRIDE = 1, 343 }; 344 enum dtm_pstate{ 345 dtm_level_p0 = 0,/*highest voltage*/ 346 dtm_level_p1, 347 dtm_level_p2, 348 dtm_level_p3, 349 dtm_level_p4,/*when active_display_count = 0*/ 350 }; 351 352 enum dcn_pwr_state { 353 DCN_PWR_STATE_UNKNOWN = -1, 354 DCN_PWR_STATE_MISSION_MODE = 0, 355 DCN_PWR_STATE_LOW_POWER = 3, 356 }; 357 358 #if defined(CONFIG_DRM_AMD_DC_DCN) 359 enum dcn_zstate_support_state { 360 DCN_ZSTATE_SUPPORT_UNKNOWN, 361 DCN_ZSTATE_SUPPORT_ALLOW, 362 DCN_ZSTATE_SUPPORT_DISALLOW, 363 }; 364 #endif 365 /* 366 * For any clocks that may differ per pipe 367 * only the max is stored in this structure 368 */ 369 struct dc_clocks { 370 int dispclk_khz; 371 int actual_dispclk_khz; 372 int dppclk_khz; 373 int actual_dppclk_khz; 374 int disp_dpp_voltage_level_khz; 375 int dcfclk_khz; 376 int socclk_khz; 377 int dcfclk_deep_sleep_khz; 378 int fclk_khz; 379 int phyclk_khz; 380 int dramclk_khz; 381 bool p_state_change_support; 382 #if defined(CONFIG_DRM_AMD_DC_DCN) 383 enum dcn_zstate_support_state zstate_support; 384 bool dtbclk_en; 385 #endif 386 enum dcn_pwr_state pwr_state; 387 /* 388 * Elements below are not compared for the purposes of 389 * optimization required 390 */ 391 bool prev_p_state_change_support; 392 enum dtm_pstate dtm_level; 393 int max_supported_dppclk_khz; 394 int max_supported_dispclk_khz; 395 int bw_dppclk_khz; /*a copy of dppclk_khz*/ 396 int bw_dispclk_khz; 397 }; 398 399 struct dc_bw_validation_profile { 400 bool enable; 401 402 unsigned long long total_ticks; 403 unsigned long long voltage_level_ticks; 404 unsigned long long watermark_ticks; 405 unsigned long long rq_dlg_ticks; 406 407 unsigned long long total_count; 408 unsigned long long skip_fast_count; 409 unsigned long long skip_pass_count; 410 unsigned long long skip_fail_count; 411 }; 412 413 #define BW_VAL_TRACE_SETUP() \ 414 unsigned long long end_tick = 0; \ 415 unsigned long long voltage_level_tick = 0; \ 416 unsigned long long watermark_tick = 0; \ 417 unsigned long long start_tick = dc->debug.bw_val_profile.enable ? \ 418 dm_get_timestamp(dc->ctx) : 0 419 420 #define BW_VAL_TRACE_COUNT() \ 421 if (dc->debug.bw_val_profile.enable) \ 422 dc->debug.bw_val_profile.total_count++ 423 424 #define BW_VAL_TRACE_SKIP(status) \ 425 if (dc->debug.bw_val_profile.enable) { \ 426 if (!voltage_level_tick) \ 427 voltage_level_tick = dm_get_timestamp(dc->ctx); \ 428 dc->debug.bw_val_profile.skip_ ## status ## _count++; \ 429 } 430 431 #define BW_VAL_TRACE_END_VOLTAGE_LEVEL() \ 432 if (dc->debug.bw_val_profile.enable) \ 433 voltage_level_tick = dm_get_timestamp(dc->ctx) 434 435 #define BW_VAL_TRACE_END_WATERMARKS() \ 436 if (dc->debug.bw_val_profile.enable) \ 437 watermark_tick = dm_get_timestamp(dc->ctx) 438 439 #define BW_VAL_TRACE_FINISH() \ 440 if (dc->debug.bw_val_profile.enable) { \ 441 end_tick = dm_get_timestamp(dc->ctx); \ 442 dc->debug.bw_val_profile.total_ticks += end_tick - start_tick; \ 443 dc->debug.bw_val_profile.voltage_level_ticks += voltage_level_tick - start_tick; \ 444 if (watermark_tick) { \ 445 dc->debug.bw_val_profile.watermark_ticks += watermark_tick - voltage_level_tick; \ 446 dc->debug.bw_val_profile.rq_dlg_ticks += end_tick - watermark_tick; \ 447 } \ 448 } 449 450 union mem_low_power_enable_options { 451 struct { 452 bool vga: 1; 453 bool i2c: 1; 454 bool dmcu: 1; 455 bool dscl: 1; 456 bool cm: 1; 457 bool mpc: 1; 458 bool optc: 1; 459 } bits; 460 uint32_t u32All; 461 }; 462 463 struct dc_debug_data { 464 uint32_t ltFailCount; 465 uint32_t i2cErrorCount; 466 uint32_t auxErrorCount; 467 }; 468 469 struct dc_phy_addr_space_config { 470 struct { 471 uint64_t start_addr; 472 uint64_t end_addr; 473 uint64_t fb_top; 474 uint64_t fb_offset; 475 uint64_t fb_base; 476 uint64_t agp_top; 477 uint64_t agp_bot; 478 uint64_t agp_base; 479 } system_aperture; 480 481 struct { 482 uint64_t page_table_start_addr; 483 uint64_t page_table_end_addr; 484 uint64_t page_table_base_addr; 485 bool base_addr_is_mc_addr; 486 } gart_config; 487 488 bool valid; 489 bool is_hvm_enabled; 490 uint64_t page_table_default_page_addr; 491 }; 492 493 struct dc_virtual_addr_space_config { 494 uint64_t page_table_base_addr; 495 uint64_t page_table_start_addr; 496 uint64_t page_table_end_addr; 497 uint32_t page_table_block_size_in_bytes; 498 uint8_t page_table_depth; // 1 = 1 level, 2 = 2 level, etc. 0 = invalid 499 }; 500 501 struct dc_bounding_box_overrides { 502 int sr_exit_time_ns; 503 int sr_enter_plus_exit_time_ns; 504 int urgent_latency_ns; 505 int percent_of_ideal_drambw; 506 int dram_clock_change_latency_ns; 507 int dummy_clock_change_latency_ns; 508 /* This forces a hard min on the DCFCLK we use 509 * for DML. Unlike the debug option for forcing 510 * DCFCLK, this override affects watermark calculations 511 */ 512 int min_dcfclk_mhz; 513 }; 514 515 struct dc_state; 516 struct resource_pool; 517 struct dce_hwseq; 518 519 struct dc_debug_options { 520 bool native422_support; 521 bool disable_dsc; 522 enum visual_confirm visual_confirm; 523 bool sanity_checks; 524 bool max_disp_clk; 525 bool surface_trace; 526 bool timing_trace; 527 bool clock_trace; 528 bool validation_trace; 529 bool bandwidth_calcs_trace; 530 int max_downscale_src_width; 531 532 /* stutter efficiency related */ 533 bool disable_stutter; 534 bool use_max_lb; 535 enum dcc_option disable_dcc; 536 enum pipe_split_policy pipe_split_policy; 537 bool force_single_disp_pipe_split; 538 bool voltage_align_fclk; 539 bool disable_min_fclk; 540 541 bool disable_dfs_bypass; 542 bool disable_dpp_power_gate; 543 bool disable_hubp_power_gate; 544 bool disable_dsc_power_gate; 545 int dsc_min_slice_height_override; 546 int dsc_bpp_increment_div; 547 bool disable_pplib_wm_range; 548 enum wm_report_mode pplib_wm_report_mode; 549 unsigned int min_disp_clk_khz; 550 unsigned int min_dpp_clk_khz; 551 int sr_exit_time_dpm0_ns; 552 int sr_enter_plus_exit_time_dpm0_ns; 553 int sr_exit_time_ns; 554 int sr_enter_plus_exit_time_ns; 555 int urgent_latency_ns; 556 uint32_t underflow_assert_delay_us; 557 int percent_of_ideal_drambw; 558 int dram_clock_change_latency_ns; 559 bool optimized_watermark; 560 int always_scale; 561 bool disable_pplib_clock_request; 562 bool disable_clock_gate; 563 bool disable_mem_low_power; 564 #if defined(CONFIG_DRM_AMD_DC_DCN) 565 bool pstate_enabled; 566 #endif 567 bool disable_dmcu; 568 bool disable_psr; 569 bool force_abm_enable; 570 bool disable_stereo_support; 571 bool vsr_support; 572 bool performance_trace; 573 bool az_endpoint_mute_only; 574 bool always_use_regamma; 575 bool recovery_enabled; 576 bool avoid_vbios_exec_table; 577 bool scl_reset_length10; 578 bool hdmi20_disable; 579 bool skip_detection_link_training; 580 uint32_t edid_read_retry_times; 581 bool remove_disconnect_edp; 582 unsigned int force_odm_combine; //bit vector based on otg inst 583 #if defined(CONFIG_DRM_AMD_DC_DCN) 584 unsigned int force_odm_combine_4to1; //bit vector based on otg inst 585 bool disable_z9_mpc; 586 #endif 587 unsigned int force_fclk_khz; 588 bool enable_tri_buf; 589 bool dmub_offload_enabled; 590 bool dmcub_emulation; 591 #if defined(CONFIG_DRM_AMD_DC_DCN) 592 bool disable_idle_power_optimizations; 593 unsigned int mall_size_override; 594 unsigned int mall_additional_timer_percent; 595 bool mall_error_as_fatal; 596 #endif 597 bool dmub_command_table; /* for testing only */ 598 struct dc_bw_validation_profile bw_val_profile; 599 bool disable_fec; 600 bool disable_48mhz_pwrdwn; 601 /* This forces a hard min on the DCFCLK requested to SMU/PP 602 * watermarks are not affected. 603 */ 604 unsigned int force_min_dcfclk_mhz; 605 #if defined(CONFIG_DRM_AMD_DC_DCN) 606 int dwb_fi_phase; 607 #endif 608 bool disable_timing_sync; 609 bool cm_in_bypass; 610 int force_clock_mode;/*every mode change.*/ 611 612 bool disable_dram_clock_change_vactive_support; 613 bool validate_dml_output; 614 bool enable_dmcub_surface_flip; 615 bool usbc_combo_phy_reset_wa; 616 bool enable_dram_clock_change_one_display_vactive; 617 union mem_low_power_enable_options enable_mem_low_power; 618 bool force_vblank_alignment; 619 620 /* Enable dmub aux for legacy ddc */ 621 bool enable_dmub_aux_for_legacy_ddc; 622 bool optimize_edp_link_rate; /* eDP ILR */ 623 /* force enable edp FEC */ 624 bool force_enable_edp_fec; 625 /* FEC/PSR1 sequence enable delay in 100us */ 626 uint8_t fec_enable_delay_in100us; 627 #if defined(CONFIG_DRM_AMD_DC_DCN) 628 bool disable_z10; 629 bool enable_sw_cntl_psr; 630 #endif 631 }; 632 633 struct gpu_info_soc_bounding_box_v1_0; 634 struct dc { 635 struct dc_debug_options debug; 636 struct dc_versions versions; 637 struct dc_caps caps; 638 struct dc_cap_funcs cap_funcs; 639 struct dc_config config; 640 struct dc_bounding_box_overrides bb_overrides; 641 struct dc_bug_wa work_arounds; 642 struct dc_context *ctx; 643 struct dc_phy_addr_space_config vm_pa_config; 644 645 uint8_t link_count; 646 struct dc_link *links[MAX_PIPES * 2]; 647 648 struct dc_state *current_state; 649 struct resource_pool *res_pool; 650 651 struct clk_mgr *clk_mgr; 652 653 /* Display Engine Clock levels */ 654 struct dm_pp_clock_levels sclk_lvls; 655 656 /* Inputs into BW and WM calculations. */ 657 struct bw_calcs_dceip *bw_dceip; 658 struct bw_calcs_vbios *bw_vbios; 659 #ifdef CONFIG_DRM_AMD_DC_DCN 660 struct dcn_soc_bounding_box *dcn_soc; 661 struct dcn_ip_params *dcn_ip; 662 struct display_mode_lib dml; 663 #endif 664 665 /* HW functions */ 666 struct hw_sequencer_funcs hwss; 667 struct dce_hwseq *hwseq; 668 669 /* Require to optimize clocks and bandwidth for added/removed planes */ 670 bool optimized_required; 671 bool wm_optimized_required; 672 #if defined(CONFIG_DRM_AMD_DC_DCN) 673 bool idle_optimizations_allowed; 674 #endif 675 676 /* Require to maintain clocks and bandwidth for UEFI enabled HW */ 677 678 /* FBC compressor */ 679 struct compressor *fbc_compressor; 680 681 struct dc_debug_data debug_data; 682 struct dpcd_vendor_signature vendor_signature; 683 684 const char *build_id; 685 struct vm_helper *vm_helper; 686 }; 687 688 enum frame_buffer_mode { 689 FRAME_BUFFER_MODE_LOCAL_ONLY = 0, 690 FRAME_BUFFER_MODE_ZFB_ONLY, 691 FRAME_BUFFER_MODE_MIXED_ZFB_AND_LOCAL, 692 } ; 693 694 struct dchub_init_data { 695 int64_t zfb_phys_addr_base; 696 int64_t zfb_mc_base_addr; 697 uint64_t zfb_size_in_byte; 698 enum frame_buffer_mode fb_mode; 699 bool dchub_initialzied; 700 bool dchub_info_valid; 701 }; 702 703 struct dc_init_data { 704 struct hw_asic_id asic_id; 705 void *driver; /* ctx */ 706 struct cgs_device *cgs_device; 707 struct dc_bounding_box_overrides bb_overrides; 708 709 int num_virtual_links; 710 /* 711 * If 'vbios_override' not NULL, it will be called instead 712 * of the real VBIOS. Intended use is Diagnostics on FPGA. 713 */ 714 struct dc_bios *vbios_override; 715 enum dce_environment dce_environment; 716 717 struct dmub_offload_funcs *dmub_if; 718 struct dc_reg_helper_state *dmub_offload; 719 720 struct dc_config flags; 721 uint64_t log_mask; 722 723 struct dpcd_vendor_signature vendor_signature; 724 #if defined(CONFIG_DRM_AMD_DC_DCN) 725 bool force_smu_not_present; 726 #endif 727 }; 728 729 struct dc_callback_init { 730 #ifdef CONFIG_DRM_AMD_DC_HDCP 731 struct cp_psp cp_psp; 732 #else 733 uint8_t reserved; 734 #endif 735 }; 736 737 struct dc *dc_create(const struct dc_init_data *init_params); 738 void dc_hardware_init(struct dc *dc); 739 740 int dc_get_vmid_use_vector(struct dc *dc); 741 void dc_setup_vm_context(struct dc *dc, struct dc_virtual_addr_space_config *va_config, int vmid); 742 /* Returns the number of vmids supported */ 743 int dc_setup_system_context(struct dc *dc, struct dc_phy_addr_space_config *pa_config); 744 void dc_init_callbacks(struct dc *dc, 745 const struct dc_callback_init *init_params); 746 void dc_deinit_callbacks(struct dc *dc); 747 void dc_destroy(struct dc **dc); 748 749 /******************************************************************************* 750 * Surface Interfaces 751 ******************************************************************************/ 752 753 enum { 754 TRANSFER_FUNC_POINTS = 1025 755 }; 756 757 struct dc_hdr_static_metadata { 758 /* display chromaticities and white point in units of 0.00001 */ 759 unsigned int chromaticity_green_x; 760 unsigned int chromaticity_green_y; 761 unsigned int chromaticity_blue_x; 762 unsigned int chromaticity_blue_y; 763 unsigned int chromaticity_red_x; 764 unsigned int chromaticity_red_y; 765 unsigned int chromaticity_white_point_x; 766 unsigned int chromaticity_white_point_y; 767 768 uint32_t min_luminance; 769 uint32_t max_luminance; 770 uint32_t maximum_content_light_level; 771 uint32_t maximum_frame_average_light_level; 772 }; 773 774 enum dc_transfer_func_type { 775 TF_TYPE_PREDEFINED, 776 TF_TYPE_DISTRIBUTED_POINTS, 777 TF_TYPE_BYPASS, 778 TF_TYPE_HWPWL 779 }; 780 781 struct dc_transfer_func_distributed_points { 782 struct fixed31_32 red[TRANSFER_FUNC_POINTS]; 783 struct fixed31_32 green[TRANSFER_FUNC_POINTS]; 784 struct fixed31_32 blue[TRANSFER_FUNC_POINTS]; 785 786 uint16_t end_exponent; 787 uint16_t x_point_at_y1_red; 788 uint16_t x_point_at_y1_green; 789 uint16_t x_point_at_y1_blue; 790 }; 791 792 enum dc_transfer_func_predefined { 793 TRANSFER_FUNCTION_SRGB, 794 TRANSFER_FUNCTION_BT709, 795 TRANSFER_FUNCTION_PQ, 796 TRANSFER_FUNCTION_LINEAR, 797 TRANSFER_FUNCTION_UNITY, 798 TRANSFER_FUNCTION_HLG, 799 TRANSFER_FUNCTION_HLG12, 800 TRANSFER_FUNCTION_GAMMA22, 801 TRANSFER_FUNCTION_GAMMA24, 802 TRANSFER_FUNCTION_GAMMA26 803 }; 804 805 806 struct dc_transfer_func { 807 struct kref refcount; 808 enum dc_transfer_func_type type; 809 enum dc_transfer_func_predefined tf; 810 /* FP16 1.0 reference level in nits, default is 80 nits, only for PQ*/ 811 uint32_t sdr_ref_white_level; 812 union { 813 struct pwl_params pwl; 814 struct dc_transfer_func_distributed_points tf_pts; 815 }; 816 }; 817 818 819 union dc_3dlut_state { 820 struct { 821 uint32_t initialized:1; /*if 3dlut is went through color module for initialization */ 822 uint32_t rmu_idx_valid:1; /*if mux settings are valid*/ 823 uint32_t rmu_mux_num:3; /*index of mux to use*/ 824 uint32_t mpc_rmu0_mux:4; /*select mpcc on mux, one of the following : mpcc0, mpcc1, mpcc2, mpcc3*/ 825 uint32_t mpc_rmu1_mux:4; 826 uint32_t mpc_rmu2_mux:4; 827 uint32_t reserved:15; 828 } bits; 829 uint32_t raw; 830 }; 831 832 833 struct dc_3dlut { 834 struct kref refcount; 835 struct tetrahedral_params lut_3d; 836 struct fixed31_32 hdr_multiplier; 837 union dc_3dlut_state state; 838 }; 839 /* 840 * This structure is filled in by dc_surface_get_status and contains 841 * the last requested address and the currently active address so the called 842 * can determine if there are any outstanding flips 843 */ 844 struct dc_plane_status { 845 struct dc_plane_address requested_address; 846 struct dc_plane_address current_address; 847 bool is_flip_pending; 848 bool is_right_eye; 849 }; 850 851 union surface_update_flags { 852 853 struct { 854 uint32_t addr_update:1; 855 /* Medium updates */ 856 uint32_t dcc_change:1; 857 uint32_t color_space_change:1; 858 uint32_t horizontal_mirror_change:1; 859 uint32_t per_pixel_alpha_change:1; 860 uint32_t global_alpha_change:1; 861 uint32_t hdr_mult:1; 862 uint32_t rotation_change:1; 863 uint32_t swizzle_change:1; 864 uint32_t scaling_change:1; 865 uint32_t position_change:1; 866 uint32_t in_transfer_func_change:1; 867 uint32_t input_csc_change:1; 868 uint32_t coeff_reduction_change:1; 869 uint32_t output_tf_change:1; 870 uint32_t pixel_format_change:1; 871 uint32_t plane_size_change:1; 872 uint32_t gamut_remap_change:1; 873 874 /* Full updates */ 875 uint32_t new_plane:1; 876 uint32_t bpp_change:1; 877 uint32_t gamma_change:1; 878 uint32_t bandwidth_change:1; 879 uint32_t clock_change:1; 880 uint32_t stereo_format_change:1; 881 uint32_t full_update:1; 882 } bits; 883 884 uint32_t raw; 885 }; 886 887 struct dc_plane_state { 888 struct dc_plane_address address; 889 struct dc_plane_flip_time time; 890 bool triplebuffer_flips; 891 struct scaling_taps scaling_quality; 892 struct rect src_rect; 893 struct rect dst_rect; 894 struct rect clip_rect; 895 896 struct plane_size plane_size; 897 union dc_tiling_info tiling_info; 898 899 struct dc_plane_dcc_param dcc; 900 901 struct dc_gamma *gamma_correction; 902 struct dc_transfer_func *in_transfer_func; 903 struct dc_bias_and_scale *bias_and_scale; 904 struct dc_csc_transform input_csc_color_matrix; 905 struct fixed31_32 coeff_reduction_factor; 906 struct fixed31_32 hdr_mult; 907 struct colorspace_transform gamut_remap_matrix; 908 909 // TODO: No longer used, remove 910 struct dc_hdr_static_metadata hdr_static_ctx; 911 912 enum dc_color_space color_space; 913 914 struct dc_3dlut *lut3d_func; 915 struct dc_transfer_func *in_shaper_func; 916 struct dc_transfer_func *blend_tf; 917 918 #if defined(CONFIG_DRM_AMD_DC_DCN) 919 struct dc_transfer_func *gamcor_tf; 920 #endif 921 enum surface_pixel_format format; 922 enum dc_rotation_angle rotation; 923 enum plane_stereo_format stereo_format; 924 925 bool is_tiling_rotated; 926 bool per_pixel_alpha; 927 bool global_alpha; 928 int global_alpha_value; 929 bool visible; 930 bool flip_immediate; 931 bool horizontal_mirror; 932 int layer_index; 933 934 union surface_update_flags update_flags; 935 bool flip_int_enabled; 936 bool skip_manual_trigger; 937 938 /* private to DC core */ 939 struct dc_plane_status status; 940 struct dc_context *ctx; 941 942 /* HACK: Workaround for forcing full reprogramming under some conditions */ 943 bool force_full_update; 944 945 /* private to dc_surface.c */ 946 enum dc_irq_source irq_source; 947 struct kref refcount; 948 }; 949 950 struct dc_plane_info { 951 struct plane_size plane_size; 952 union dc_tiling_info tiling_info; 953 struct dc_plane_dcc_param dcc; 954 enum surface_pixel_format format; 955 enum dc_rotation_angle rotation; 956 enum plane_stereo_format stereo_format; 957 enum dc_color_space color_space; 958 bool horizontal_mirror; 959 bool visible; 960 bool per_pixel_alpha; 961 bool global_alpha; 962 int global_alpha_value; 963 bool input_csc_enabled; 964 int layer_index; 965 }; 966 967 struct dc_scaling_info { 968 struct rect src_rect; 969 struct rect dst_rect; 970 struct rect clip_rect; 971 struct scaling_taps scaling_quality; 972 }; 973 974 struct dc_surface_update { 975 struct dc_plane_state *surface; 976 977 /* isr safe update parameters. null means no updates */ 978 const struct dc_flip_addrs *flip_addr; 979 const struct dc_plane_info *plane_info; 980 const struct dc_scaling_info *scaling_info; 981 struct fixed31_32 hdr_mult; 982 /* following updates require alloc/sleep/spin that is not isr safe, 983 * null means no updates 984 */ 985 const struct dc_gamma *gamma; 986 const struct dc_transfer_func *in_transfer_func; 987 988 const struct dc_csc_transform *input_csc_color_matrix; 989 const struct fixed31_32 *coeff_reduction_factor; 990 const struct dc_transfer_func *func_shaper; 991 const struct dc_3dlut *lut3d_func; 992 const struct dc_transfer_func *blend_tf; 993 const struct colorspace_transform *gamut_remap_matrix; 994 }; 995 996 /* 997 * Create a new surface with default parameters; 998 */ 999 struct dc_plane_state *dc_create_plane_state(struct dc *dc); 1000 const struct dc_plane_status *dc_plane_get_status( 1001 const struct dc_plane_state *plane_state); 1002 1003 void dc_plane_state_retain(struct dc_plane_state *plane_state); 1004 void dc_plane_state_release(struct dc_plane_state *plane_state); 1005 1006 void dc_gamma_retain(struct dc_gamma *dc_gamma); 1007 void dc_gamma_release(struct dc_gamma **dc_gamma); 1008 struct dc_gamma *dc_create_gamma(void); 1009 1010 void dc_transfer_func_retain(struct dc_transfer_func *dc_tf); 1011 void dc_transfer_func_release(struct dc_transfer_func *dc_tf); 1012 struct dc_transfer_func *dc_create_transfer_func(void); 1013 1014 struct dc_3dlut *dc_create_3dlut_func(void); 1015 void dc_3dlut_func_release(struct dc_3dlut *lut); 1016 void dc_3dlut_func_retain(struct dc_3dlut *lut); 1017 /* 1018 * This structure holds a surface address. There could be multiple addresses 1019 * in cases such as Stereo 3D, Planar YUV, etc. Other per-flip attributes such 1020 * as frame durations and DCC format can also be set. 1021 */ 1022 struct dc_flip_addrs { 1023 struct dc_plane_address address; 1024 unsigned int flip_timestamp_in_us; 1025 bool flip_immediate; 1026 /* TODO: add flip duration for FreeSync */ 1027 bool triplebuffer_flips; 1028 }; 1029 1030 void dc_post_update_surfaces_to_stream( 1031 struct dc *dc); 1032 1033 #include "dc_stream.h" 1034 1035 /* 1036 * Structure to store surface/stream associations for validation 1037 */ 1038 struct dc_validation_set { 1039 struct dc_stream_state *stream; 1040 struct dc_plane_state *plane_states[MAX_SURFACES]; 1041 uint8_t plane_count; 1042 }; 1043 1044 bool dc_validate_seamless_boot_timing(const struct dc *dc, 1045 const struct dc_sink *sink, 1046 struct dc_crtc_timing *crtc_timing); 1047 1048 enum dc_status dc_validate_plane(struct dc *dc, const struct dc_plane_state *plane_state); 1049 1050 void get_clock_requirements_for_state(struct dc_state *state, struct AsicStateEx *info); 1051 1052 bool dc_set_generic_gpio_for_stereo(bool enable, 1053 struct gpio_service *gpio_service); 1054 1055 /* 1056 * fast_validate: we return after determining if we can support the new state, 1057 * but before we populate the programming info 1058 */ 1059 enum dc_status dc_validate_global_state( 1060 struct dc *dc, 1061 struct dc_state *new_ctx, 1062 bool fast_validate); 1063 1064 1065 void dc_resource_state_construct( 1066 const struct dc *dc, 1067 struct dc_state *dst_ctx); 1068 1069 #if defined(CONFIG_DRM_AMD_DC_DCN) 1070 bool dc_acquire_release_mpc_3dlut( 1071 struct dc *dc, bool acquire, 1072 struct dc_stream_state *stream, 1073 struct dc_3dlut **lut, 1074 struct dc_transfer_func **shaper); 1075 #endif 1076 1077 void dc_resource_state_copy_construct( 1078 const struct dc_state *src_ctx, 1079 struct dc_state *dst_ctx); 1080 1081 void dc_resource_state_copy_construct_current( 1082 const struct dc *dc, 1083 struct dc_state *dst_ctx); 1084 1085 void dc_resource_state_destruct(struct dc_state *context); 1086 1087 bool dc_resource_is_dsc_encoding_supported(const struct dc *dc); 1088 1089 /* 1090 * TODO update to make it about validation sets 1091 * Set up streams and links associated to drive sinks 1092 * The streams parameter is an absolute set of all active streams. 1093 * 1094 * After this call: 1095 * Phy, Encoder, Timing Generator are programmed and enabled. 1096 * New streams are enabled with blank stream; no memory read. 1097 */ 1098 bool dc_commit_state(struct dc *dc, struct dc_state *context); 1099 1100 struct dc_state *dc_create_state(struct dc *dc); 1101 struct dc_state *dc_copy_state(struct dc_state *src_ctx); 1102 void dc_retain_state(struct dc_state *context); 1103 void dc_release_state(struct dc_state *context); 1104 1105 /******************************************************************************* 1106 * Link Interfaces 1107 ******************************************************************************/ 1108 1109 struct dpcd_caps { 1110 union dpcd_rev dpcd_rev; 1111 union max_lane_count max_ln_count; 1112 union max_down_spread max_down_spread; 1113 union dprx_feature dprx_feature; 1114 1115 /* valid only for eDP v1.4 or higher*/ 1116 uint8_t edp_supported_link_rates_count; 1117 enum dc_link_rate edp_supported_link_rates[8]; 1118 1119 /* dongle type (DP converter, CV smart dongle) */ 1120 enum display_dongle_type dongle_type; 1121 /* branch device or sink device */ 1122 bool is_branch_dev; 1123 /* Dongle's downstream count. */ 1124 union sink_count sink_count; 1125 /* If dongle_type == DISPLAY_DONGLE_DP_HDMI_CONVERTER, 1126 indicates 'Frame Sequential-to-lllFrame Pack' conversion capability.*/ 1127 struct dc_dongle_caps dongle_caps; 1128 1129 uint32_t sink_dev_id; 1130 int8_t sink_dev_id_str[6]; 1131 int8_t sink_hw_revision; 1132 int8_t sink_fw_revision[2]; 1133 1134 uint32_t branch_dev_id; 1135 int8_t branch_dev_name[6]; 1136 int8_t branch_hw_revision; 1137 int8_t branch_fw_revision[2]; 1138 1139 bool allow_invalid_MSA_timing_param; 1140 bool panel_mode_edp; 1141 bool dpcd_display_control_capable; 1142 bool ext_receiver_cap_field_present; 1143 bool dynamic_backlight_capable_edp; 1144 union dpcd_fec_capability fec_cap; 1145 struct dpcd_dsc_capabilities dsc_caps; 1146 struct dc_lttpr_caps lttpr_caps; 1147 struct psr_caps psr_caps; 1148 1149 }; 1150 1151 union dpcd_sink_ext_caps { 1152 struct { 1153 /* 0 - Sink supports backlight adjust via PWM during SDR/HDR mode 1154 * 1 - Sink supports backlight adjust via AUX during SDR/HDR mode. 1155 */ 1156 uint8_t sdr_aux_backlight_control : 1; 1157 uint8_t hdr_aux_backlight_control : 1; 1158 uint8_t reserved_1 : 2; 1159 uint8_t oled : 1; 1160 uint8_t reserved : 3; 1161 } bits; 1162 uint8_t raw; 1163 }; 1164 1165 #if defined(CONFIG_DRM_AMD_DC_HDCP) 1166 union hdcp_rx_caps { 1167 struct { 1168 uint8_t version; 1169 uint8_t reserved; 1170 struct { 1171 uint8_t repeater : 1; 1172 uint8_t hdcp_capable : 1; 1173 uint8_t reserved : 6; 1174 } byte0; 1175 } fields; 1176 uint8_t raw[3]; 1177 }; 1178 1179 union hdcp_bcaps { 1180 struct { 1181 uint8_t HDCP_CAPABLE:1; 1182 uint8_t REPEATER:1; 1183 uint8_t RESERVED:6; 1184 } bits; 1185 uint8_t raw; 1186 }; 1187 1188 struct hdcp_caps { 1189 union hdcp_rx_caps rx_caps; 1190 union hdcp_bcaps bcaps; 1191 }; 1192 #endif 1193 1194 #include "dc_link.h" 1195 1196 #if defined(CONFIG_DRM_AMD_DC_DCN) 1197 uint32_t dc_get_opp_for_plane(struct dc *dc, struct dc_plane_state *plane); 1198 1199 #endif 1200 /******************************************************************************* 1201 * Sink Interfaces - A sink corresponds to a display output device 1202 ******************************************************************************/ 1203 1204 struct dc_container_id { 1205 // 128bit GUID in binary form 1206 unsigned char guid[16]; 1207 // 8 byte port ID -> ELD.PortID 1208 unsigned int portId[2]; 1209 // 128bit GUID in binary formufacturer name -> ELD.ManufacturerName 1210 unsigned short manufacturerName; 1211 // 2 byte product code -> ELD.ProductCode 1212 unsigned short productCode; 1213 }; 1214 1215 1216 struct dc_sink_dsc_caps { 1217 // 'true' if these are virtual DPCD's DSC caps (immediately upstream of sink in MST topology), 1218 // 'false' if they are sink's DSC caps 1219 bool is_virtual_dpcd_dsc; 1220 struct dsc_dec_dpcd_caps dsc_dec_caps; 1221 }; 1222 1223 struct dc_sink_fec_caps { 1224 bool is_rx_fec_supported; 1225 bool is_topology_fec_supported; 1226 }; 1227 1228 /* 1229 * The sink structure contains EDID and other display device properties 1230 */ 1231 struct dc_sink { 1232 enum signal_type sink_signal; 1233 struct dc_edid dc_edid; /* raw edid */ 1234 struct dc_edid_caps edid_caps; /* parse display caps */ 1235 struct dc_container_id *dc_container_id; 1236 uint32_t dongle_max_pix_clk; 1237 void *priv; 1238 struct stereo_3d_features features_3d[TIMING_3D_FORMAT_MAX]; 1239 bool converter_disable_audio; 1240 1241 struct dc_sink_dsc_caps dsc_caps; 1242 struct dc_sink_fec_caps fec_caps; 1243 1244 bool is_vsc_sdp_colorimetry_supported; 1245 1246 /* private to DC core */ 1247 struct dc_link *link; 1248 struct dc_context *ctx; 1249 1250 uint32_t sink_id; 1251 1252 /* private to dc_sink.c */ 1253 // refcount must be the last member in dc_sink, since we want the 1254 // sink structure to be logically cloneable up to (but not including) 1255 // refcount 1256 struct kref refcount; 1257 }; 1258 1259 void dc_sink_retain(struct dc_sink *sink); 1260 void dc_sink_release(struct dc_sink *sink); 1261 1262 struct dc_sink_init_data { 1263 enum signal_type sink_signal; 1264 struct dc_link *link; 1265 uint32_t dongle_max_pix_clk; 1266 bool converter_disable_audio; 1267 }; 1268 1269 struct dc_sink *dc_sink_create(const struct dc_sink_init_data *init_params); 1270 1271 /* Newer interfaces */ 1272 struct dc_cursor { 1273 struct dc_plane_address address; 1274 struct dc_cursor_attributes attributes; 1275 }; 1276 1277 1278 /******************************************************************************* 1279 * Interrupt interfaces 1280 ******************************************************************************/ 1281 enum dc_irq_source dc_interrupt_to_irq_source( 1282 struct dc *dc, 1283 uint32_t src_id, 1284 uint32_t ext_id); 1285 bool dc_interrupt_set(struct dc *dc, enum dc_irq_source src, bool enable); 1286 void dc_interrupt_ack(struct dc *dc, enum dc_irq_source src); 1287 enum dc_irq_source dc_get_hpd_irq_source_at_index( 1288 struct dc *dc, uint32_t link_index); 1289 1290 /******************************************************************************* 1291 * Power Interfaces 1292 ******************************************************************************/ 1293 1294 void dc_set_power_state( 1295 struct dc *dc, 1296 enum dc_acpi_cm_power_state power_state); 1297 void dc_resume(struct dc *dc); 1298 1299 void dc_power_down_on_boot(struct dc *dc); 1300 1301 #if defined(CONFIG_DRM_AMD_DC_HDCP) 1302 /* 1303 * HDCP Interfaces 1304 */ 1305 enum hdcp_message_status dc_process_hdcp_msg( 1306 enum signal_type signal, 1307 struct dc_link *link, 1308 struct hdcp_protection_message *message_info); 1309 #endif 1310 bool dc_is_dmcu_initialized(struct dc *dc); 1311 1312 enum dc_status dc_set_clock(struct dc *dc, enum dc_clock_type clock_type, uint32_t clk_khz, uint32_t stepping); 1313 void dc_get_clock(struct dc *dc, enum dc_clock_type clock_type, struct dc_clock_config *clock_cfg); 1314 #if defined(CONFIG_DRM_AMD_DC_DCN) 1315 1316 bool dc_is_plane_eligible_for_idle_optimizations(struct dc *dc, struct dc_plane_state *plane, 1317 struct dc_cursor_attributes *cursor_attr); 1318 1319 void dc_allow_idle_optimizations(struct dc *dc, bool allow); 1320 1321 /* 1322 * blank all streams, and set min and max memory clock to 1323 * lowest and highest DPM level, respectively 1324 */ 1325 void dc_unlock_memory_clock_frequency(struct dc *dc); 1326 1327 /* 1328 * set min memory clock to the min required for current mode, 1329 * max to maxDPM, and unblank streams 1330 */ 1331 void dc_lock_memory_clock_frequency(struct dc *dc); 1332 1333 /* cleanup on driver unload */ 1334 void dc_hardware_release(struct dc *dc); 1335 1336 #endif 1337 1338 bool dc_set_psr_allow_active(struct dc *dc, bool enable); 1339 #if defined(CONFIG_DRM_AMD_DC_DCN) 1340 void dc_z10_restore(struct dc *dc); 1341 void dc_z10_save_init(struct dc *dc); 1342 #endif 1343 1344 bool dc_enable_dmub_notifications(struct dc *dc); 1345 1346 bool dc_process_dmub_aux_transfer_async(struct dc *dc, 1347 uint32_t link_index, 1348 struct aux_payload *payload); 1349 1350 /******************************************************************************* 1351 * DSC Interfaces 1352 ******************************************************************************/ 1353 #include "dc_dsc.h" 1354 1355 /******************************************************************************* 1356 * Disable acc mode Interfaces 1357 ******************************************************************************/ 1358 void dc_disable_accelerated_mode(struct dc *dc); 1359 1360 #endif /* DC_INTERFACE_H_ */ 1361