1 /* 2 * Copyright 2012-14 Advanced Micro Devices, Inc. 3 * 4 * Permission is hereby granted, free of charge, to any person obtaining a 5 * copy of this software and associated documentation files (the "Software"), 6 * to deal in the Software without restriction, including without limitation 7 * the rights to use, copy, modify, merge, publish, distribute, sublicense, 8 * and/or sell copies of the Software, and to permit persons to whom the 9 * Software is furnished to do so, subject to the following conditions: 10 * 11 * The above copyright notice and this permission notice shall be included in 12 * all copies or substantial portions of the Software. 13 * 14 * THE SOFTWARE IS PROVIDED "AS IS", WITHOUT WARRANTY OF ANY KIND, EXPRESS OR 15 * IMPLIED, INCLUDING BUT NOT LIMITED TO THE WARRANTIES OF MERCHANTABILITY, 16 * FITNESS FOR A PARTICULAR PURPOSE AND NONINFRINGEMENT. IN NO EVENT SHALL 17 * THE COPYRIGHT HOLDER(S) OR AUTHOR(S) BE LIABLE FOR ANY CLAIM, DAMAGES OR 18 * OTHER LIABILITY, WHETHER IN AN ACTION OF CONTRACT, TORT OR OTHERWISE, 19 * ARISING FROM, OUT OF OR IN CONNECTION WITH THE SOFTWARE OR THE USE OR 20 * OTHER DEALINGS IN THE SOFTWARE. 21 * 22 * Authors: AMD 23 * 24 */ 25 26 #ifndef DC_INTERFACE_H_ 27 #define DC_INTERFACE_H_ 28 29 #include "dc_types.h" 30 #include "grph_object_defs.h" 31 #include "logger_types.h" 32 #include "gpio_types.h" 33 #include "link_service_types.h" 34 #include "grph_object_ctrl_defs.h" 35 #include <inc/hw/opp.h> 36 37 #include "inc/hw_sequencer.h" 38 #include "inc/compressor.h" 39 #include "inc/hw/dmcu.h" 40 #include "dml/display_mode_lib.h" 41 42 #define DC_VER "3.2.60" 43 44 #define MAX_SURFACES 3 45 #define MAX_PLANES 6 46 #define MAX_STREAMS 6 47 #define MAX_SINKS_PER_LINK 4 48 49 /******************************************************************************* 50 * Display Core Interfaces 51 ******************************************************************************/ 52 struct dc_versions { 53 const char *dc_ver; 54 struct dmcu_version dmcu_version; 55 }; 56 57 enum dc_plane_type { 58 DC_PLANE_TYPE_INVALID, 59 DC_PLANE_TYPE_DCE_RGB, 60 DC_PLANE_TYPE_DCE_UNDERLAY, 61 DC_PLANE_TYPE_DCN_UNIVERSAL, 62 }; 63 64 struct dc_plane_cap { 65 enum dc_plane_type type; 66 uint32_t blends_with_above : 1; 67 uint32_t blends_with_below : 1; 68 uint32_t per_pixel_alpha : 1; 69 struct { 70 uint32_t argb8888 : 1; 71 uint32_t nv12 : 1; 72 uint32_t fp16 : 1; 73 uint32_t p010 : 1; 74 uint32_t ayuv : 1; 75 } pixel_format_support; 76 // max upscaling factor x1000 77 // upscaling factors are always >= 1 78 // for example, 1080p -> 8K is 4.0, or 4000 raw value 79 struct { 80 uint32_t argb8888; 81 uint32_t nv12; 82 uint32_t fp16; 83 } max_upscale_factor; 84 // max downscale factor x1000 85 // downscale factors are always <= 1 86 // for example, 8K -> 1080p is 0.25, or 250 raw value 87 struct { 88 uint32_t argb8888; 89 uint32_t nv12; 90 uint32_t fp16; 91 } max_downscale_factor; 92 }; 93 94 struct dc_caps { 95 uint32_t max_streams; 96 uint32_t max_links; 97 uint32_t max_audios; 98 uint32_t max_slave_planes; 99 uint32_t max_planes; 100 uint32_t max_downscale_ratio; 101 uint32_t i2c_speed_in_khz; 102 uint32_t dmdata_alloc_size; 103 unsigned int max_cursor_size; 104 unsigned int max_video_width; 105 int linear_pitch_alignment; 106 bool dcc_const_color; 107 bool dynamic_audio; 108 bool is_apu; 109 bool dual_link_dvi; 110 bool post_blend_color_processing; 111 bool force_dp_tps4_for_cp2520; 112 bool disable_dp_clk_share; 113 bool psp_setup_panel_mode; 114 bool extended_aux_timeout_support; 115 bool dmcub_support; 116 bool hw_3d_lut; 117 struct dc_plane_cap planes[MAX_PLANES]; 118 }; 119 120 struct dc_bug_wa { 121 bool no_connect_phy_config; 122 bool dedcn20_305_wa; 123 bool skip_clock_update; 124 }; 125 126 struct dc_dcc_surface_param { 127 struct dc_size surface_size; 128 enum surface_pixel_format format; 129 enum swizzle_mode_values swizzle_mode; 130 enum dc_scan_direction scan; 131 }; 132 133 struct dc_dcc_setting { 134 unsigned int max_compressed_blk_size; 135 unsigned int max_uncompressed_blk_size; 136 bool independent_64b_blks; 137 }; 138 139 struct dc_surface_dcc_cap { 140 union { 141 struct { 142 struct dc_dcc_setting rgb; 143 } grph; 144 145 struct { 146 struct dc_dcc_setting luma; 147 struct dc_dcc_setting chroma; 148 } video; 149 }; 150 151 bool capable; 152 bool const_color_support; 153 }; 154 155 struct dc_static_screen_events { 156 bool force_trigger; 157 bool cursor_update; 158 bool surface_update; 159 bool overlay_update; 160 }; 161 162 163 /* Surface update type is used by dc_update_surfaces_and_stream 164 * The update type is determined at the very beginning of the function based 165 * on parameters passed in and decides how much programming (or updating) is 166 * going to be done during the call. 167 * 168 * UPDATE_TYPE_FAST is used for really fast updates that do not require much 169 * logical calculations or hardware register programming. This update MUST be 170 * ISR safe on windows. Currently fast update will only be used to flip surface 171 * address. 172 * 173 * UPDATE_TYPE_MED is used for slower updates which require significant hw 174 * re-programming however do not affect bandwidth consumption or clock 175 * requirements. At present, this is the level at which front end updates 176 * that do not require us to run bw_calcs happen. These are in/out transfer func 177 * updates, viewport offset changes, recout size changes and pixel depth changes. 178 * This update can be done at ISR, but we want to minimize how often this happens. 179 * 180 * UPDATE_TYPE_FULL is slow. Really slow. This requires us to recalculate our 181 * bandwidth and clocks, possibly rearrange some pipes and reprogram anything front 182 * end related. Any time viewport dimensions, recout dimensions, scaling ratios or 183 * gamma need to be adjusted or pipe needs to be turned on (or disconnected) we do 184 * a full update. This cannot be done at ISR level and should be a rare event. 185 * Unless someone is stress testing mpo enter/exit, playing with colour or adjusting 186 * underscan we don't expect to see this call at all. 187 */ 188 189 enum surface_update_type { 190 UPDATE_TYPE_FAST, /* super fast, safe to execute in isr */ 191 UPDATE_TYPE_MED, /* ISR safe, most of programming needed, no bw/clk change*/ 192 UPDATE_TYPE_FULL, /* may need to shuffle resources */ 193 }; 194 195 /* Forward declaration*/ 196 struct dc; 197 struct dc_plane_state; 198 struct dc_state; 199 200 201 struct dc_cap_funcs { 202 bool (*get_dcc_compression_cap)(const struct dc *dc, 203 const struct dc_dcc_surface_param *input, 204 struct dc_surface_dcc_cap *output); 205 }; 206 207 struct link_training_settings; 208 209 210 /* Structure to hold configuration flags set by dm at dc creation. */ 211 struct dc_config { 212 bool gpu_vm_support; 213 bool disable_disp_pll_sharing; 214 bool fbc_support; 215 bool optimize_edp_link_rate; 216 bool disable_fractional_pwm; 217 bool allow_seamless_boot_optimization; 218 bool power_down_display_on_boot; 219 bool edp_not_connected; 220 bool force_enum_edp; 221 bool forced_clocks; 222 bool disable_extended_timeout_support; // Used to disable extended timeout and lttpr feature as well 223 bool multi_mon_pp_mclk_switch; 224 }; 225 226 enum visual_confirm { 227 VISUAL_CONFIRM_DISABLE = 0, 228 VISUAL_CONFIRM_SURFACE = 1, 229 VISUAL_CONFIRM_HDR = 2, 230 VISUAL_CONFIRM_MPCTREE = 4, 231 }; 232 233 enum dcc_option { 234 DCC_ENABLE = 0, 235 DCC_DISABLE = 1, 236 DCC_HALF_REQ_DISALBE = 2, 237 }; 238 239 enum pipe_split_policy { 240 MPC_SPLIT_DYNAMIC = 0, 241 MPC_SPLIT_AVOID = 1, 242 MPC_SPLIT_AVOID_MULT_DISP = 2, 243 }; 244 245 enum wm_report_mode { 246 WM_REPORT_DEFAULT = 0, 247 WM_REPORT_OVERRIDE = 1, 248 }; 249 enum dtm_pstate{ 250 dtm_level_p0 = 0,/*highest voltage*/ 251 dtm_level_p1, 252 dtm_level_p2, 253 dtm_level_p3, 254 dtm_level_p4,/*when active_display_count = 0*/ 255 }; 256 257 enum dcn_pwr_state { 258 DCN_PWR_STATE_UNKNOWN = -1, 259 DCN_PWR_STATE_MISSION_MODE = 0, 260 DCN_PWR_STATE_LOW_POWER = 3, 261 }; 262 263 /* 264 * For any clocks that may differ per pipe 265 * only the max is stored in this structure 266 */ 267 struct dc_clocks { 268 int dispclk_khz; 269 int dppclk_khz; 270 int dcfclk_khz; 271 int socclk_khz; 272 int dcfclk_deep_sleep_khz; 273 int fclk_khz; 274 int phyclk_khz; 275 int dramclk_khz; 276 bool p_state_change_support; 277 enum dcn_pwr_state pwr_state; 278 /* 279 * Elements below are not compared for the purposes of 280 * optimization required 281 */ 282 bool prev_p_state_change_support; 283 enum dtm_pstate dtm_level; 284 int max_supported_dppclk_khz; 285 int max_supported_dispclk_khz; 286 int bw_dppclk_khz; /*a copy of dppclk_khz*/ 287 int bw_dispclk_khz; 288 }; 289 290 struct dc_bw_validation_profile { 291 bool enable; 292 293 unsigned long long total_ticks; 294 unsigned long long voltage_level_ticks; 295 unsigned long long watermark_ticks; 296 unsigned long long rq_dlg_ticks; 297 298 unsigned long long total_count; 299 unsigned long long skip_fast_count; 300 unsigned long long skip_pass_count; 301 unsigned long long skip_fail_count; 302 }; 303 304 #define BW_VAL_TRACE_SETUP() \ 305 unsigned long long end_tick = 0; \ 306 unsigned long long voltage_level_tick = 0; \ 307 unsigned long long watermark_tick = 0; \ 308 unsigned long long start_tick = dc->debug.bw_val_profile.enable ? \ 309 dm_get_timestamp(dc->ctx) : 0 310 311 #define BW_VAL_TRACE_COUNT() \ 312 if (dc->debug.bw_val_profile.enable) \ 313 dc->debug.bw_val_profile.total_count++ 314 315 #define BW_VAL_TRACE_SKIP(status) \ 316 if (dc->debug.bw_val_profile.enable) { \ 317 if (!voltage_level_tick) \ 318 voltage_level_tick = dm_get_timestamp(dc->ctx); \ 319 dc->debug.bw_val_profile.skip_ ## status ## _count++; \ 320 } 321 322 #define BW_VAL_TRACE_END_VOLTAGE_LEVEL() \ 323 if (dc->debug.bw_val_profile.enable) \ 324 voltage_level_tick = dm_get_timestamp(dc->ctx) 325 326 #define BW_VAL_TRACE_END_WATERMARKS() \ 327 if (dc->debug.bw_val_profile.enable) \ 328 watermark_tick = dm_get_timestamp(dc->ctx) 329 330 #define BW_VAL_TRACE_FINISH() \ 331 if (dc->debug.bw_val_profile.enable) { \ 332 end_tick = dm_get_timestamp(dc->ctx); \ 333 dc->debug.bw_val_profile.total_ticks += end_tick - start_tick; \ 334 dc->debug.bw_val_profile.voltage_level_ticks += voltage_level_tick - start_tick; \ 335 if (watermark_tick) { \ 336 dc->debug.bw_val_profile.watermark_ticks += watermark_tick - voltage_level_tick; \ 337 dc->debug.bw_val_profile.rq_dlg_ticks += end_tick - watermark_tick; \ 338 } \ 339 } 340 341 struct dc_debug_options { 342 enum visual_confirm visual_confirm; 343 bool sanity_checks; 344 bool max_disp_clk; 345 bool surface_trace; 346 bool timing_trace; 347 bool clock_trace; 348 bool validation_trace; 349 bool bandwidth_calcs_trace; 350 int max_downscale_src_width; 351 352 /* stutter efficiency related */ 353 bool disable_stutter; 354 bool use_max_lb; 355 enum dcc_option disable_dcc; 356 enum pipe_split_policy pipe_split_policy; 357 bool force_single_disp_pipe_split; 358 bool voltage_align_fclk; 359 360 bool disable_dfs_bypass; 361 bool disable_dpp_power_gate; 362 bool disable_hubp_power_gate; 363 bool disable_dsc_power_gate; 364 int dsc_min_slice_height_override; 365 bool native422_support; 366 bool disable_pplib_wm_range; 367 enum wm_report_mode pplib_wm_report_mode; 368 unsigned int min_disp_clk_khz; 369 unsigned int min_dpp_clk_khz; 370 int sr_exit_time_dpm0_ns; 371 int sr_enter_plus_exit_time_dpm0_ns; 372 int sr_exit_time_ns; 373 int sr_enter_plus_exit_time_ns; 374 int urgent_latency_ns; 375 uint32_t underflow_assert_delay_us; 376 int percent_of_ideal_drambw; 377 int dram_clock_change_latency_ns; 378 bool optimized_watermark; 379 int always_scale; 380 bool disable_pplib_clock_request; 381 bool disable_clock_gate; 382 bool disable_dmcu; 383 bool disable_psr; 384 bool force_abm_enable; 385 bool disable_stereo_support; 386 bool vsr_support; 387 bool performance_trace; 388 bool az_endpoint_mute_only; 389 bool always_use_regamma; 390 bool p010_mpo_support; 391 bool recovery_enabled; 392 bool avoid_vbios_exec_table; 393 bool scl_reset_length10; 394 bool hdmi20_disable; 395 bool skip_detection_link_training; 396 bool remove_disconnect_edp; 397 unsigned int force_odm_combine; //bit vector based on otg inst 398 unsigned int force_fclk_khz; 399 bool disable_tri_buf; 400 bool dmub_offload_enabled; 401 bool dmcub_emulation; 402 bool dmub_command_table; /* for testing only */ 403 struct dc_bw_validation_profile bw_val_profile; 404 bool disable_fec; 405 bool disable_48mhz_pwrdwn; 406 /* This forces a hard min on the DCFCLK requested to SMU/PP 407 * watermarks are not affected. 408 */ 409 unsigned int force_min_dcfclk_mhz; 410 bool disable_timing_sync; 411 bool cm_in_bypass; 412 int force_clock_mode;/*every mode change.*/ 413 414 bool nv12_iflip_vm_wa; 415 bool disable_dram_clock_change_vactive_support; 416 bool validate_dml_output; 417 }; 418 419 struct dc_debug_data { 420 uint32_t ltFailCount; 421 uint32_t i2cErrorCount; 422 uint32_t auxErrorCount; 423 }; 424 425 struct dc_phy_addr_space_config { 426 struct { 427 uint64_t start_addr; 428 uint64_t end_addr; 429 uint64_t fb_top; 430 uint64_t fb_offset; 431 uint64_t fb_base; 432 uint64_t agp_top; 433 uint64_t agp_bot; 434 uint64_t agp_base; 435 } system_aperture; 436 437 struct { 438 uint64_t page_table_start_addr; 439 uint64_t page_table_end_addr; 440 uint64_t page_table_base_addr; 441 } gart_config; 442 443 bool valid; 444 uint64_t page_table_default_page_addr; 445 }; 446 447 struct dc_virtual_addr_space_config { 448 uint64_t page_table_base_addr; 449 uint64_t page_table_start_addr; 450 uint64_t page_table_end_addr; 451 uint32_t page_table_block_size_in_bytes; 452 uint8_t page_table_depth; // 1 = 1 level, 2 = 2 level, etc. 0 = invalid 453 }; 454 455 struct dc_bounding_box_overrides { 456 int sr_exit_time_ns; 457 int sr_enter_plus_exit_time_ns; 458 int urgent_latency_ns; 459 int percent_of_ideal_drambw; 460 int dram_clock_change_latency_ns; 461 /* This forces a hard min on the DCFCLK we use 462 * for DML. Unlike the debug option for forcing 463 * DCFCLK, this override affects watermark calculations 464 */ 465 int min_dcfclk_mhz; 466 }; 467 468 struct dc_state; 469 struct resource_pool; 470 struct dce_hwseq; 471 struct gpu_info_soc_bounding_box_v1_0; 472 struct dc { 473 struct dc_versions versions; 474 struct dc_caps caps; 475 struct dc_cap_funcs cap_funcs; 476 struct dc_config config; 477 struct dc_debug_options debug; 478 struct dc_bounding_box_overrides bb_overrides; 479 struct dc_bug_wa work_arounds; 480 struct dc_context *ctx; 481 struct dc_phy_addr_space_config vm_pa_config; 482 483 uint8_t link_count; 484 struct dc_link *links[MAX_PIPES * 2]; 485 486 struct dc_state *current_state; 487 struct resource_pool *res_pool; 488 489 struct clk_mgr *clk_mgr; 490 491 /* Display Engine Clock levels */ 492 struct dm_pp_clock_levels sclk_lvls; 493 494 /* Inputs into BW and WM calculations. */ 495 struct bw_calcs_dceip *bw_dceip; 496 struct bw_calcs_vbios *bw_vbios; 497 #ifdef CONFIG_DRM_AMD_DC_DCN 498 struct dcn_soc_bounding_box *dcn_soc; 499 struct dcn_ip_params *dcn_ip; 500 struct display_mode_lib dml; 501 #endif 502 503 /* HW functions */ 504 struct hw_sequencer_funcs hwss; 505 struct dce_hwseq *hwseq; 506 507 /* Require to optimize clocks and bandwidth for added/removed planes */ 508 bool optimized_required; 509 510 /* Require to maintain clocks and bandwidth for UEFI enabled HW */ 511 bool optimize_seamless_boot; 512 513 /* FBC compressor */ 514 struct compressor *fbc_compressor; 515 516 struct dc_debug_data debug_data; 517 518 const char *build_id; 519 struct vm_helper *vm_helper; 520 const struct gpu_info_soc_bounding_box_v1_0 *soc_bounding_box; 521 }; 522 523 enum frame_buffer_mode { 524 FRAME_BUFFER_MODE_LOCAL_ONLY = 0, 525 FRAME_BUFFER_MODE_ZFB_ONLY, 526 FRAME_BUFFER_MODE_MIXED_ZFB_AND_LOCAL, 527 } ; 528 529 struct dchub_init_data { 530 int64_t zfb_phys_addr_base; 531 int64_t zfb_mc_base_addr; 532 uint64_t zfb_size_in_byte; 533 enum frame_buffer_mode fb_mode; 534 bool dchub_initialzied; 535 bool dchub_info_valid; 536 }; 537 538 struct dc_init_data { 539 struct hw_asic_id asic_id; 540 void *driver; /* ctx */ 541 struct cgs_device *cgs_device; 542 struct dc_bounding_box_overrides bb_overrides; 543 544 int num_virtual_links; 545 /* 546 * If 'vbios_override' not NULL, it will be called instead 547 * of the real VBIOS. Intended use is Diagnostics on FPGA. 548 */ 549 struct dc_bios *vbios_override; 550 enum dce_environment dce_environment; 551 552 struct dmub_offload_funcs *dmub_if; 553 struct dc_reg_helper_state *dmub_offload; 554 555 struct dc_config flags; 556 uint32_t log_mask; 557 /** 558 * gpu_info FW provided soc bounding box struct or 0 if not 559 * available in FW 560 */ 561 const struct gpu_info_soc_bounding_box_v1_0 *soc_bounding_box; 562 }; 563 564 struct dc_callback_init { 565 #ifdef CONFIG_DRM_AMD_DC_HDCP 566 struct cp_psp cp_psp; 567 #else 568 uint8_t reserved; 569 #endif 570 }; 571 572 struct dc *dc_create(const struct dc_init_data *init_params); 573 void dc_hardware_init(struct dc *dc); 574 575 int dc_get_vmid_use_vector(struct dc *dc); 576 void dc_setup_vm_context(struct dc *dc, struct dc_virtual_addr_space_config *va_config, int vmid); 577 /* Returns the number of vmids supported */ 578 int dc_setup_system_context(struct dc *dc, struct dc_phy_addr_space_config *pa_config); 579 void dc_init_callbacks(struct dc *dc, 580 const struct dc_callback_init *init_params); 581 void dc_deinit_callbacks(struct dc *dc); 582 void dc_destroy(struct dc **dc); 583 584 /******************************************************************************* 585 * Surface Interfaces 586 ******************************************************************************/ 587 588 enum { 589 TRANSFER_FUNC_POINTS = 1025 590 }; 591 592 struct dc_hdr_static_metadata { 593 /* display chromaticities and white point in units of 0.00001 */ 594 unsigned int chromaticity_green_x; 595 unsigned int chromaticity_green_y; 596 unsigned int chromaticity_blue_x; 597 unsigned int chromaticity_blue_y; 598 unsigned int chromaticity_red_x; 599 unsigned int chromaticity_red_y; 600 unsigned int chromaticity_white_point_x; 601 unsigned int chromaticity_white_point_y; 602 603 uint32_t min_luminance; 604 uint32_t max_luminance; 605 uint32_t maximum_content_light_level; 606 uint32_t maximum_frame_average_light_level; 607 }; 608 609 enum dc_transfer_func_type { 610 TF_TYPE_PREDEFINED, 611 TF_TYPE_DISTRIBUTED_POINTS, 612 TF_TYPE_BYPASS, 613 TF_TYPE_HWPWL 614 }; 615 616 struct dc_transfer_func_distributed_points { 617 struct fixed31_32 red[TRANSFER_FUNC_POINTS]; 618 struct fixed31_32 green[TRANSFER_FUNC_POINTS]; 619 struct fixed31_32 blue[TRANSFER_FUNC_POINTS]; 620 621 uint16_t end_exponent; 622 uint16_t x_point_at_y1_red; 623 uint16_t x_point_at_y1_green; 624 uint16_t x_point_at_y1_blue; 625 }; 626 627 enum dc_transfer_func_predefined { 628 TRANSFER_FUNCTION_SRGB, 629 TRANSFER_FUNCTION_BT709, 630 TRANSFER_FUNCTION_PQ, 631 TRANSFER_FUNCTION_LINEAR, 632 TRANSFER_FUNCTION_UNITY, 633 TRANSFER_FUNCTION_HLG, 634 TRANSFER_FUNCTION_HLG12, 635 TRANSFER_FUNCTION_GAMMA22, 636 TRANSFER_FUNCTION_GAMMA24, 637 TRANSFER_FUNCTION_GAMMA26 638 }; 639 640 641 struct dc_transfer_func { 642 struct kref refcount; 643 enum dc_transfer_func_type type; 644 enum dc_transfer_func_predefined tf; 645 /* FP16 1.0 reference level in nits, default is 80 nits, only for PQ*/ 646 uint32_t sdr_ref_white_level; 647 struct dc_context *ctx; 648 union { 649 struct pwl_params pwl; 650 struct dc_transfer_func_distributed_points tf_pts; 651 }; 652 }; 653 654 655 union dc_3dlut_state { 656 struct { 657 uint32_t initialized:1; /*if 3dlut is went through color module for initialization */ 658 uint32_t rmu_idx_valid:1; /*if mux settings are valid*/ 659 uint32_t rmu_mux_num:3; /*index of mux to use*/ 660 uint32_t mpc_rmu0_mux:4; /*select mpcc on mux, one of the following : mpcc0, mpcc1, mpcc2, mpcc3*/ 661 uint32_t mpc_rmu1_mux:4; 662 uint32_t mpc_rmu2_mux:4; 663 uint32_t reserved:15; 664 } bits; 665 uint32_t raw; 666 }; 667 668 669 struct dc_3dlut { 670 struct kref refcount; 671 struct tetrahedral_params lut_3d; 672 struct fixed31_32 hdr_multiplier; 673 bool initialized; /*remove after diag fix*/ 674 union dc_3dlut_state state; 675 struct dc_context *ctx; 676 }; 677 /* 678 * This structure is filled in by dc_surface_get_status and contains 679 * the last requested address and the currently active address so the called 680 * can determine if there are any outstanding flips 681 */ 682 struct dc_plane_status { 683 struct dc_plane_address requested_address; 684 struct dc_plane_address current_address; 685 bool is_flip_pending; 686 bool is_right_eye; 687 }; 688 689 union surface_update_flags { 690 691 struct { 692 uint32_t addr_update:1; 693 /* Medium updates */ 694 uint32_t dcc_change:1; 695 uint32_t color_space_change:1; 696 uint32_t horizontal_mirror_change:1; 697 uint32_t per_pixel_alpha_change:1; 698 uint32_t global_alpha_change:1; 699 uint32_t hdr_mult:1; 700 uint32_t rotation_change:1; 701 uint32_t swizzle_change:1; 702 uint32_t scaling_change:1; 703 uint32_t position_change:1; 704 uint32_t in_transfer_func_change:1; 705 uint32_t input_csc_change:1; 706 uint32_t coeff_reduction_change:1; 707 uint32_t output_tf_change:1; 708 uint32_t pixel_format_change:1; 709 uint32_t plane_size_change:1; 710 711 /* Full updates */ 712 uint32_t new_plane:1; 713 uint32_t bpp_change:1; 714 uint32_t gamma_change:1; 715 uint32_t bandwidth_change:1; 716 uint32_t clock_change:1; 717 uint32_t stereo_format_change:1; 718 uint32_t full_update:1; 719 } bits; 720 721 uint32_t raw; 722 }; 723 724 struct dc_plane_state { 725 struct dc_plane_address address; 726 struct dc_plane_flip_time time; 727 bool triplebuffer_flips; 728 struct scaling_taps scaling_quality; 729 struct rect src_rect; 730 struct rect dst_rect; 731 struct rect clip_rect; 732 733 struct plane_size plane_size; 734 union dc_tiling_info tiling_info; 735 736 struct dc_plane_dcc_param dcc; 737 738 struct dc_gamma *gamma_correction; 739 struct dc_transfer_func *in_transfer_func; 740 struct dc_bias_and_scale *bias_and_scale; 741 struct dc_csc_transform input_csc_color_matrix; 742 struct fixed31_32 coeff_reduction_factor; 743 struct fixed31_32 hdr_mult; 744 745 // TODO: No longer used, remove 746 struct dc_hdr_static_metadata hdr_static_ctx; 747 748 enum dc_color_space color_space; 749 750 struct dc_3dlut *lut3d_func; 751 struct dc_transfer_func *in_shaper_func; 752 struct dc_transfer_func *blend_tf; 753 754 enum surface_pixel_format format; 755 enum dc_rotation_angle rotation; 756 enum plane_stereo_format stereo_format; 757 758 bool is_tiling_rotated; 759 bool per_pixel_alpha; 760 bool global_alpha; 761 int global_alpha_value; 762 bool visible; 763 bool flip_immediate; 764 bool horizontal_mirror; 765 int layer_index; 766 767 union surface_update_flags update_flags; 768 /* private to DC core */ 769 struct dc_plane_status status; 770 struct dc_context *ctx; 771 772 /* HACK: Workaround for forcing full reprogramming under some conditions */ 773 bool force_full_update; 774 775 /* private to dc_surface.c */ 776 enum dc_irq_source irq_source; 777 struct kref refcount; 778 }; 779 780 struct dc_plane_info { 781 struct plane_size plane_size; 782 union dc_tiling_info tiling_info; 783 struct dc_plane_dcc_param dcc; 784 enum surface_pixel_format format; 785 enum dc_rotation_angle rotation; 786 enum plane_stereo_format stereo_format; 787 enum dc_color_space color_space; 788 bool horizontal_mirror; 789 bool visible; 790 bool per_pixel_alpha; 791 bool global_alpha; 792 int global_alpha_value; 793 bool input_csc_enabled; 794 int layer_index; 795 }; 796 797 struct dc_scaling_info { 798 struct rect src_rect; 799 struct rect dst_rect; 800 struct rect clip_rect; 801 struct scaling_taps scaling_quality; 802 }; 803 804 struct dc_surface_update { 805 struct dc_plane_state *surface; 806 807 /* isr safe update parameters. null means no updates */ 808 const struct dc_flip_addrs *flip_addr; 809 const struct dc_plane_info *plane_info; 810 const struct dc_scaling_info *scaling_info; 811 struct fixed31_32 hdr_mult; 812 /* following updates require alloc/sleep/spin that is not isr safe, 813 * null means no updates 814 */ 815 const struct dc_gamma *gamma; 816 const struct dc_transfer_func *in_transfer_func; 817 818 const struct dc_csc_transform *input_csc_color_matrix; 819 const struct fixed31_32 *coeff_reduction_factor; 820 const struct dc_transfer_func *func_shaper; 821 const struct dc_3dlut *lut3d_func; 822 const struct dc_transfer_func *blend_tf; 823 }; 824 825 /* 826 * Create a new surface with default parameters; 827 */ 828 struct dc_plane_state *dc_create_plane_state(struct dc *dc); 829 const struct dc_plane_status *dc_plane_get_status( 830 const struct dc_plane_state *plane_state); 831 832 void dc_plane_state_retain(struct dc_plane_state *plane_state); 833 void dc_plane_state_release(struct dc_plane_state *plane_state); 834 835 void dc_gamma_retain(struct dc_gamma *dc_gamma); 836 void dc_gamma_release(struct dc_gamma **dc_gamma); 837 struct dc_gamma *dc_create_gamma(void); 838 839 void dc_transfer_func_retain(struct dc_transfer_func *dc_tf); 840 void dc_transfer_func_release(struct dc_transfer_func *dc_tf); 841 struct dc_transfer_func *dc_create_transfer_func(void); 842 843 struct dc_3dlut *dc_create_3dlut_func(void); 844 void dc_3dlut_func_release(struct dc_3dlut *lut); 845 void dc_3dlut_func_retain(struct dc_3dlut *lut); 846 /* 847 * This structure holds a surface address. There could be multiple addresses 848 * in cases such as Stereo 3D, Planar YUV, etc. Other per-flip attributes such 849 * as frame durations and DCC format can also be set. 850 */ 851 struct dc_flip_addrs { 852 struct dc_plane_address address; 853 unsigned int flip_timestamp_in_us; 854 bool flip_immediate; 855 /* TODO: add flip duration for FreeSync */ 856 }; 857 858 bool dc_post_update_surfaces_to_stream( 859 struct dc *dc); 860 861 #include "dc_stream.h" 862 863 /* 864 * Structure to store surface/stream associations for validation 865 */ 866 struct dc_validation_set { 867 struct dc_stream_state *stream; 868 struct dc_plane_state *plane_states[MAX_SURFACES]; 869 uint8_t plane_count; 870 }; 871 872 bool dc_validate_seamless_boot_timing(const struct dc *dc, 873 const struct dc_sink *sink, 874 struct dc_crtc_timing *crtc_timing); 875 876 enum dc_status dc_validate_plane(struct dc *dc, const struct dc_plane_state *plane_state); 877 878 void get_clock_requirements_for_state(struct dc_state *state, struct AsicStateEx *info); 879 880 bool dc_set_generic_gpio_for_stereo(bool enable, 881 struct gpio_service *gpio_service); 882 883 /* 884 * fast_validate: we return after determining if we can support the new state, 885 * but before we populate the programming info 886 */ 887 enum dc_status dc_validate_global_state( 888 struct dc *dc, 889 struct dc_state *new_ctx, 890 bool fast_validate); 891 892 893 void dc_resource_state_construct( 894 const struct dc *dc, 895 struct dc_state *dst_ctx); 896 897 void dc_resource_state_copy_construct( 898 const struct dc_state *src_ctx, 899 struct dc_state *dst_ctx); 900 901 void dc_resource_state_copy_construct_current( 902 const struct dc *dc, 903 struct dc_state *dst_ctx); 904 905 void dc_resource_state_destruct(struct dc_state *context); 906 907 /* 908 * TODO update to make it about validation sets 909 * Set up streams and links associated to drive sinks 910 * The streams parameter is an absolute set of all active streams. 911 * 912 * After this call: 913 * Phy, Encoder, Timing Generator are programmed and enabled. 914 * New streams are enabled with blank stream; no memory read. 915 */ 916 bool dc_commit_state(struct dc *dc, struct dc_state *context); 917 918 919 struct dc_state *dc_create_state(struct dc *dc); 920 struct dc_state *dc_copy_state(struct dc_state *src_ctx); 921 void dc_retain_state(struct dc_state *context); 922 void dc_release_state(struct dc_state *context); 923 924 /******************************************************************************* 925 * Link Interfaces 926 ******************************************************************************/ 927 928 struct dpcd_caps { 929 union dpcd_rev dpcd_rev; 930 union max_lane_count max_ln_count; 931 union max_down_spread max_down_spread; 932 union dprx_feature dprx_feature; 933 934 /* valid only for eDP v1.4 or higher*/ 935 uint8_t edp_supported_link_rates_count; 936 enum dc_link_rate edp_supported_link_rates[8]; 937 938 /* dongle type (DP converter, CV smart dongle) */ 939 enum display_dongle_type dongle_type; 940 /* branch device or sink device */ 941 bool is_branch_dev; 942 /* Dongle's downstream count. */ 943 union sink_count sink_count; 944 /* If dongle_type == DISPLAY_DONGLE_DP_HDMI_CONVERTER, 945 indicates 'Frame Sequential-to-lllFrame Pack' conversion capability.*/ 946 struct dc_dongle_caps dongle_caps; 947 948 uint32_t sink_dev_id; 949 int8_t sink_dev_id_str[6]; 950 int8_t sink_hw_revision; 951 int8_t sink_fw_revision[2]; 952 953 uint32_t branch_dev_id; 954 int8_t branch_dev_name[6]; 955 int8_t branch_hw_revision; 956 int8_t branch_fw_revision[2]; 957 958 bool allow_invalid_MSA_timing_param; 959 bool panel_mode_edp; 960 bool dpcd_display_control_capable; 961 bool ext_receiver_cap_field_present; 962 union dpcd_fec_capability fec_cap; 963 struct dpcd_dsc_capabilities dsc_caps; 964 struct dc_lttpr_caps lttpr_caps; 965 966 }; 967 968 #include "dc_link.h" 969 970 /******************************************************************************* 971 * Sink Interfaces - A sink corresponds to a display output device 972 ******************************************************************************/ 973 974 struct dc_container_id { 975 // 128bit GUID in binary form 976 unsigned char guid[16]; 977 // 8 byte port ID -> ELD.PortID 978 unsigned int portId[2]; 979 // 128bit GUID in binary formufacturer name -> ELD.ManufacturerName 980 unsigned short manufacturerName; 981 // 2 byte product code -> ELD.ProductCode 982 unsigned short productCode; 983 }; 984 985 986 struct dc_sink_dsc_caps { 987 // 'true' if these are virtual DPCD's DSC caps (immediately upstream of sink in MST topology), 988 // 'false' if they are sink's DSC caps 989 bool is_virtual_dpcd_dsc; 990 struct dsc_dec_dpcd_caps dsc_dec_caps; 991 }; 992 993 /* 994 * The sink structure contains EDID and other display device properties 995 */ 996 struct dc_sink { 997 enum signal_type sink_signal; 998 struct dc_edid dc_edid; /* raw edid */ 999 struct dc_edid_caps edid_caps; /* parse display caps */ 1000 struct dc_container_id *dc_container_id; 1001 uint32_t dongle_max_pix_clk; 1002 void *priv; 1003 struct stereo_3d_features features_3d[TIMING_3D_FORMAT_MAX]; 1004 bool converter_disable_audio; 1005 1006 struct dc_sink_dsc_caps sink_dsc_caps; 1007 1008 /* private to DC core */ 1009 struct dc_link *link; 1010 struct dc_context *ctx; 1011 1012 uint32_t sink_id; 1013 1014 /* private to dc_sink.c */ 1015 // refcount must be the last member in dc_sink, since we want the 1016 // sink structure to be logically cloneable up to (but not including) 1017 // refcount 1018 struct kref refcount; 1019 }; 1020 1021 void dc_sink_retain(struct dc_sink *sink); 1022 void dc_sink_release(struct dc_sink *sink); 1023 1024 struct dc_sink_init_data { 1025 enum signal_type sink_signal; 1026 struct dc_link *link; 1027 uint32_t dongle_max_pix_clk; 1028 bool converter_disable_audio; 1029 }; 1030 1031 struct dc_sink *dc_sink_create(const struct dc_sink_init_data *init_params); 1032 1033 /* Newer interfaces */ 1034 struct dc_cursor { 1035 struct dc_plane_address address; 1036 struct dc_cursor_attributes attributes; 1037 }; 1038 1039 1040 /******************************************************************************* 1041 * Interrupt interfaces 1042 ******************************************************************************/ 1043 enum dc_irq_source dc_interrupt_to_irq_source( 1044 struct dc *dc, 1045 uint32_t src_id, 1046 uint32_t ext_id); 1047 bool dc_interrupt_set(struct dc *dc, enum dc_irq_source src, bool enable); 1048 void dc_interrupt_ack(struct dc *dc, enum dc_irq_source src); 1049 enum dc_irq_source dc_get_hpd_irq_source_at_index( 1050 struct dc *dc, uint32_t link_index); 1051 1052 /******************************************************************************* 1053 * Power Interfaces 1054 ******************************************************************************/ 1055 1056 void dc_set_power_state( 1057 struct dc *dc, 1058 enum dc_acpi_cm_power_state power_state); 1059 void dc_resume(struct dc *dc); 1060 unsigned int dc_get_current_backlight_pwm(struct dc *dc); 1061 unsigned int dc_get_target_backlight_pwm(struct dc *dc); 1062 1063 bool dc_is_dmcu_initialized(struct dc *dc); 1064 1065 enum dc_status dc_set_clock(struct dc *dc, enum dc_clock_type clock_type, uint32_t clk_khz, uint32_t stepping); 1066 void dc_get_clock(struct dc *dc, enum dc_clock_type clock_type, struct dc_clock_config *clock_cfg); 1067 /******************************************************************************* 1068 * DSC Interfaces 1069 ******************************************************************************/ 1070 #include "dc_dsc.h" 1071 #endif /* DC_INTERFACE_H_ */ 1072