1 /* 2 * Copyright 2012-14 Advanced Micro Devices, Inc. 3 * 4 * Permission is hereby granted, free of charge, to any person obtaining a 5 * copy of this software and associated documentation files (the "Software"), 6 * to deal in the Software without restriction, including without limitation 7 * the rights to use, copy, modify, merge, publish, distribute, sublicense, 8 * and/or sell copies of the Software, and to permit persons to whom the 9 * Software is furnished to do so, subject to the following conditions: 10 * 11 * The above copyright notice and this permission notice shall be included in 12 * all copies or substantial portions of the Software. 13 * 14 * THE SOFTWARE IS PROVIDED "AS IS", WITHOUT WARRANTY OF ANY KIND, EXPRESS OR 15 * IMPLIED, INCLUDING BUT NOT LIMITED TO THE WARRANTIES OF MERCHANTABILITY, 16 * FITNESS FOR A PARTICULAR PURPOSE AND NONINFRINGEMENT. IN NO EVENT SHALL 17 * THE COPYRIGHT HOLDER(S) OR AUTHOR(S) BE LIABLE FOR ANY CLAIM, DAMAGES OR 18 * OTHER LIABILITY, WHETHER IN AN ACTION OF CONTRACT, TORT OR OTHERWISE, 19 * ARISING FROM, OUT OF OR IN CONNECTION WITH THE SOFTWARE OR THE USE OR 20 * OTHER DEALINGS IN THE SOFTWARE. 21 * 22 * Authors: AMD 23 * 24 */ 25 26 #ifndef DC_INTERFACE_H_ 27 #define DC_INTERFACE_H_ 28 29 #include "dc_types.h" 30 #include "grph_object_defs.h" 31 #include "logger_types.h" 32 #if defined(CONFIG_DRM_AMD_DC_HDCP) 33 #include "hdcp_types.h" 34 #endif 35 #include "gpio_types.h" 36 #include "link_service_types.h" 37 #include "grph_object_ctrl_defs.h" 38 #include <inc/hw/opp.h> 39 40 #include "inc/hw_sequencer.h" 41 #include "inc/compressor.h" 42 #include "inc/hw/dmcu.h" 43 #include "dml/display_mode_lib.h" 44 45 /* forward declaration */ 46 struct aux_payload; 47 48 #define DC_VER "3.2.151" 49 50 #define MAX_SURFACES 3 51 #define MAX_PLANES 6 52 #define MAX_STREAMS 6 53 #define MAX_SINKS_PER_LINK 4 54 #define MIN_VIEWPORT_SIZE 12 55 #define MAX_NUM_EDP 2 56 57 /******************************************************************************* 58 * Display Core Interfaces 59 ******************************************************************************/ 60 struct dc_versions { 61 const char *dc_ver; 62 struct dmcu_version dmcu_version; 63 }; 64 65 enum dp_protocol_version { 66 DP_VERSION_1_4, 67 }; 68 69 enum dc_plane_type { 70 DC_PLANE_TYPE_INVALID, 71 DC_PLANE_TYPE_DCE_RGB, 72 DC_PLANE_TYPE_DCE_UNDERLAY, 73 DC_PLANE_TYPE_DCN_UNIVERSAL, 74 }; 75 76 struct dc_plane_cap { 77 enum dc_plane_type type; 78 uint32_t blends_with_above : 1; 79 uint32_t blends_with_below : 1; 80 uint32_t per_pixel_alpha : 1; 81 struct { 82 uint32_t argb8888 : 1; 83 uint32_t nv12 : 1; 84 uint32_t fp16 : 1; 85 uint32_t p010 : 1; 86 uint32_t ayuv : 1; 87 } pixel_format_support; 88 // max upscaling factor x1000 89 // upscaling factors are always >= 1 90 // for example, 1080p -> 8K is 4.0, or 4000 raw value 91 struct { 92 uint32_t argb8888; 93 uint32_t nv12; 94 uint32_t fp16; 95 } max_upscale_factor; 96 // max downscale factor x1000 97 // downscale factors are always <= 1 98 // for example, 8K -> 1080p is 0.25, or 250 raw value 99 struct { 100 uint32_t argb8888; 101 uint32_t nv12; 102 uint32_t fp16; 103 } max_downscale_factor; 104 // minimal width/height 105 uint32_t min_width; 106 uint32_t min_height; 107 }; 108 109 // Color management caps (DPP and MPC) 110 struct rom_curve_caps { 111 uint16_t srgb : 1; 112 uint16_t bt2020 : 1; 113 uint16_t gamma2_2 : 1; 114 uint16_t pq : 1; 115 uint16_t hlg : 1; 116 }; 117 118 struct dpp_color_caps { 119 uint16_t dcn_arch : 1; // all DCE generations treated the same 120 // input lut is different than most LUTs, just plain 256-entry lookup 121 uint16_t input_lut_shared : 1; // shared with DGAM 122 uint16_t icsc : 1; 123 uint16_t dgam_ram : 1; 124 uint16_t post_csc : 1; // before gamut remap 125 uint16_t gamma_corr : 1; 126 127 // hdr_mult and gamut remap always available in DPP (in that order) 128 // 3d lut implies shaper LUT, 129 // it may be shared with MPC - check MPC:shared_3d_lut flag 130 uint16_t hw_3d_lut : 1; 131 uint16_t ogam_ram : 1; // blnd gam 132 uint16_t ocsc : 1; 133 uint16_t dgam_rom_for_yuv : 1; 134 struct rom_curve_caps dgam_rom_caps; 135 struct rom_curve_caps ogam_rom_caps; 136 }; 137 138 struct mpc_color_caps { 139 uint16_t gamut_remap : 1; 140 uint16_t ogam_ram : 1; 141 uint16_t ocsc : 1; 142 uint16_t num_3dluts : 3; //3d lut always assumes a preceding shaper LUT 143 uint16_t shared_3d_lut:1; //can be in either DPP or MPC, but single instance 144 145 struct rom_curve_caps ogam_rom_caps; 146 }; 147 148 struct dc_color_caps { 149 struct dpp_color_caps dpp; 150 struct mpc_color_caps mpc; 151 }; 152 153 struct dc_caps { 154 uint32_t max_streams; 155 uint32_t max_links; 156 uint32_t max_audios; 157 uint32_t max_slave_planes; 158 uint32_t max_slave_yuv_planes; 159 uint32_t max_slave_rgb_planes; 160 uint32_t max_planes; 161 uint32_t max_downscale_ratio; 162 uint32_t i2c_speed_in_khz; 163 uint32_t i2c_speed_in_khz_hdcp; 164 uint32_t dmdata_alloc_size; 165 unsigned int max_cursor_size; 166 unsigned int max_video_width; 167 unsigned int min_horizontal_blanking_period; 168 int linear_pitch_alignment; 169 bool dcc_const_color; 170 bool dynamic_audio; 171 bool is_apu; 172 bool dual_link_dvi; 173 bool post_blend_color_processing; 174 bool force_dp_tps4_for_cp2520; 175 bool disable_dp_clk_share; 176 bool psp_setup_panel_mode; 177 bool extended_aux_timeout_support; 178 bool dmcub_support; 179 uint32_t num_of_internal_disp; 180 enum dp_protocol_version max_dp_protocol_version; 181 unsigned int mall_size_per_mem_channel; 182 unsigned int mall_size_total; 183 unsigned int cursor_cache_size; 184 struct dc_plane_cap planes[MAX_PLANES]; 185 struct dc_color_caps color; 186 #if defined(CONFIG_DRM_AMD_DC_DCN) 187 bool dp_hpo; 188 #endif 189 bool vbios_lttpr_aware; 190 bool vbios_lttpr_enable; 191 }; 192 193 struct dc_bug_wa { 194 bool no_connect_phy_config; 195 bool dedcn20_305_wa; 196 bool skip_clock_update; 197 bool lt_early_cr_pattern; 198 }; 199 200 struct dc_dcc_surface_param { 201 struct dc_size surface_size; 202 enum surface_pixel_format format; 203 enum swizzle_mode_values swizzle_mode; 204 enum dc_scan_direction scan; 205 }; 206 207 struct dc_dcc_setting { 208 unsigned int max_compressed_blk_size; 209 unsigned int max_uncompressed_blk_size; 210 bool independent_64b_blks; 211 #if defined(CONFIG_DRM_AMD_DC_DCN) 212 //These bitfields to be used starting with DCN 3.0 213 struct { 214 uint32_t dcc_256_64_64 : 1;//available in ASICs before DCN 3.0 (the worst compression case) 215 uint32_t dcc_128_128_uncontrained : 1; //available in ASICs before DCN 3.0 216 uint32_t dcc_256_128_128 : 1; //available starting with DCN 3.0 217 uint32_t dcc_256_256_unconstrained : 1; //available in ASICs before DCN 3.0 (the best compression case) 218 } dcc_controls; 219 #endif 220 }; 221 222 struct dc_surface_dcc_cap { 223 union { 224 struct { 225 struct dc_dcc_setting rgb; 226 } grph; 227 228 struct { 229 struct dc_dcc_setting luma; 230 struct dc_dcc_setting chroma; 231 } video; 232 }; 233 234 bool capable; 235 bool const_color_support; 236 }; 237 238 struct dc_static_screen_params { 239 struct { 240 bool force_trigger; 241 bool cursor_update; 242 bool surface_update; 243 bool overlay_update; 244 } triggers; 245 unsigned int num_frames; 246 }; 247 248 249 /* Surface update type is used by dc_update_surfaces_and_stream 250 * The update type is determined at the very beginning of the function based 251 * on parameters passed in and decides how much programming (or updating) is 252 * going to be done during the call. 253 * 254 * UPDATE_TYPE_FAST is used for really fast updates that do not require much 255 * logical calculations or hardware register programming. This update MUST be 256 * ISR safe on windows. Currently fast update will only be used to flip surface 257 * address. 258 * 259 * UPDATE_TYPE_MED is used for slower updates which require significant hw 260 * re-programming however do not affect bandwidth consumption or clock 261 * requirements. At present, this is the level at which front end updates 262 * that do not require us to run bw_calcs happen. These are in/out transfer func 263 * updates, viewport offset changes, recout size changes and pixel depth changes. 264 * This update can be done at ISR, but we want to minimize how often this happens. 265 * 266 * UPDATE_TYPE_FULL is slow. Really slow. This requires us to recalculate our 267 * bandwidth and clocks, possibly rearrange some pipes and reprogram anything front 268 * end related. Any time viewport dimensions, recout dimensions, scaling ratios or 269 * gamma need to be adjusted or pipe needs to be turned on (or disconnected) we do 270 * a full update. This cannot be done at ISR level and should be a rare event. 271 * Unless someone is stress testing mpo enter/exit, playing with colour or adjusting 272 * underscan we don't expect to see this call at all. 273 */ 274 275 enum surface_update_type { 276 UPDATE_TYPE_FAST, /* super fast, safe to execute in isr */ 277 UPDATE_TYPE_MED, /* ISR safe, most of programming needed, no bw/clk change*/ 278 UPDATE_TYPE_FULL, /* may need to shuffle resources */ 279 }; 280 281 /* Forward declaration*/ 282 struct dc; 283 struct dc_plane_state; 284 struct dc_state; 285 286 287 struct dc_cap_funcs { 288 bool (*get_dcc_compression_cap)(const struct dc *dc, 289 const struct dc_dcc_surface_param *input, 290 struct dc_surface_dcc_cap *output); 291 }; 292 293 struct link_training_settings; 294 295 #if defined(CONFIG_DRM_AMD_DC_DCN) 296 union allow_lttpr_non_transparent_mode { 297 struct { 298 bool DP1_4A : 1; 299 bool DP2_0 : 1; 300 } bits; 301 unsigned char raw; 302 }; 303 #endif 304 /* Structure to hold configuration flags set by dm at dc creation. */ 305 struct dc_config { 306 bool gpu_vm_support; 307 bool disable_disp_pll_sharing; 308 bool fbc_support; 309 bool disable_fractional_pwm; 310 bool allow_seamless_boot_optimization; 311 bool power_down_display_on_boot; 312 bool edp_not_connected; 313 bool edp_no_power_sequencing; 314 bool force_enum_edp; 315 bool forced_clocks; 316 #if defined(CONFIG_DRM_AMD_DC_DCN) 317 union allow_lttpr_non_transparent_mode allow_lttpr_non_transparent_mode; 318 #else 319 bool allow_lttpr_non_transparent_mode; 320 #endif 321 bool multi_mon_pp_mclk_switch; 322 bool disable_dmcu; 323 bool enable_4to1MPC; 324 bool allow_edp_hotplug_detection; 325 #if defined(CONFIG_DRM_AMD_DC_DCN) 326 bool clamp_min_dcfclk; 327 #endif 328 uint64_t vblank_alignment_dto_params; 329 uint8_t vblank_alignment_max_frame_time_diff; 330 bool is_asymmetric_memory; 331 bool is_single_rank_dimm; 332 }; 333 334 enum visual_confirm { 335 VISUAL_CONFIRM_DISABLE = 0, 336 VISUAL_CONFIRM_SURFACE = 1, 337 VISUAL_CONFIRM_HDR = 2, 338 VISUAL_CONFIRM_MPCTREE = 4, 339 VISUAL_CONFIRM_PSR = 5, 340 VISUAL_CONFIRM_SWIZZLE = 9, 341 }; 342 343 enum dcc_option { 344 DCC_ENABLE = 0, 345 DCC_DISABLE = 1, 346 DCC_HALF_REQ_DISALBE = 2, 347 }; 348 349 enum pipe_split_policy { 350 MPC_SPLIT_DYNAMIC = 0, 351 MPC_SPLIT_AVOID = 1, 352 MPC_SPLIT_AVOID_MULT_DISP = 2, 353 }; 354 355 enum wm_report_mode { 356 WM_REPORT_DEFAULT = 0, 357 WM_REPORT_OVERRIDE = 1, 358 }; 359 enum dtm_pstate{ 360 dtm_level_p0 = 0,/*highest voltage*/ 361 dtm_level_p1, 362 dtm_level_p2, 363 dtm_level_p3, 364 dtm_level_p4,/*when active_display_count = 0*/ 365 }; 366 367 enum dcn_pwr_state { 368 DCN_PWR_STATE_UNKNOWN = -1, 369 DCN_PWR_STATE_MISSION_MODE = 0, 370 DCN_PWR_STATE_LOW_POWER = 3, 371 }; 372 373 #if defined(CONFIG_DRM_AMD_DC_DCN) 374 enum dcn_zstate_support_state { 375 DCN_ZSTATE_SUPPORT_UNKNOWN, 376 DCN_ZSTATE_SUPPORT_ALLOW, 377 DCN_ZSTATE_SUPPORT_DISALLOW, 378 }; 379 #endif 380 /* 381 * For any clocks that may differ per pipe 382 * only the max is stored in this structure 383 */ 384 struct dc_clocks { 385 int dispclk_khz; 386 int actual_dispclk_khz; 387 int dppclk_khz; 388 int actual_dppclk_khz; 389 int disp_dpp_voltage_level_khz; 390 int dcfclk_khz; 391 int socclk_khz; 392 int dcfclk_deep_sleep_khz; 393 int fclk_khz; 394 int phyclk_khz; 395 int dramclk_khz; 396 bool p_state_change_support; 397 #if defined(CONFIG_DRM_AMD_DC_DCN) 398 enum dcn_zstate_support_state zstate_support; 399 bool dtbclk_en; 400 #endif 401 enum dcn_pwr_state pwr_state; 402 /* 403 * Elements below are not compared for the purposes of 404 * optimization required 405 */ 406 bool prev_p_state_change_support; 407 enum dtm_pstate dtm_level; 408 int max_supported_dppclk_khz; 409 int max_supported_dispclk_khz; 410 int bw_dppclk_khz; /*a copy of dppclk_khz*/ 411 int bw_dispclk_khz; 412 }; 413 414 struct dc_bw_validation_profile { 415 bool enable; 416 417 unsigned long long total_ticks; 418 unsigned long long voltage_level_ticks; 419 unsigned long long watermark_ticks; 420 unsigned long long rq_dlg_ticks; 421 422 unsigned long long total_count; 423 unsigned long long skip_fast_count; 424 unsigned long long skip_pass_count; 425 unsigned long long skip_fail_count; 426 }; 427 428 #define BW_VAL_TRACE_SETUP() \ 429 unsigned long long end_tick = 0; \ 430 unsigned long long voltage_level_tick = 0; \ 431 unsigned long long watermark_tick = 0; \ 432 unsigned long long start_tick = dc->debug.bw_val_profile.enable ? \ 433 dm_get_timestamp(dc->ctx) : 0 434 435 #define BW_VAL_TRACE_COUNT() \ 436 if (dc->debug.bw_val_profile.enable) \ 437 dc->debug.bw_val_profile.total_count++ 438 439 #define BW_VAL_TRACE_SKIP(status) \ 440 if (dc->debug.bw_val_profile.enable) { \ 441 if (!voltage_level_tick) \ 442 voltage_level_tick = dm_get_timestamp(dc->ctx); \ 443 dc->debug.bw_val_profile.skip_ ## status ## _count++; \ 444 } 445 446 #define BW_VAL_TRACE_END_VOLTAGE_LEVEL() \ 447 if (dc->debug.bw_val_profile.enable) \ 448 voltage_level_tick = dm_get_timestamp(dc->ctx) 449 450 #define BW_VAL_TRACE_END_WATERMARKS() \ 451 if (dc->debug.bw_val_profile.enable) \ 452 watermark_tick = dm_get_timestamp(dc->ctx) 453 454 #define BW_VAL_TRACE_FINISH() \ 455 if (dc->debug.bw_val_profile.enable) { \ 456 end_tick = dm_get_timestamp(dc->ctx); \ 457 dc->debug.bw_val_profile.total_ticks += end_tick - start_tick; \ 458 dc->debug.bw_val_profile.voltage_level_ticks += voltage_level_tick - start_tick; \ 459 if (watermark_tick) { \ 460 dc->debug.bw_val_profile.watermark_ticks += watermark_tick - voltage_level_tick; \ 461 dc->debug.bw_val_profile.rq_dlg_ticks += end_tick - watermark_tick; \ 462 } \ 463 } 464 465 union mem_low_power_enable_options { 466 struct { 467 bool vga: 1; 468 bool i2c: 1; 469 bool dmcu: 1; 470 bool dscl: 1; 471 bool cm: 1; 472 bool mpc: 1; 473 bool optc: 1; 474 } bits; 475 uint32_t u32All; 476 }; 477 478 struct dc_debug_data { 479 uint32_t ltFailCount; 480 uint32_t i2cErrorCount; 481 uint32_t auxErrorCount; 482 }; 483 484 struct dc_phy_addr_space_config { 485 struct { 486 uint64_t start_addr; 487 uint64_t end_addr; 488 uint64_t fb_top; 489 uint64_t fb_offset; 490 uint64_t fb_base; 491 uint64_t agp_top; 492 uint64_t agp_bot; 493 uint64_t agp_base; 494 } system_aperture; 495 496 struct { 497 uint64_t page_table_start_addr; 498 uint64_t page_table_end_addr; 499 uint64_t page_table_base_addr; 500 bool base_addr_is_mc_addr; 501 } gart_config; 502 503 bool valid; 504 bool is_hvm_enabled; 505 uint64_t page_table_default_page_addr; 506 }; 507 508 struct dc_virtual_addr_space_config { 509 uint64_t page_table_base_addr; 510 uint64_t page_table_start_addr; 511 uint64_t page_table_end_addr; 512 uint32_t page_table_block_size_in_bytes; 513 uint8_t page_table_depth; // 1 = 1 level, 2 = 2 level, etc. 0 = invalid 514 }; 515 516 struct dc_bounding_box_overrides { 517 int sr_exit_time_ns; 518 int sr_enter_plus_exit_time_ns; 519 int urgent_latency_ns; 520 int percent_of_ideal_drambw; 521 int dram_clock_change_latency_ns; 522 int dummy_clock_change_latency_ns; 523 /* This forces a hard min on the DCFCLK we use 524 * for DML. Unlike the debug option for forcing 525 * DCFCLK, this override affects watermark calculations 526 */ 527 int min_dcfclk_mhz; 528 }; 529 530 struct dc_state; 531 struct resource_pool; 532 struct dce_hwseq; 533 534 struct dc_debug_options { 535 bool native422_support; 536 bool disable_dsc; 537 enum visual_confirm visual_confirm; 538 bool sanity_checks; 539 bool max_disp_clk; 540 bool surface_trace; 541 bool timing_trace; 542 bool clock_trace; 543 bool validation_trace; 544 bool bandwidth_calcs_trace; 545 int max_downscale_src_width; 546 547 /* stutter efficiency related */ 548 bool disable_stutter; 549 bool use_max_lb; 550 enum dcc_option disable_dcc; 551 enum pipe_split_policy pipe_split_policy; 552 bool force_single_disp_pipe_split; 553 bool voltage_align_fclk; 554 bool disable_min_fclk; 555 556 bool disable_dfs_bypass; 557 bool disable_dpp_power_gate; 558 bool disable_hubp_power_gate; 559 bool disable_dsc_power_gate; 560 int dsc_min_slice_height_override; 561 int dsc_bpp_increment_div; 562 bool disable_pplib_wm_range; 563 enum wm_report_mode pplib_wm_report_mode; 564 unsigned int min_disp_clk_khz; 565 unsigned int min_dpp_clk_khz; 566 int sr_exit_time_dpm0_ns; 567 int sr_enter_plus_exit_time_dpm0_ns; 568 int sr_exit_time_ns; 569 int sr_enter_plus_exit_time_ns; 570 int urgent_latency_ns; 571 uint32_t underflow_assert_delay_us; 572 int percent_of_ideal_drambw; 573 int dram_clock_change_latency_ns; 574 bool optimized_watermark; 575 int always_scale; 576 bool disable_pplib_clock_request; 577 bool disable_clock_gate; 578 bool disable_mem_low_power; 579 #if defined(CONFIG_DRM_AMD_DC_DCN) 580 bool pstate_enabled; 581 #endif 582 bool disable_dmcu; 583 bool disable_psr; 584 bool force_abm_enable; 585 bool disable_stereo_support; 586 bool vsr_support; 587 bool performance_trace; 588 bool az_endpoint_mute_only; 589 bool always_use_regamma; 590 bool recovery_enabled; 591 bool avoid_vbios_exec_table; 592 bool scl_reset_length10; 593 bool hdmi20_disable; 594 bool skip_detection_link_training; 595 uint32_t edid_read_retry_times; 596 bool remove_disconnect_edp; 597 unsigned int force_odm_combine; //bit vector based on otg inst 598 #if defined(CONFIG_DRM_AMD_DC_DCN) 599 unsigned int force_odm_combine_4to1; //bit vector based on otg inst 600 bool disable_z9_mpc; 601 #endif 602 unsigned int force_fclk_khz; 603 bool enable_tri_buf; 604 bool dmub_offload_enabled; 605 bool dmcub_emulation; 606 #if defined(CONFIG_DRM_AMD_DC_DCN) 607 bool disable_idle_power_optimizations; 608 unsigned int mall_size_override; 609 unsigned int mall_additional_timer_percent; 610 bool mall_error_as_fatal; 611 #endif 612 bool dmub_command_table; /* for testing only */ 613 struct dc_bw_validation_profile bw_val_profile; 614 bool disable_fec; 615 bool disable_48mhz_pwrdwn; 616 /* This forces a hard min on the DCFCLK requested to SMU/PP 617 * watermarks are not affected. 618 */ 619 unsigned int force_min_dcfclk_mhz; 620 #if defined(CONFIG_DRM_AMD_DC_DCN) 621 int dwb_fi_phase; 622 #endif 623 bool disable_timing_sync; 624 bool cm_in_bypass; 625 int force_clock_mode;/*every mode change.*/ 626 627 bool disable_dram_clock_change_vactive_support; 628 bool validate_dml_output; 629 bool enable_dmcub_surface_flip; 630 bool usbc_combo_phy_reset_wa; 631 bool enable_dram_clock_change_one_display_vactive; 632 #if defined(CONFIG_DRM_AMD_DC_DCN) 633 /* TODO - remove once tested */ 634 bool legacy_dp2_lt; 635 #endif 636 union mem_low_power_enable_options enable_mem_low_power; 637 bool force_vblank_alignment; 638 639 /* Enable dmub aux for legacy ddc */ 640 bool enable_dmub_aux_for_legacy_ddc; 641 bool optimize_edp_link_rate; /* eDP ILR */ 642 /* force enable edp FEC */ 643 bool force_enable_edp_fec; 644 /* FEC/PSR1 sequence enable delay in 100us */ 645 uint8_t fec_enable_delay_in100us; 646 bool enable_driver_sequence_debug; 647 #if defined(CONFIG_DRM_AMD_DC_DCN) 648 bool disable_z10; 649 bool enable_sw_cntl_psr; 650 #endif 651 }; 652 653 struct gpu_info_soc_bounding_box_v1_0; 654 struct dc { 655 struct dc_debug_options debug; 656 struct dc_versions versions; 657 struct dc_caps caps; 658 struct dc_cap_funcs cap_funcs; 659 struct dc_config config; 660 struct dc_bounding_box_overrides bb_overrides; 661 struct dc_bug_wa work_arounds; 662 struct dc_context *ctx; 663 struct dc_phy_addr_space_config vm_pa_config; 664 665 uint8_t link_count; 666 struct dc_link *links[MAX_PIPES * 2]; 667 668 struct dc_state *current_state; 669 struct resource_pool *res_pool; 670 671 struct clk_mgr *clk_mgr; 672 673 /* Display Engine Clock levels */ 674 struct dm_pp_clock_levels sclk_lvls; 675 676 /* Inputs into BW and WM calculations. */ 677 struct bw_calcs_dceip *bw_dceip; 678 struct bw_calcs_vbios *bw_vbios; 679 #ifdef CONFIG_DRM_AMD_DC_DCN 680 struct dcn_soc_bounding_box *dcn_soc; 681 struct dcn_ip_params *dcn_ip; 682 struct display_mode_lib dml; 683 #endif 684 685 /* HW functions */ 686 struct hw_sequencer_funcs hwss; 687 struct dce_hwseq *hwseq; 688 689 /* Require to optimize clocks and bandwidth for added/removed planes */ 690 bool optimized_required; 691 bool wm_optimized_required; 692 #if defined(CONFIG_DRM_AMD_DC_DCN) 693 bool idle_optimizations_allowed; 694 #endif 695 696 /* Require to maintain clocks and bandwidth for UEFI enabled HW */ 697 698 /* FBC compressor */ 699 struct compressor *fbc_compressor; 700 701 struct dc_debug_data debug_data; 702 struct dpcd_vendor_signature vendor_signature; 703 704 const char *build_id; 705 struct vm_helper *vm_helper; 706 }; 707 708 enum frame_buffer_mode { 709 FRAME_BUFFER_MODE_LOCAL_ONLY = 0, 710 FRAME_BUFFER_MODE_ZFB_ONLY, 711 FRAME_BUFFER_MODE_MIXED_ZFB_AND_LOCAL, 712 } ; 713 714 struct dchub_init_data { 715 int64_t zfb_phys_addr_base; 716 int64_t zfb_mc_base_addr; 717 uint64_t zfb_size_in_byte; 718 enum frame_buffer_mode fb_mode; 719 bool dchub_initialzied; 720 bool dchub_info_valid; 721 }; 722 723 struct dc_init_data { 724 struct hw_asic_id asic_id; 725 void *driver; /* ctx */ 726 struct cgs_device *cgs_device; 727 struct dc_bounding_box_overrides bb_overrides; 728 729 int num_virtual_links; 730 /* 731 * If 'vbios_override' not NULL, it will be called instead 732 * of the real VBIOS. Intended use is Diagnostics on FPGA. 733 */ 734 struct dc_bios *vbios_override; 735 enum dce_environment dce_environment; 736 737 struct dmub_offload_funcs *dmub_if; 738 struct dc_reg_helper_state *dmub_offload; 739 740 struct dc_config flags; 741 uint64_t log_mask; 742 743 struct dpcd_vendor_signature vendor_signature; 744 #if defined(CONFIG_DRM_AMD_DC_DCN) 745 bool force_smu_not_present; 746 #endif 747 }; 748 749 struct dc_callback_init { 750 #ifdef CONFIG_DRM_AMD_DC_HDCP 751 struct cp_psp cp_psp; 752 #else 753 uint8_t reserved; 754 #endif 755 }; 756 757 struct dc *dc_create(const struct dc_init_data *init_params); 758 void dc_hardware_init(struct dc *dc); 759 760 int dc_get_vmid_use_vector(struct dc *dc); 761 void dc_setup_vm_context(struct dc *dc, struct dc_virtual_addr_space_config *va_config, int vmid); 762 /* Returns the number of vmids supported */ 763 int dc_setup_system_context(struct dc *dc, struct dc_phy_addr_space_config *pa_config); 764 void dc_init_callbacks(struct dc *dc, 765 const struct dc_callback_init *init_params); 766 void dc_deinit_callbacks(struct dc *dc); 767 void dc_destroy(struct dc **dc); 768 769 /******************************************************************************* 770 * Surface Interfaces 771 ******************************************************************************/ 772 773 enum { 774 TRANSFER_FUNC_POINTS = 1025 775 }; 776 777 struct dc_hdr_static_metadata { 778 /* display chromaticities and white point in units of 0.00001 */ 779 unsigned int chromaticity_green_x; 780 unsigned int chromaticity_green_y; 781 unsigned int chromaticity_blue_x; 782 unsigned int chromaticity_blue_y; 783 unsigned int chromaticity_red_x; 784 unsigned int chromaticity_red_y; 785 unsigned int chromaticity_white_point_x; 786 unsigned int chromaticity_white_point_y; 787 788 uint32_t min_luminance; 789 uint32_t max_luminance; 790 uint32_t maximum_content_light_level; 791 uint32_t maximum_frame_average_light_level; 792 }; 793 794 enum dc_transfer_func_type { 795 TF_TYPE_PREDEFINED, 796 TF_TYPE_DISTRIBUTED_POINTS, 797 TF_TYPE_BYPASS, 798 TF_TYPE_HWPWL 799 }; 800 801 struct dc_transfer_func_distributed_points { 802 struct fixed31_32 red[TRANSFER_FUNC_POINTS]; 803 struct fixed31_32 green[TRANSFER_FUNC_POINTS]; 804 struct fixed31_32 blue[TRANSFER_FUNC_POINTS]; 805 806 uint16_t end_exponent; 807 uint16_t x_point_at_y1_red; 808 uint16_t x_point_at_y1_green; 809 uint16_t x_point_at_y1_blue; 810 }; 811 812 enum dc_transfer_func_predefined { 813 TRANSFER_FUNCTION_SRGB, 814 TRANSFER_FUNCTION_BT709, 815 TRANSFER_FUNCTION_PQ, 816 TRANSFER_FUNCTION_LINEAR, 817 TRANSFER_FUNCTION_UNITY, 818 TRANSFER_FUNCTION_HLG, 819 TRANSFER_FUNCTION_HLG12, 820 TRANSFER_FUNCTION_GAMMA22, 821 TRANSFER_FUNCTION_GAMMA24, 822 TRANSFER_FUNCTION_GAMMA26 823 }; 824 825 826 struct dc_transfer_func { 827 struct kref refcount; 828 enum dc_transfer_func_type type; 829 enum dc_transfer_func_predefined tf; 830 /* FP16 1.0 reference level in nits, default is 80 nits, only for PQ*/ 831 uint32_t sdr_ref_white_level; 832 union { 833 struct pwl_params pwl; 834 struct dc_transfer_func_distributed_points tf_pts; 835 }; 836 }; 837 838 839 union dc_3dlut_state { 840 struct { 841 uint32_t initialized:1; /*if 3dlut is went through color module for initialization */ 842 uint32_t rmu_idx_valid:1; /*if mux settings are valid*/ 843 uint32_t rmu_mux_num:3; /*index of mux to use*/ 844 uint32_t mpc_rmu0_mux:4; /*select mpcc on mux, one of the following : mpcc0, mpcc1, mpcc2, mpcc3*/ 845 uint32_t mpc_rmu1_mux:4; 846 uint32_t mpc_rmu2_mux:4; 847 uint32_t reserved:15; 848 } bits; 849 uint32_t raw; 850 }; 851 852 853 struct dc_3dlut { 854 struct kref refcount; 855 struct tetrahedral_params lut_3d; 856 struct fixed31_32 hdr_multiplier; 857 union dc_3dlut_state state; 858 }; 859 /* 860 * This structure is filled in by dc_surface_get_status and contains 861 * the last requested address and the currently active address so the called 862 * can determine if there are any outstanding flips 863 */ 864 struct dc_plane_status { 865 struct dc_plane_address requested_address; 866 struct dc_plane_address current_address; 867 bool is_flip_pending; 868 bool is_right_eye; 869 }; 870 871 union surface_update_flags { 872 873 struct { 874 uint32_t addr_update:1; 875 /* Medium updates */ 876 uint32_t dcc_change:1; 877 uint32_t color_space_change:1; 878 uint32_t horizontal_mirror_change:1; 879 uint32_t per_pixel_alpha_change:1; 880 uint32_t global_alpha_change:1; 881 uint32_t hdr_mult:1; 882 uint32_t rotation_change:1; 883 uint32_t swizzle_change:1; 884 uint32_t scaling_change:1; 885 uint32_t position_change:1; 886 uint32_t in_transfer_func_change:1; 887 uint32_t input_csc_change:1; 888 uint32_t coeff_reduction_change:1; 889 uint32_t output_tf_change:1; 890 uint32_t pixel_format_change:1; 891 uint32_t plane_size_change:1; 892 uint32_t gamut_remap_change:1; 893 894 /* Full updates */ 895 uint32_t new_plane:1; 896 uint32_t bpp_change:1; 897 uint32_t gamma_change:1; 898 uint32_t bandwidth_change:1; 899 uint32_t clock_change:1; 900 uint32_t stereo_format_change:1; 901 uint32_t full_update:1; 902 } bits; 903 904 uint32_t raw; 905 }; 906 907 struct dc_plane_state { 908 struct dc_plane_address address; 909 struct dc_plane_flip_time time; 910 bool triplebuffer_flips; 911 struct scaling_taps scaling_quality; 912 struct rect src_rect; 913 struct rect dst_rect; 914 struct rect clip_rect; 915 916 struct plane_size plane_size; 917 union dc_tiling_info tiling_info; 918 919 struct dc_plane_dcc_param dcc; 920 921 struct dc_gamma *gamma_correction; 922 struct dc_transfer_func *in_transfer_func; 923 struct dc_bias_and_scale *bias_and_scale; 924 struct dc_csc_transform input_csc_color_matrix; 925 struct fixed31_32 coeff_reduction_factor; 926 struct fixed31_32 hdr_mult; 927 struct colorspace_transform gamut_remap_matrix; 928 929 // TODO: No longer used, remove 930 struct dc_hdr_static_metadata hdr_static_ctx; 931 932 enum dc_color_space color_space; 933 934 struct dc_3dlut *lut3d_func; 935 struct dc_transfer_func *in_shaper_func; 936 struct dc_transfer_func *blend_tf; 937 938 #if defined(CONFIG_DRM_AMD_DC_DCN) 939 struct dc_transfer_func *gamcor_tf; 940 #endif 941 enum surface_pixel_format format; 942 enum dc_rotation_angle rotation; 943 enum plane_stereo_format stereo_format; 944 945 bool is_tiling_rotated; 946 bool per_pixel_alpha; 947 bool global_alpha; 948 int global_alpha_value; 949 bool visible; 950 bool flip_immediate; 951 bool horizontal_mirror; 952 int layer_index; 953 954 union surface_update_flags update_flags; 955 bool flip_int_enabled; 956 bool skip_manual_trigger; 957 958 /* private to DC core */ 959 struct dc_plane_status status; 960 struct dc_context *ctx; 961 962 /* HACK: Workaround for forcing full reprogramming under some conditions */ 963 bool force_full_update; 964 965 /* private to dc_surface.c */ 966 enum dc_irq_source irq_source; 967 struct kref refcount; 968 }; 969 970 struct dc_plane_info { 971 struct plane_size plane_size; 972 union dc_tiling_info tiling_info; 973 struct dc_plane_dcc_param dcc; 974 enum surface_pixel_format format; 975 enum dc_rotation_angle rotation; 976 enum plane_stereo_format stereo_format; 977 enum dc_color_space color_space; 978 bool horizontal_mirror; 979 bool visible; 980 bool per_pixel_alpha; 981 bool global_alpha; 982 int global_alpha_value; 983 bool input_csc_enabled; 984 int layer_index; 985 }; 986 987 struct dc_scaling_info { 988 struct rect src_rect; 989 struct rect dst_rect; 990 struct rect clip_rect; 991 struct scaling_taps scaling_quality; 992 }; 993 994 struct dc_surface_update { 995 struct dc_plane_state *surface; 996 997 /* isr safe update parameters. null means no updates */ 998 const struct dc_flip_addrs *flip_addr; 999 const struct dc_plane_info *plane_info; 1000 const struct dc_scaling_info *scaling_info; 1001 struct fixed31_32 hdr_mult; 1002 /* following updates require alloc/sleep/spin that is not isr safe, 1003 * null means no updates 1004 */ 1005 const struct dc_gamma *gamma; 1006 const struct dc_transfer_func *in_transfer_func; 1007 1008 const struct dc_csc_transform *input_csc_color_matrix; 1009 const struct fixed31_32 *coeff_reduction_factor; 1010 const struct dc_transfer_func *func_shaper; 1011 const struct dc_3dlut *lut3d_func; 1012 const struct dc_transfer_func *blend_tf; 1013 const struct colorspace_transform *gamut_remap_matrix; 1014 }; 1015 1016 /* 1017 * Create a new surface with default parameters; 1018 */ 1019 struct dc_plane_state *dc_create_plane_state(struct dc *dc); 1020 const struct dc_plane_status *dc_plane_get_status( 1021 const struct dc_plane_state *plane_state); 1022 1023 void dc_plane_state_retain(struct dc_plane_state *plane_state); 1024 void dc_plane_state_release(struct dc_plane_state *plane_state); 1025 1026 void dc_gamma_retain(struct dc_gamma *dc_gamma); 1027 void dc_gamma_release(struct dc_gamma **dc_gamma); 1028 struct dc_gamma *dc_create_gamma(void); 1029 1030 void dc_transfer_func_retain(struct dc_transfer_func *dc_tf); 1031 void dc_transfer_func_release(struct dc_transfer_func *dc_tf); 1032 struct dc_transfer_func *dc_create_transfer_func(void); 1033 1034 struct dc_3dlut *dc_create_3dlut_func(void); 1035 void dc_3dlut_func_release(struct dc_3dlut *lut); 1036 void dc_3dlut_func_retain(struct dc_3dlut *lut); 1037 /* 1038 * This structure holds a surface address. There could be multiple addresses 1039 * in cases such as Stereo 3D, Planar YUV, etc. Other per-flip attributes such 1040 * as frame durations and DCC format can also be set. 1041 */ 1042 struct dc_flip_addrs { 1043 struct dc_plane_address address; 1044 unsigned int flip_timestamp_in_us; 1045 bool flip_immediate; 1046 /* TODO: add flip duration for FreeSync */ 1047 bool triplebuffer_flips; 1048 }; 1049 1050 void dc_post_update_surfaces_to_stream( 1051 struct dc *dc); 1052 1053 #include "dc_stream.h" 1054 1055 /* 1056 * Structure to store surface/stream associations for validation 1057 */ 1058 struct dc_validation_set { 1059 struct dc_stream_state *stream; 1060 struct dc_plane_state *plane_states[MAX_SURFACES]; 1061 uint8_t plane_count; 1062 }; 1063 1064 bool dc_validate_seamless_boot_timing(const struct dc *dc, 1065 const struct dc_sink *sink, 1066 struct dc_crtc_timing *crtc_timing); 1067 1068 enum dc_status dc_validate_plane(struct dc *dc, const struct dc_plane_state *plane_state); 1069 1070 void get_clock_requirements_for_state(struct dc_state *state, struct AsicStateEx *info); 1071 1072 bool dc_set_generic_gpio_for_stereo(bool enable, 1073 struct gpio_service *gpio_service); 1074 1075 /* 1076 * fast_validate: we return after determining if we can support the new state, 1077 * but before we populate the programming info 1078 */ 1079 enum dc_status dc_validate_global_state( 1080 struct dc *dc, 1081 struct dc_state *new_ctx, 1082 bool fast_validate); 1083 1084 1085 void dc_resource_state_construct( 1086 const struct dc *dc, 1087 struct dc_state *dst_ctx); 1088 1089 #if defined(CONFIG_DRM_AMD_DC_DCN) 1090 bool dc_acquire_release_mpc_3dlut( 1091 struct dc *dc, bool acquire, 1092 struct dc_stream_state *stream, 1093 struct dc_3dlut **lut, 1094 struct dc_transfer_func **shaper); 1095 #endif 1096 1097 void dc_resource_state_copy_construct( 1098 const struct dc_state *src_ctx, 1099 struct dc_state *dst_ctx); 1100 1101 void dc_resource_state_copy_construct_current( 1102 const struct dc *dc, 1103 struct dc_state *dst_ctx); 1104 1105 void dc_resource_state_destruct(struct dc_state *context); 1106 1107 bool dc_resource_is_dsc_encoding_supported(const struct dc *dc); 1108 1109 /* 1110 * TODO update to make it about validation sets 1111 * Set up streams and links associated to drive sinks 1112 * The streams parameter is an absolute set of all active streams. 1113 * 1114 * After this call: 1115 * Phy, Encoder, Timing Generator are programmed and enabled. 1116 * New streams are enabled with blank stream; no memory read. 1117 */ 1118 bool dc_commit_state(struct dc *dc, struct dc_state *context); 1119 1120 struct dc_state *dc_create_state(struct dc *dc); 1121 struct dc_state *dc_copy_state(struct dc_state *src_ctx); 1122 void dc_retain_state(struct dc_state *context); 1123 void dc_release_state(struct dc_state *context); 1124 1125 /******************************************************************************* 1126 * Link Interfaces 1127 ******************************************************************************/ 1128 1129 struct dpcd_caps { 1130 union dpcd_rev dpcd_rev; 1131 union max_lane_count max_ln_count; 1132 union max_down_spread max_down_spread; 1133 union dprx_feature dprx_feature; 1134 1135 /* valid only for eDP v1.4 or higher*/ 1136 uint8_t edp_supported_link_rates_count; 1137 enum dc_link_rate edp_supported_link_rates[8]; 1138 1139 /* dongle type (DP converter, CV smart dongle) */ 1140 enum display_dongle_type dongle_type; 1141 /* branch device or sink device */ 1142 bool is_branch_dev; 1143 /* Dongle's downstream count. */ 1144 union sink_count sink_count; 1145 /* If dongle_type == DISPLAY_DONGLE_DP_HDMI_CONVERTER, 1146 indicates 'Frame Sequential-to-lllFrame Pack' conversion capability.*/ 1147 struct dc_dongle_caps dongle_caps; 1148 1149 uint32_t sink_dev_id; 1150 int8_t sink_dev_id_str[6]; 1151 int8_t sink_hw_revision; 1152 int8_t sink_fw_revision[2]; 1153 1154 uint32_t branch_dev_id; 1155 int8_t branch_dev_name[6]; 1156 int8_t branch_hw_revision; 1157 int8_t branch_fw_revision[2]; 1158 1159 bool allow_invalid_MSA_timing_param; 1160 bool panel_mode_edp; 1161 bool dpcd_display_control_capable; 1162 bool ext_receiver_cap_field_present; 1163 bool dynamic_backlight_capable_edp; 1164 union dpcd_fec_capability fec_cap; 1165 struct dpcd_dsc_capabilities dsc_caps; 1166 struct dc_lttpr_caps lttpr_caps; 1167 struct psr_caps psr_caps; 1168 1169 #if defined(CONFIG_DRM_AMD_DC_DCN) 1170 union dp_128b_132b_supported_link_rates dp_128b_132b_supported_link_rates; 1171 union dp_main_line_channel_coding_cap channel_coding_cap; 1172 union dp_sink_video_fallback_formats fallback_formats; 1173 union dp_fec_capability1 fec_cap1; 1174 #endif 1175 }; 1176 1177 union dpcd_sink_ext_caps { 1178 struct { 1179 /* 0 - Sink supports backlight adjust via PWM during SDR/HDR mode 1180 * 1 - Sink supports backlight adjust via AUX during SDR/HDR mode. 1181 */ 1182 uint8_t sdr_aux_backlight_control : 1; 1183 uint8_t hdr_aux_backlight_control : 1; 1184 uint8_t reserved_1 : 2; 1185 uint8_t oled : 1; 1186 uint8_t reserved : 3; 1187 } bits; 1188 uint8_t raw; 1189 }; 1190 1191 #if defined(CONFIG_DRM_AMD_DC_HDCP) 1192 union hdcp_rx_caps { 1193 struct { 1194 uint8_t version; 1195 uint8_t reserved; 1196 struct { 1197 uint8_t repeater : 1; 1198 uint8_t hdcp_capable : 1; 1199 uint8_t reserved : 6; 1200 } byte0; 1201 } fields; 1202 uint8_t raw[3]; 1203 }; 1204 1205 union hdcp_bcaps { 1206 struct { 1207 uint8_t HDCP_CAPABLE:1; 1208 uint8_t REPEATER:1; 1209 uint8_t RESERVED:6; 1210 } bits; 1211 uint8_t raw; 1212 }; 1213 1214 struct hdcp_caps { 1215 union hdcp_rx_caps rx_caps; 1216 union hdcp_bcaps bcaps; 1217 }; 1218 #endif 1219 1220 #include "dc_link.h" 1221 1222 #if defined(CONFIG_DRM_AMD_DC_DCN) 1223 uint32_t dc_get_opp_for_plane(struct dc *dc, struct dc_plane_state *plane); 1224 1225 #endif 1226 /******************************************************************************* 1227 * Sink Interfaces - A sink corresponds to a display output device 1228 ******************************************************************************/ 1229 1230 struct dc_container_id { 1231 // 128bit GUID in binary form 1232 unsigned char guid[16]; 1233 // 8 byte port ID -> ELD.PortID 1234 unsigned int portId[2]; 1235 // 128bit GUID in binary formufacturer name -> ELD.ManufacturerName 1236 unsigned short manufacturerName; 1237 // 2 byte product code -> ELD.ProductCode 1238 unsigned short productCode; 1239 }; 1240 1241 1242 struct dc_sink_dsc_caps { 1243 // 'true' if these are virtual DPCD's DSC caps (immediately upstream of sink in MST topology), 1244 // 'false' if they are sink's DSC caps 1245 bool is_virtual_dpcd_dsc; 1246 struct dsc_dec_dpcd_caps dsc_dec_caps; 1247 }; 1248 1249 struct dc_sink_fec_caps { 1250 bool is_rx_fec_supported; 1251 bool is_topology_fec_supported; 1252 }; 1253 1254 /* 1255 * The sink structure contains EDID and other display device properties 1256 */ 1257 struct dc_sink { 1258 enum signal_type sink_signal; 1259 struct dc_edid dc_edid; /* raw edid */ 1260 struct dc_edid_caps edid_caps; /* parse display caps */ 1261 struct dc_container_id *dc_container_id; 1262 uint32_t dongle_max_pix_clk; 1263 void *priv; 1264 struct stereo_3d_features features_3d[TIMING_3D_FORMAT_MAX]; 1265 bool converter_disable_audio; 1266 1267 struct dc_sink_dsc_caps dsc_caps; 1268 struct dc_sink_fec_caps fec_caps; 1269 1270 bool is_vsc_sdp_colorimetry_supported; 1271 1272 /* private to DC core */ 1273 struct dc_link *link; 1274 struct dc_context *ctx; 1275 1276 uint32_t sink_id; 1277 1278 /* private to dc_sink.c */ 1279 // refcount must be the last member in dc_sink, since we want the 1280 // sink structure to be logically cloneable up to (but not including) 1281 // refcount 1282 struct kref refcount; 1283 }; 1284 1285 void dc_sink_retain(struct dc_sink *sink); 1286 void dc_sink_release(struct dc_sink *sink); 1287 1288 struct dc_sink_init_data { 1289 enum signal_type sink_signal; 1290 struct dc_link *link; 1291 uint32_t dongle_max_pix_clk; 1292 bool converter_disable_audio; 1293 }; 1294 1295 struct dc_sink *dc_sink_create(const struct dc_sink_init_data *init_params); 1296 1297 /* Newer interfaces */ 1298 struct dc_cursor { 1299 struct dc_plane_address address; 1300 struct dc_cursor_attributes attributes; 1301 }; 1302 1303 1304 /******************************************************************************* 1305 * Interrupt interfaces 1306 ******************************************************************************/ 1307 enum dc_irq_source dc_interrupt_to_irq_source( 1308 struct dc *dc, 1309 uint32_t src_id, 1310 uint32_t ext_id); 1311 bool dc_interrupt_set(struct dc *dc, enum dc_irq_source src, bool enable); 1312 void dc_interrupt_ack(struct dc *dc, enum dc_irq_source src); 1313 enum dc_irq_source dc_get_hpd_irq_source_at_index( 1314 struct dc *dc, uint32_t link_index); 1315 1316 /******************************************************************************* 1317 * Power Interfaces 1318 ******************************************************************************/ 1319 1320 void dc_set_power_state( 1321 struct dc *dc, 1322 enum dc_acpi_cm_power_state power_state); 1323 void dc_resume(struct dc *dc); 1324 1325 void dc_power_down_on_boot(struct dc *dc); 1326 1327 #if defined(CONFIG_DRM_AMD_DC_HDCP) 1328 /* 1329 * HDCP Interfaces 1330 */ 1331 enum hdcp_message_status dc_process_hdcp_msg( 1332 enum signal_type signal, 1333 struct dc_link *link, 1334 struct hdcp_protection_message *message_info); 1335 #endif 1336 bool dc_is_dmcu_initialized(struct dc *dc); 1337 1338 enum dc_status dc_set_clock(struct dc *dc, enum dc_clock_type clock_type, uint32_t clk_khz, uint32_t stepping); 1339 void dc_get_clock(struct dc *dc, enum dc_clock_type clock_type, struct dc_clock_config *clock_cfg); 1340 #if defined(CONFIG_DRM_AMD_DC_DCN) 1341 1342 bool dc_is_plane_eligible_for_idle_optimizations(struct dc *dc, struct dc_plane_state *plane, 1343 struct dc_cursor_attributes *cursor_attr); 1344 1345 void dc_allow_idle_optimizations(struct dc *dc, bool allow); 1346 1347 /* 1348 * blank all streams, and set min and max memory clock to 1349 * lowest and highest DPM level, respectively 1350 */ 1351 void dc_unlock_memory_clock_frequency(struct dc *dc); 1352 1353 /* 1354 * set min memory clock to the min required for current mode, 1355 * max to maxDPM, and unblank streams 1356 */ 1357 void dc_lock_memory_clock_frequency(struct dc *dc); 1358 1359 /* cleanup on driver unload */ 1360 void dc_hardware_release(struct dc *dc); 1361 1362 #endif 1363 1364 bool dc_set_psr_allow_active(struct dc *dc, bool enable); 1365 #if defined(CONFIG_DRM_AMD_DC_DCN) 1366 void dc_z10_restore(struct dc *dc); 1367 void dc_z10_save_init(struct dc *dc); 1368 #endif 1369 1370 bool dc_enable_dmub_notifications(struct dc *dc); 1371 1372 bool dc_process_dmub_aux_transfer_async(struct dc *dc, 1373 uint32_t link_index, 1374 struct aux_payload *payload); 1375 1376 /******************************************************************************* 1377 * DSC Interfaces 1378 ******************************************************************************/ 1379 #include "dc_dsc.h" 1380 1381 /******************************************************************************* 1382 * Disable acc mode Interfaces 1383 ******************************************************************************/ 1384 void dc_disable_accelerated_mode(struct dc *dc); 1385 1386 #endif /* DC_INTERFACE_H_ */ 1387