1 /* 2 * Copyright 2012-14 Advanced Micro Devices, Inc. 3 * 4 * Permission is hereby granted, free of charge, to any person obtaining a 5 * copy of this software and associated documentation files (the "Software"), 6 * to deal in the Software without restriction, including without limitation 7 * the rights to use, copy, modify, merge, publish, distribute, sublicense, 8 * and/or sell copies of the Software, and to permit persons to whom the 9 * Software is furnished to do so, subject to the following conditions: 10 * 11 * The above copyright notice and this permission notice shall be included in 12 * all copies or substantial portions of the Software. 13 * 14 * THE SOFTWARE IS PROVIDED "AS IS", WITHOUT WARRANTY OF ANY KIND, EXPRESS OR 15 * IMPLIED, INCLUDING BUT NOT LIMITED TO THE WARRANTIES OF MERCHANTABILITY, 16 * FITNESS FOR A PARTICULAR PURPOSE AND NONINFRINGEMENT. IN NO EVENT SHALL 17 * THE COPYRIGHT HOLDER(S) OR AUTHOR(S) BE LIABLE FOR ANY CLAIM, DAMAGES OR 18 * OTHER LIABILITY, WHETHER IN AN ACTION OF CONTRACT, TORT OR OTHERWISE, 19 * ARISING FROM, OUT OF OR IN CONNECTION WITH THE SOFTWARE OR THE USE OR 20 * OTHER DEALINGS IN THE SOFTWARE. 21 * 22 * Authors: AMD 23 * 24 */ 25 26 #ifndef DC_INTERFACE_H_ 27 #define DC_INTERFACE_H_ 28 29 #include "dc_types.h" 30 #include "grph_object_defs.h" 31 #include "logger_types.h" 32 #include "hdcp_msg_types.h" 33 #include "gpio_types.h" 34 #include "link_service_types.h" 35 #include "grph_object_ctrl_defs.h" 36 #include <inc/hw/opp.h> 37 38 #include "inc/hw_sequencer.h" 39 #include "inc/compressor.h" 40 #include "inc/hw/dmcu.h" 41 #include "dml/display_mode_lib.h" 42 43 /* forward declaration */ 44 struct aux_payload; 45 struct set_config_cmd_payload; 46 struct dmub_notification; 47 48 #define DC_VER "3.2.236" 49 50 #define MAX_SURFACES 3 51 #define MAX_PLANES 6 52 #define MAX_STREAMS 6 53 #define MIN_VIEWPORT_SIZE 12 54 #define MAX_NUM_EDP 2 55 56 /* Display Core Interfaces */ 57 struct dc_versions { 58 const char *dc_ver; 59 struct dmcu_version dmcu_version; 60 }; 61 62 enum dp_protocol_version { 63 DP_VERSION_1_4, 64 }; 65 66 enum dc_plane_type { 67 DC_PLANE_TYPE_INVALID, 68 DC_PLANE_TYPE_DCE_RGB, 69 DC_PLANE_TYPE_DCE_UNDERLAY, 70 DC_PLANE_TYPE_DCN_UNIVERSAL, 71 }; 72 73 // Sizes defined as multiples of 64KB 74 enum det_size { 75 DET_SIZE_DEFAULT = 0, 76 DET_SIZE_192KB = 3, 77 DET_SIZE_256KB = 4, 78 DET_SIZE_320KB = 5, 79 DET_SIZE_384KB = 6 80 }; 81 82 83 struct dc_plane_cap { 84 enum dc_plane_type type; 85 uint32_t per_pixel_alpha : 1; 86 struct { 87 uint32_t argb8888 : 1; 88 uint32_t nv12 : 1; 89 uint32_t fp16 : 1; 90 uint32_t p010 : 1; 91 uint32_t ayuv : 1; 92 } pixel_format_support; 93 // max upscaling factor x1000 94 // upscaling factors are always >= 1 95 // for example, 1080p -> 8K is 4.0, or 4000 raw value 96 struct { 97 uint32_t argb8888; 98 uint32_t nv12; 99 uint32_t fp16; 100 } max_upscale_factor; 101 // max downscale factor x1000 102 // downscale factors are always <= 1 103 // for example, 8K -> 1080p is 0.25, or 250 raw value 104 struct { 105 uint32_t argb8888; 106 uint32_t nv12; 107 uint32_t fp16; 108 } max_downscale_factor; 109 // minimal width/height 110 uint32_t min_width; 111 uint32_t min_height; 112 }; 113 114 /** 115 * DOC: color-management-caps 116 * 117 * **Color management caps (DPP and MPC)** 118 * 119 * Modules/color calculates various color operations which are translated to 120 * abstracted HW. DCE 5-12 had almost no important changes, but starting with 121 * DCN1, every new generation comes with fairly major differences in color 122 * pipeline. Therefore, we abstract color pipe capabilities so modules/DM can 123 * decide mapping to HW block based on logical capabilities. 124 */ 125 126 /** 127 * struct rom_curve_caps - predefined transfer function caps for degamma and regamma 128 * @srgb: RGB color space transfer func 129 * @bt2020: BT.2020 transfer func 130 * @gamma2_2: standard gamma 131 * @pq: perceptual quantizer transfer function 132 * @hlg: hybrid log–gamma transfer function 133 */ 134 struct rom_curve_caps { 135 uint16_t srgb : 1; 136 uint16_t bt2020 : 1; 137 uint16_t gamma2_2 : 1; 138 uint16_t pq : 1; 139 uint16_t hlg : 1; 140 }; 141 142 /** 143 * struct dpp_color_caps - color pipeline capabilities for display pipe and 144 * plane blocks 145 * 146 * @dcn_arch: all DCE generations treated the same 147 * @input_lut_shared: shared with DGAM. Input LUT is different than most LUTs, 148 * just plain 256-entry lookup 149 * @icsc: input color space conversion 150 * @dgam_ram: programmable degamma LUT 151 * @post_csc: post color space conversion, before gamut remap 152 * @gamma_corr: degamma correction 153 * @hw_3d_lut: 3D LUT support. It implies a shaper LUT before. It may be shared 154 * with MPC by setting mpc:shared_3d_lut flag 155 * @ogam_ram: programmable out/blend gamma LUT 156 * @ocsc: output color space conversion 157 * @dgam_rom_for_yuv: pre-defined degamma LUT for YUV planes 158 * @dgam_rom_caps: pre-definied curve caps for degamma 1D LUT 159 * @ogam_rom_caps: pre-definied curve caps for regamma 1D LUT 160 * 161 * Note: hdr_mult and gamut remap (CTM) are always available in DPP (in that order) 162 */ 163 struct dpp_color_caps { 164 uint16_t dcn_arch : 1; 165 uint16_t input_lut_shared : 1; 166 uint16_t icsc : 1; 167 uint16_t dgam_ram : 1; 168 uint16_t post_csc : 1; 169 uint16_t gamma_corr : 1; 170 uint16_t hw_3d_lut : 1; 171 uint16_t ogam_ram : 1; 172 uint16_t ocsc : 1; 173 uint16_t dgam_rom_for_yuv : 1; 174 struct rom_curve_caps dgam_rom_caps; 175 struct rom_curve_caps ogam_rom_caps; 176 }; 177 178 /** 179 * struct mpc_color_caps - color pipeline capabilities for multiple pipe and 180 * plane combined blocks 181 * 182 * @gamut_remap: color transformation matrix 183 * @ogam_ram: programmable out gamma LUT 184 * @ocsc: output color space conversion matrix 185 * @num_3dluts: MPC 3D LUT; always assumes a preceding shaper LUT 186 * @shared_3d_lut: shared 3D LUT flag. Can be either DPP or MPC, but single 187 * instance 188 * @ogam_rom_caps: pre-definied curve caps for regamma 1D LUT 189 */ 190 struct mpc_color_caps { 191 uint16_t gamut_remap : 1; 192 uint16_t ogam_ram : 1; 193 uint16_t ocsc : 1; 194 uint16_t num_3dluts : 3; 195 uint16_t shared_3d_lut:1; 196 struct rom_curve_caps ogam_rom_caps; 197 }; 198 199 /** 200 * struct dc_color_caps - color pipes capabilities for DPP and MPC hw blocks 201 * @dpp: color pipes caps for DPP 202 * @mpc: color pipes caps for MPC 203 */ 204 struct dc_color_caps { 205 struct dpp_color_caps dpp; 206 struct mpc_color_caps mpc; 207 }; 208 209 struct dc_dmub_caps { 210 bool psr; 211 bool mclk_sw; 212 bool subvp_psr; 213 bool gecc_enable; 214 }; 215 216 struct dc_caps { 217 uint32_t max_streams; 218 uint32_t max_links; 219 uint32_t max_audios; 220 uint32_t max_slave_planes; 221 uint32_t max_slave_yuv_planes; 222 uint32_t max_slave_rgb_planes; 223 uint32_t max_planes; 224 uint32_t max_downscale_ratio; 225 uint32_t i2c_speed_in_khz; 226 uint32_t i2c_speed_in_khz_hdcp; 227 uint32_t dmdata_alloc_size; 228 unsigned int max_cursor_size; 229 unsigned int max_video_width; 230 unsigned int min_horizontal_blanking_period; 231 int linear_pitch_alignment; 232 bool dcc_const_color; 233 bool dynamic_audio; 234 bool is_apu; 235 bool dual_link_dvi; 236 bool post_blend_color_processing; 237 bool force_dp_tps4_for_cp2520; 238 bool disable_dp_clk_share; 239 bool psp_setup_panel_mode; 240 bool extended_aux_timeout_support; 241 bool dmcub_support; 242 bool zstate_support; 243 uint32_t num_of_internal_disp; 244 enum dp_protocol_version max_dp_protocol_version; 245 unsigned int mall_size_per_mem_channel; 246 unsigned int mall_size_total; 247 unsigned int cursor_cache_size; 248 struct dc_plane_cap planes[MAX_PLANES]; 249 struct dc_color_caps color; 250 struct dc_dmub_caps dmub_caps; 251 bool dp_hpo; 252 bool dp_hdmi21_pcon_support; 253 bool edp_dsc_support; 254 bool vbios_lttpr_aware; 255 bool vbios_lttpr_enable; 256 uint32_t max_otg_num; 257 uint32_t max_cab_allocation_bytes; 258 uint32_t cache_line_size; 259 uint32_t cache_num_ways; 260 uint16_t subvp_fw_processing_delay_us; 261 uint8_t subvp_drr_max_vblank_margin_us; 262 uint16_t subvp_prefetch_end_to_mall_start_us; 263 uint8_t subvp_swath_height_margin_lines; // subvp start line must be aligned to 2 x swath height 264 uint16_t subvp_pstate_allow_width_us; 265 uint16_t subvp_vertical_int_margin_us; 266 bool seamless_odm; 267 uint8_t subvp_drr_vblank_start_margin_us; 268 }; 269 270 struct dc_bug_wa { 271 bool no_connect_phy_config; 272 bool dedcn20_305_wa; 273 bool skip_clock_update; 274 bool lt_early_cr_pattern; 275 struct { 276 uint8_t uclk : 1; 277 uint8_t fclk : 1; 278 uint8_t dcfclk : 1; 279 uint8_t dcfclk_ds: 1; 280 } clock_update_disable_mask; 281 }; 282 struct dc_dcc_surface_param { 283 struct dc_size surface_size; 284 enum surface_pixel_format format; 285 enum swizzle_mode_values swizzle_mode; 286 enum dc_scan_direction scan; 287 }; 288 289 struct dc_dcc_setting { 290 unsigned int max_compressed_blk_size; 291 unsigned int max_uncompressed_blk_size; 292 bool independent_64b_blks; 293 //These bitfields to be used starting with DCN 294 struct { 295 uint32_t dcc_256_64_64 : 1;//available in ASICs before DCN (the worst compression case) 296 uint32_t dcc_128_128_uncontrained : 1; //available in ASICs before DCN 297 uint32_t dcc_256_128_128 : 1; //available starting with DCN 298 uint32_t dcc_256_256_unconstrained : 1; //available in ASICs before DCN (the best compression case) 299 } dcc_controls; 300 }; 301 302 struct dc_surface_dcc_cap { 303 union { 304 struct { 305 struct dc_dcc_setting rgb; 306 } grph; 307 308 struct { 309 struct dc_dcc_setting luma; 310 struct dc_dcc_setting chroma; 311 } video; 312 }; 313 314 bool capable; 315 bool const_color_support; 316 }; 317 318 struct dc_static_screen_params { 319 struct { 320 bool force_trigger; 321 bool cursor_update; 322 bool surface_update; 323 bool overlay_update; 324 } triggers; 325 unsigned int num_frames; 326 }; 327 328 329 /* Surface update type is used by dc_update_surfaces_and_stream 330 * The update type is determined at the very beginning of the function based 331 * on parameters passed in and decides how much programming (or updating) is 332 * going to be done during the call. 333 * 334 * UPDATE_TYPE_FAST is used for really fast updates that do not require much 335 * logical calculations or hardware register programming. This update MUST be 336 * ISR safe on windows. Currently fast update will only be used to flip surface 337 * address. 338 * 339 * UPDATE_TYPE_MED is used for slower updates which require significant hw 340 * re-programming however do not affect bandwidth consumption or clock 341 * requirements. At present, this is the level at which front end updates 342 * that do not require us to run bw_calcs happen. These are in/out transfer func 343 * updates, viewport offset changes, recout size changes and pixel depth changes. 344 * This update can be done at ISR, but we want to minimize how often this happens. 345 * 346 * UPDATE_TYPE_FULL is slow. Really slow. This requires us to recalculate our 347 * bandwidth and clocks, possibly rearrange some pipes and reprogram anything front 348 * end related. Any time viewport dimensions, recout dimensions, scaling ratios or 349 * gamma need to be adjusted or pipe needs to be turned on (or disconnected) we do 350 * a full update. This cannot be done at ISR level and should be a rare event. 351 * Unless someone is stress testing mpo enter/exit, playing with colour or adjusting 352 * underscan we don't expect to see this call at all. 353 */ 354 355 enum surface_update_type { 356 UPDATE_TYPE_FAST, /* super fast, safe to execute in isr */ 357 UPDATE_TYPE_MED, /* ISR safe, most of programming needed, no bw/clk change*/ 358 UPDATE_TYPE_FULL, /* may need to shuffle resources */ 359 }; 360 361 /* Forward declaration*/ 362 struct dc; 363 struct dc_plane_state; 364 struct dc_state; 365 366 367 struct dc_cap_funcs { 368 bool (*get_dcc_compression_cap)(const struct dc *dc, 369 const struct dc_dcc_surface_param *input, 370 struct dc_surface_dcc_cap *output); 371 }; 372 373 struct link_training_settings; 374 375 union allow_lttpr_non_transparent_mode { 376 struct { 377 bool DP1_4A : 1; 378 bool DP2_0 : 1; 379 } bits; 380 unsigned char raw; 381 }; 382 383 /* Structure to hold configuration flags set by dm at dc creation. */ 384 struct dc_config { 385 bool gpu_vm_support; 386 bool disable_disp_pll_sharing; 387 bool fbc_support; 388 bool disable_fractional_pwm; 389 bool allow_seamless_boot_optimization; 390 bool seamless_boot_edp_requested; 391 bool edp_not_connected; 392 bool edp_no_power_sequencing; 393 bool force_enum_edp; 394 bool forced_clocks; 395 union allow_lttpr_non_transparent_mode allow_lttpr_non_transparent_mode; 396 bool multi_mon_pp_mclk_switch; 397 bool disable_dmcu; 398 bool enable_4to1MPC; 399 bool enable_windowed_mpo_odm; 400 bool forceHBR2CP2520; // Used for switching between test patterns TPS4 and CP2520 401 uint32_t allow_edp_hotplug_detection; 402 bool clamp_min_dcfclk; 403 uint64_t vblank_alignment_dto_params; 404 uint8_t vblank_alignment_max_frame_time_diff; 405 bool is_asymmetric_memory; 406 bool is_single_rank_dimm; 407 bool is_vmin_only_asic; 408 bool use_pipe_ctx_sync_logic; 409 bool ignore_dpref_ss; 410 bool enable_mipi_converter_optimization; 411 bool use_default_clock_table; 412 bool force_bios_enable_lttpr; 413 uint8_t force_bios_fixed_vs; 414 int sdpif_request_limit_words_per_umc; 415 bool use_old_fixed_vs_sequence; 416 bool disable_subvp_drr; 417 }; 418 419 enum visual_confirm { 420 VISUAL_CONFIRM_DISABLE = 0, 421 VISUAL_CONFIRM_SURFACE = 1, 422 VISUAL_CONFIRM_HDR = 2, 423 VISUAL_CONFIRM_MPCTREE = 4, 424 VISUAL_CONFIRM_PSR = 5, 425 VISUAL_CONFIRM_SWAPCHAIN = 6, 426 VISUAL_CONFIRM_FAMS = 7, 427 VISUAL_CONFIRM_SWIZZLE = 9, 428 VISUAL_CONFIRM_SUBVP = 14, 429 VISUAL_CONFIRM_MCLK_SWITCH = 16, 430 }; 431 432 enum dc_psr_power_opts { 433 psr_power_opt_invalid = 0x0, 434 psr_power_opt_smu_opt_static_screen = 0x1, 435 psr_power_opt_z10_static_screen = 0x10, 436 psr_power_opt_ds_disable_allow = 0x100, 437 }; 438 439 enum dml_hostvm_override_opts { 440 DML_HOSTVM_NO_OVERRIDE = 0x0, 441 DML_HOSTVM_OVERRIDE_FALSE = 0x1, 442 DML_HOSTVM_OVERRIDE_TRUE = 0x2, 443 }; 444 445 enum dcc_option { 446 DCC_ENABLE = 0, 447 DCC_DISABLE = 1, 448 DCC_HALF_REQ_DISALBE = 2, 449 }; 450 451 /** 452 * enum pipe_split_policy - Pipe split strategy supported by DCN 453 * 454 * This enum is used to define the pipe split policy supported by DCN. By 455 * default, DC favors MPC_SPLIT_DYNAMIC. 456 */ 457 enum pipe_split_policy { 458 /** 459 * @MPC_SPLIT_DYNAMIC: DC will automatically decide how to split the 460 * pipe in order to bring the best trade-off between performance and 461 * power consumption. This is the recommended option. 462 */ 463 MPC_SPLIT_DYNAMIC = 0, 464 465 /** 466 * @MPC_SPLIT_AVOID: Avoid pipe split, which means that DC will not 467 * try any sort of split optimization. 468 */ 469 MPC_SPLIT_AVOID = 1, 470 471 /** 472 * @MPC_SPLIT_AVOID_MULT_DISP: With this option, DC will only try to 473 * optimize the pipe utilization when using a single display; if the 474 * user connects to a second display, DC will avoid pipe split. 475 */ 476 MPC_SPLIT_AVOID_MULT_DISP = 2, 477 }; 478 479 enum wm_report_mode { 480 WM_REPORT_DEFAULT = 0, 481 WM_REPORT_OVERRIDE = 1, 482 }; 483 enum dtm_pstate{ 484 dtm_level_p0 = 0,/*highest voltage*/ 485 dtm_level_p1, 486 dtm_level_p2, 487 dtm_level_p3, 488 dtm_level_p4,/*when active_display_count = 0*/ 489 }; 490 491 enum dcn_pwr_state { 492 DCN_PWR_STATE_UNKNOWN = -1, 493 DCN_PWR_STATE_MISSION_MODE = 0, 494 DCN_PWR_STATE_LOW_POWER = 3, 495 }; 496 497 enum dcn_zstate_support_state { 498 DCN_ZSTATE_SUPPORT_UNKNOWN, 499 DCN_ZSTATE_SUPPORT_ALLOW, 500 DCN_ZSTATE_SUPPORT_ALLOW_Z8_ONLY, 501 DCN_ZSTATE_SUPPORT_ALLOW_Z8_Z10_ONLY, 502 DCN_ZSTATE_SUPPORT_ALLOW_Z10_ONLY, 503 DCN_ZSTATE_SUPPORT_DISALLOW, 504 }; 505 506 /** 507 * struct dc_clocks - DC pipe clocks 508 * 509 * For any clocks that may differ per pipe only the max is stored in this 510 * structure 511 */ 512 struct dc_clocks { 513 int dispclk_khz; 514 int actual_dispclk_khz; 515 int dppclk_khz; 516 int actual_dppclk_khz; 517 int disp_dpp_voltage_level_khz; 518 int dcfclk_khz; 519 int socclk_khz; 520 int dcfclk_deep_sleep_khz; 521 int fclk_khz; 522 int phyclk_khz; 523 int dramclk_khz; 524 bool p_state_change_support; 525 enum dcn_zstate_support_state zstate_support; 526 bool dtbclk_en; 527 int ref_dtbclk_khz; 528 bool fclk_p_state_change_support; 529 enum dcn_pwr_state pwr_state; 530 /* 531 * Elements below are not compared for the purposes of 532 * optimization required 533 */ 534 bool prev_p_state_change_support; 535 bool fclk_prev_p_state_change_support; 536 int num_ways; 537 538 /* 539 * @fw_based_mclk_switching 540 * 541 * DC has a mechanism that leverage the variable refresh rate to switch 542 * memory clock in cases that we have a large latency to achieve the 543 * memory clock change and a short vblank window. DC has some 544 * requirements to enable this feature, and this field describes if the 545 * system support or not such a feature. 546 */ 547 bool fw_based_mclk_switching; 548 bool fw_based_mclk_switching_shut_down; 549 int prev_num_ways; 550 enum dtm_pstate dtm_level; 551 int max_supported_dppclk_khz; 552 int max_supported_dispclk_khz; 553 int bw_dppclk_khz; /*a copy of dppclk_khz*/ 554 int bw_dispclk_khz; 555 }; 556 557 struct dc_bw_validation_profile { 558 bool enable; 559 560 unsigned long long total_ticks; 561 unsigned long long voltage_level_ticks; 562 unsigned long long watermark_ticks; 563 unsigned long long rq_dlg_ticks; 564 565 unsigned long long total_count; 566 unsigned long long skip_fast_count; 567 unsigned long long skip_pass_count; 568 unsigned long long skip_fail_count; 569 }; 570 571 #define BW_VAL_TRACE_SETUP() \ 572 unsigned long long end_tick = 0; \ 573 unsigned long long voltage_level_tick = 0; \ 574 unsigned long long watermark_tick = 0; \ 575 unsigned long long start_tick = dc->debug.bw_val_profile.enable ? \ 576 dm_get_timestamp(dc->ctx) : 0 577 578 #define BW_VAL_TRACE_COUNT() \ 579 if (dc->debug.bw_val_profile.enable) \ 580 dc->debug.bw_val_profile.total_count++ 581 582 #define BW_VAL_TRACE_SKIP(status) \ 583 if (dc->debug.bw_val_profile.enable) { \ 584 if (!voltage_level_tick) \ 585 voltage_level_tick = dm_get_timestamp(dc->ctx); \ 586 dc->debug.bw_val_profile.skip_ ## status ## _count++; \ 587 } 588 589 #define BW_VAL_TRACE_END_VOLTAGE_LEVEL() \ 590 if (dc->debug.bw_val_profile.enable) \ 591 voltage_level_tick = dm_get_timestamp(dc->ctx) 592 593 #define BW_VAL_TRACE_END_WATERMARKS() \ 594 if (dc->debug.bw_val_profile.enable) \ 595 watermark_tick = dm_get_timestamp(dc->ctx) 596 597 #define BW_VAL_TRACE_FINISH() \ 598 if (dc->debug.bw_val_profile.enable) { \ 599 end_tick = dm_get_timestamp(dc->ctx); \ 600 dc->debug.bw_val_profile.total_ticks += end_tick - start_tick; \ 601 dc->debug.bw_val_profile.voltage_level_ticks += voltage_level_tick - start_tick; \ 602 if (watermark_tick) { \ 603 dc->debug.bw_val_profile.watermark_ticks += watermark_tick - voltage_level_tick; \ 604 dc->debug.bw_val_profile.rq_dlg_ticks += end_tick - watermark_tick; \ 605 } \ 606 } 607 608 union mem_low_power_enable_options { 609 struct { 610 bool vga: 1; 611 bool i2c: 1; 612 bool dmcu: 1; 613 bool dscl: 1; 614 bool cm: 1; 615 bool mpc: 1; 616 bool optc: 1; 617 bool vpg: 1; 618 bool afmt: 1; 619 } bits; 620 uint32_t u32All; 621 }; 622 623 union root_clock_optimization_options { 624 struct { 625 bool dpp: 1; 626 bool dsc: 1; 627 bool hdmistream: 1; 628 bool hdmichar: 1; 629 bool dpstream: 1; 630 bool symclk32_se: 1; 631 bool symclk32_le: 1; 632 bool symclk_fe: 1; 633 bool physymclk: 1; 634 bool dpiasymclk: 1; 635 uint32_t reserved: 22; 636 } bits; 637 uint32_t u32All; 638 }; 639 640 union dpia_debug_options { 641 struct { 642 uint32_t disable_dpia:1; /* bit 0 */ 643 uint32_t force_non_lttpr:1; /* bit 1 */ 644 uint32_t extend_aux_rd_interval:1; /* bit 2 */ 645 uint32_t disable_mst_dsc_work_around:1; /* bit 3 */ 646 uint32_t enable_force_tbt3_work_around:1; /* bit 4 */ 647 uint32_t reserved:27; 648 } bits; 649 uint32_t raw; 650 }; 651 652 /* AUX wake work around options 653 * 0: enable/disable work around 654 * 1: use default timeout LINK_AUX_WAKE_TIMEOUT_MS 655 * 15-2: reserved 656 * 31-16: timeout in ms 657 */ 658 union aux_wake_wa_options { 659 struct { 660 uint32_t enable_wa : 1; 661 uint32_t use_default_timeout : 1; 662 uint32_t rsvd: 14; 663 uint32_t timeout_ms : 16; 664 } bits; 665 uint32_t raw; 666 }; 667 668 struct dc_debug_data { 669 uint32_t ltFailCount; 670 uint32_t i2cErrorCount; 671 uint32_t auxErrorCount; 672 }; 673 674 struct dc_phy_addr_space_config { 675 struct { 676 uint64_t start_addr; 677 uint64_t end_addr; 678 uint64_t fb_top; 679 uint64_t fb_offset; 680 uint64_t fb_base; 681 uint64_t agp_top; 682 uint64_t agp_bot; 683 uint64_t agp_base; 684 } system_aperture; 685 686 struct { 687 uint64_t page_table_start_addr; 688 uint64_t page_table_end_addr; 689 uint64_t page_table_base_addr; 690 bool base_addr_is_mc_addr; 691 } gart_config; 692 693 bool valid; 694 bool is_hvm_enabled; 695 uint64_t page_table_default_page_addr; 696 }; 697 698 struct dc_virtual_addr_space_config { 699 uint64_t page_table_base_addr; 700 uint64_t page_table_start_addr; 701 uint64_t page_table_end_addr; 702 uint32_t page_table_block_size_in_bytes; 703 uint8_t page_table_depth; // 1 = 1 level, 2 = 2 level, etc. 0 = invalid 704 }; 705 706 struct dc_bounding_box_overrides { 707 int sr_exit_time_ns; 708 int sr_enter_plus_exit_time_ns; 709 int sr_exit_z8_time_ns; 710 int sr_enter_plus_exit_z8_time_ns; 711 int urgent_latency_ns; 712 int percent_of_ideal_drambw; 713 int dram_clock_change_latency_ns; 714 int dummy_clock_change_latency_ns; 715 int fclk_clock_change_latency_ns; 716 /* This forces a hard min on the DCFCLK we use 717 * for DML. Unlike the debug option for forcing 718 * DCFCLK, this override affects watermark calculations 719 */ 720 int min_dcfclk_mhz; 721 }; 722 723 struct dc_state; 724 struct resource_pool; 725 struct dce_hwseq; 726 struct link_service; 727 728 /** 729 * struct dc_debug_options - DC debug struct 730 * 731 * This struct provides a simple mechanism for developers to change some 732 * configurations, enable/disable features, and activate extra debug options. 733 * This can be very handy to narrow down whether some specific feature is 734 * causing an issue or not. 735 */ 736 struct dc_debug_options { 737 bool native422_support; 738 bool disable_dsc; 739 enum visual_confirm visual_confirm; 740 int visual_confirm_rect_height; 741 742 bool sanity_checks; 743 bool max_disp_clk; 744 bool surface_trace; 745 bool timing_trace; 746 bool clock_trace; 747 bool validation_trace; 748 bool bandwidth_calcs_trace; 749 int max_downscale_src_width; 750 751 /* stutter efficiency related */ 752 bool disable_stutter; 753 bool use_max_lb; 754 enum dcc_option disable_dcc; 755 756 /** 757 * @pipe_split_policy: Define which pipe split policy is used by the 758 * display core. 759 */ 760 enum pipe_split_policy pipe_split_policy; 761 bool force_single_disp_pipe_split; 762 bool voltage_align_fclk; 763 bool disable_min_fclk; 764 765 bool disable_dfs_bypass; 766 bool disable_dpp_power_gate; 767 bool disable_hubp_power_gate; 768 bool disable_dsc_power_gate; 769 int dsc_min_slice_height_override; 770 int dsc_bpp_increment_div; 771 bool disable_pplib_wm_range; 772 enum wm_report_mode pplib_wm_report_mode; 773 unsigned int min_disp_clk_khz; 774 unsigned int min_dpp_clk_khz; 775 unsigned int min_dram_clk_khz; 776 int sr_exit_time_dpm0_ns; 777 int sr_enter_plus_exit_time_dpm0_ns; 778 int sr_exit_time_ns; 779 int sr_enter_plus_exit_time_ns; 780 int sr_exit_z8_time_ns; 781 int sr_enter_plus_exit_z8_time_ns; 782 int urgent_latency_ns; 783 uint32_t underflow_assert_delay_us; 784 int percent_of_ideal_drambw; 785 int dram_clock_change_latency_ns; 786 bool optimized_watermark; 787 int always_scale; 788 bool disable_pplib_clock_request; 789 bool disable_clock_gate; 790 bool disable_mem_low_power; 791 bool pstate_enabled; 792 bool disable_dmcu; 793 bool force_abm_enable; 794 bool disable_stereo_support; 795 bool vsr_support; 796 bool performance_trace; 797 bool az_endpoint_mute_only; 798 bool always_use_regamma; 799 bool recovery_enabled; 800 bool avoid_vbios_exec_table; 801 bool scl_reset_length10; 802 bool hdmi20_disable; 803 bool skip_detection_link_training; 804 uint32_t edid_read_retry_times; 805 unsigned int force_odm_combine; //bit vector based on otg inst 806 unsigned int seamless_boot_odm_combine; 807 unsigned int force_odm_combine_4to1; //bit vector based on otg inst 808 int minimum_z8_residency_time; 809 bool disable_z9_mpc; 810 unsigned int force_fclk_khz; 811 bool enable_tri_buf; 812 bool dmub_offload_enabled; 813 bool dmcub_emulation; 814 bool disable_idle_power_optimizations; 815 unsigned int mall_size_override; 816 unsigned int mall_additional_timer_percent; 817 bool mall_error_as_fatal; 818 bool dmub_command_table; /* for testing only */ 819 struct dc_bw_validation_profile bw_val_profile; 820 bool disable_fec; 821 bool disable_48mhz_pwrdwn; 822 /* This forces a hard min on the DCFCLK requested to SMU/PP 823 * watermarks are not affected. 824 */ 825 unsigned int force_min_dcfclk_mhz; 826 int dwb_fi_phase; 827 bool disable_timing_sync; 828 bool cm_in_bypass; 829 int force_clock_mode;/*every mode change.*/ 830 831 bool disable_dram_clock_change_vactive_support; 832 bool validate_dml_output; 833 bool enable_dmcub_surface_flip; 834 bool usbc_combo_phy_reset_wa; 835 bool enable_dram_clock_change_one_display_vactive; 836 /* TODO - remove once tested */ 837 bool legacy_dp2_lt; 838 bool set_mst_en_for_sst; 839 bool disable_uhbr; 840 bool force_dp2_lt_fallback_method; 841 bool ignore_cable_id; 842 union mem_low_power_enable_options enable_mem_low_power; 843 union root_clock_optimization_options root_clock_optimization; 844 bool hpo_optimization; 845 bool force_vblank_alignment; 846 847 /* Enable dmub aux for legacy ddc */ 848 bool enable_dmub_aux_for_legacy_ddc; 849 bool disable_fams; 850 /* FEC/PSR1 sequence enable delay in 100us */ 851 uint8_t fec_enable_delay_in100us; 852 bool enable_driver_sequence_debug; 853 enum det_size crb_alloc_policy; 854 int crb_alloc_policy_min_disp_count; 855 bool disable_z10; 856 bool enable_z9_disable_interface; 857 bool psr_skip_crtc_disable; 858 union dpia_debug_options dpia_debug; 859 bool disable_fixed_vs_aux_timeout_wa; 860 bool force_disable_subvp; 861 bool force_subvp_mclk_switch; 862 bool allow_sw_cursor_fallback; 863 unsigned int force_subvp_num_ways; 864 unsigned int force_mall_ss_num_ways; 865 bool alloc_extra_way_for_cursor; 866 uint32_t subvp_extra_lines; 867 bool force_usr_allow; 868 /* uses value at boot and disables switch */ 869 bool disable_dtb_ref_clk_switch; 870 bool extended_blank_optimization; 871 union aux_wake_wa_options aux_wake_wa; 872 uint32_t mst_start_top_delay; 873 uint8_t psr_power_use_phy_fsm; 874 enum dml_hostvm_override_opts dml_hostvm_override; 875 bool dml_disallow_alternate_prefetch_modes; 876 bool use_legacy_soc_bb_mechanism; 877 bool exit_idle_opt_for_cursor_updates; 878 bool enable_single_display_2to1_odm_policy; 879 bool enable_double_buffered_dsc_pg_support; 880 bool enable_dp_dig_pixel_rate_div_policy; 881 enum lttpr_mode lttpr_mode_override; 882 unsigned int dsc_delay_factor_wa_x1000; 883 unsigned int min_prefetch_in_strobe_ns; 884 bool disable_unbounded_requesting; 885 bool dig_fifo_off_in_blank; 886 bool temp_mst_deallocation_sequence; 887 bool override_dispclk_programming; 888 bool disable_fpo_optimizations; 889 bool support_eDP1_5; 890 uint32_t fpo_vactive_margin_us; 891 bool disable_fpo_vactive; 892 bool disable_boot_optimizations; 893 bool override_odm_optimization; 894 bool minimize_dispclk_using_odm; 895 bool disable_subvp_high_refresh; 896 bool disable_dp_plus_plus_wa; 897 uint32_t fpo_vactive_min_active_margin_us; 898 uint32_t fpo_vactive_max_blank_us; 899 }; 900 901 struct gpu_info_soc_bounding_box_v1_0; 902 struct dc { 903 struct dc_debug_options debug; 904 struct dc_versions versions; 905 struct dc_caps caps; 906 struct dc_cap_funcs cap_funcs; 907 struct dc_config config; 908 struct dc_bounding_box_overrides bb_overrides; 909 struct dc_bug_wa work_arounds; 910 struct dc_context *ctx; 911 struct dc_phy_addr_space_config vm_pa_config; 912 913 uint8_t link_count; 914 struct dc_link *links[MAX_PIPES * 2]; 915 struct link_service *link_srv; 916 917 struct dc_state *current_state; 918 struct resource_pool *res_pool; 919 920 struct clk_mgr *clk_mgr; 921 922 /* Display Engine Clock levels */ 923 struct dm_pp_clock_levels sclk_lvls; 924 925 /* Inputs into BW and WM calculations. */ 926 struct bw_calcs_dceip *bw_dceip; 927 struct bw_calcs_vbios *bw_vbios; 928 struct dcn_soc_bounding_box *dcn_soc; 929 struct dcn_ip_params *dcn_ip; 930 struct display_mode_lib dml; 931 932 /* HW functions */ 933 struct hw_sequencer_funcs hwss; 934 struct dce_hwseq *hwseq; 935 936 /* Require to optimize clocks and bandwidth for added/removed planes */ 937 bool optimized_required; 938 bool wm_optimized_required; 939 bool idle_optimizations_allowed; 940 bool enable_c20_dtm_b0; 941 942 /* Require to maintain clocks and bandwidth for UEFI enabled HW */ 943 944 /* FBC compressor */ 945 struct compressor *fbc_compressor; 946 947 struct dc_debug_data debug_data; 948 struct dpcd_vendor_signature vendor_signature; 949 950 const char *build_id; 951 struct vm_helper *vm_helper; 952 953 uint32_t *dcn_reg_offsets; 954 uint32_t *nbio_reg_offsets; 955 956 /* Scratch memory */ 957 struct { 958 struct { 959 /* 960 * For matching clock_limits table in driver with table 961 * from PMFW. 962 */ 963 struct _vcs_dpi_voltage_scaling_st clock_limits[DC__VOLTAGE_STATES]; 964 } update_bw_bounding_box; 965 } scratch; 966 }; 967 968 enum frame_buffer_mode { 969 FRAME_BUFFER_MODE_LOCAL_ONLY = 0, 970 FRAME_BUFFER_MODE_ZFB_ONLY, 971 FRAME_BUFFER_MODE_MIXED_ZFB_AND_LOCAL, 972 } ; 973 974 struct dchub_init_data { 975 int64_t zfb_phys_addr_base; 976 int64_t zfb_mc_base_addr; 977 uint64_t zfb_size_in_byte; 978 enum frame_buffer_mode fb_mode; 979 bool dchub_initialzied; 980 bool dchub_info_valid; 981 }; 982 983 struct dc_init_data { 984 struct hw_asic_id asic_id; 985 void *driver; /* ctx */ 986 struct cgs_device *cgs_device; 987 struct dc_bounding_box_overrides bb_overrides; 988 989 int num_virtual_links; 990 /* 991 * If 'vbios_override' not NULL, it will be called instead 992 * of the real VBIOS. Intended use is Diagnostics on FPGA. 993 */ 994 struct dc_bios *vbios_override; 995 enum dce_environment dce_environment; 996 997 struct dmub_offload_funcs *dmub_if; 998 struct dc_reg_helper_state *dmub_offload; 999 1000 struct dc_config flags; 1001 uint64_t log_mask; 1002 1003 struct dpcd_vendor_signature vendor_signature; 1004 bool force_smu_not_present; 1005 /* 1006 * IP offset for run time initializaion of register addresses 1007 * 1008 * DCN3.5+ will fail dc_create() if these fields are null for them. They are 1009 * applicable starting with DCN32/321 and are not used for ASICs upstreamed 1010 * before them. 1011 */ 1012 uint32_t *dcn_reg_offsets; 1013 uint32_t *nbio_reg_offsets; 1014 }; 1015 1016 struct dc_callback_init { 1017 struct cp_psp cp_psp; 1018 }; 1019 1020 struct dc *dc_create(const struct dc_init_data *init_params); 1021 void dc_hardware_init(struct dc *dc); 1022 1023 int dc_get_vmid_use_vector(struct dc *dc); 1024 void dc_setup_vm_context(struct dc *dc, struct dc_virtual_addr_space_config *va_config, int vmid); 1025 /* Returns the number of vmids supported */ 1026 int dc_setup_system_context(struct dc *dc, struct dc_phy_addr_space_config *pa_config); 1027 void dc_init_callbacks(struct dc *dc, 1028 const struct dc_callback_init *init_params); 1029 void dc_deinit_callbacks(struct dc *dc); 1030 void dc_destroy(struct dc **dc); 1031 1032 /* Surface Interfaces */ 1033 1034 enum { 1035 TRANSFER_FUNC_POINTS = 1025 1036 }; 1037 1038 struct dc_hdr_static_metadata { 1039 /* display chromaticities and white point in units of 0.00001 */ 1040 unsigned int chromaticity_green_x; 1041 unsigned int chromaticity_green_y; 1042 unsigned int chromaticity_blue_x; 1043 unsigned int chromaticity_blue_y; 1044 unsigned int chromaticity_red_x; 1045 unsigned int chromaticity_red_y; 1046 unsigned int chromaticity_white_point_x; 1047 unsigned int chromaticity_white_point_y; 1048 1049 uint32_t min_luminance; 1050 uint32_t max_luminance; 1051 uint32_t maximum_content_light_level; 1052 uint32_t maximum_frame_average_light_level; 1053 }; 1054 1055 enum dc_transfer_func_type { 1056 TF_TYPE_PREDEFINED, 1057 TF_TYPE_DISTRIBUTED_POINTS, 1058 TF_TYPE_BYPASS, 1059 TF_TYPE_HWPWL 1060 }; 1061 1062 struct dc_transfer_func_distributed_points { 1063 struct fixed31_32 red[TRANSFER_FUNC_POINTS]; 1064 struct fixed31_32 green[TRANSFER_FUNC_POINTS]; 1065 struct fixed31_32 blue[TRANSFER_FUNC_POINTS]; 1066 1067 uint16_t end_exponent; 1068 uint16_t x_point_at_y1_red; 1069 uint16_t x_point_at_y1_green; 1070 uint16_t x_point_at_y1_blue; 1071 }; 1072 1073 enum dc_transfer_func_predefined { 1074 TRANSFER_FUNCTION_SRGB, 1075 TRANSFER_FUNCTION_BT709, 1076 TRANSFER_FUNCTION_PQ, 1077 TRANSFER_FUNCTION_LINEAR, 1078 TRANSFER_FUNCTION_UNITY, 1079 TRANSFER_FUNCTION_HLG, 1080 TRANSFER_FUNCTION_HLG12, 1081 TRANSFER_FUNCTION_GAMMA22, 1082 TRANSFER_FUNCTION_GAMMA24, 1083 TRANSFER_FUNCTION_GAMMA26 1084 }; 1085 1086 1087 struct dc_transfer_func { 1088 struct kref refcount; 1089 enum dc_transfer_func_type type; 1090 enum dc_transfer_func_predefined tf; 1091 /* FP16 1.0 reference level in nits, default is 80 nits, only for PQ*/ 1092 uint32_t sdr_ref_white_level; 1093 union { 1094 struct pwl_params pwl; 1095 struct dc_transfer_func_distributed_points tf_pts; 1096 }; 1097 }; 1098 1099 1100 union dc_3dlut_state { 1101 struct { 1102 uint32_t initialized:1; /*if 3dlut is went through color module for initialization */ 1103 uint32_t rmu_idx_valid:1; /*if mux settings are valid*/ 1104 uint32_t rmu_mux_num:3; /*index of mux to use*/ 1105 uint32_t mpc_rmu0_mux:4; /*select mpcc on mux, one of the following : mpcc0, mpcc1, mpcc2, mpcc3*/ 1106 uint32_t mpc_rmu1_mux:4; 1107 uint32_t mpc_rmu2_mux:4; 1108 uint32_t reserved:15; 1109 } bits; 1110 uint32_t raw; 1111 }; 1112 1113 1114 struct dc_3dlut { 1115 struct kref refcount; 1116 struct tetrahedral_params lut_3d; 1117 struct fixed31_32 hdr_multiplier; 1118 union dc_3dlut_state state; 1119 }; 1120 /* 1121 * This structure is filled in by dc_surface_get_status and contains 1122 * the last requested address and the currently active address so the called 1123 * can determine if there are any outstanding flips 1124 */ 1125 struct dc_plane_status { 1126 struct dc_plane_address requested_address; 1127 struct dc_plane_address current_address; 1128 bool is_flip_pending; 1129 bool is_right_eye; 1130 }; 1131 1132 union surface_update_flags { 1133 1134 struct { 1135 uint32_t addr_update:1; 1136 /* Medium updates */ 1137 uint32_t dcc_change:1; 1138 uint32_t color_space_change:1; 1139 uint32_t horizontal_mirror_change:1; 1140 uint32_t per_pixel_alpha_change:1; 1141 uint32_t global_alpha_change:1; 1142 uint32_t hdr_mult:1; 1143 uint32_t rotation_change:1; 1144 uint32_t swizzle_change:1; 1145 uint32_t scaling_change:1; 1146 uint32_t position_change:1; 1147 uint32_t in_transfer_func_change:1; 1148 uint32_t input_csc_change:1; 1149 uint32_t coeff_reduction_change:1; 1150 uint32_t output_tf_change:1; 1151 uint32_t pixel_format_change:1; 1152 uint32_t plane_size_change:1; 1153 uint32_t gamut_remap_change:1; 1154 1155 /* Full updates */ 1156 uint32_t new_plane:1; 1157 uint32_t bpp_change:1; 1158 uint32_t gamma_change:1; 1159 uint32_t bandwidth_change:1; 1160 uint32_t clock_change:1; 1161 uint32_t stereo_format_change:1; 1162 uint32_t lut_3d:1; 1163 uint32_t tmz_changed:1; 1164 uint32_t full_update:1; 1165 } bits; 1166 1167 uint32_t raw; 1168 }; 1169 1170 struct dc_plane_state { 1171 struct dc_plane_address address; 1172 struct dc_plane_flip_time time; 1173 bool triplebuffer_flips; 1174 struct scaling_taps scaling_quality; 1175 struct rect src_rect; 1176 struct rect dst_rect; 1177 struct rect clip_rect; 1178 1179 struct plane_size plane_size; 1180 union dc_tiling_info tiling_info; 1181 1182 struct dc_plane_dcc_param dcc; 1183 1184 struct dc_gamma *gamma_correction; 1185 struct dc_transfer_func *in_transfer_func; 1186 struct dc_bias_and_scale *bias_and_scale; 1187 struct dc_csc_transform input_csc_color_matrix; 1188 struct fixed31_32 coeff_reduction_factor; 1189 struct fixed31_32 hdr_mult; 1190 struct colorspace_transform gamut_remap_matrix; 1191 1192 // TODO: No longer used, remove 1193 struct dc_hdr_static_metadata hdr_static_ctx; 1194 1195 enum dc_color_space color_space; 1196 1197 struct dc_3dlut *lut3d_func; 1198 struct dc_transfer_func *in_shaper_func; 1199 struct dc_transfer_func *blend_tf; 1200 1201 struct dc_transfer_func *gamcor_tf; 1202 enum surface_pixel_format format; 1203 enum dc_rotation_angle rotation; 1204 enum plane_stereo_format stereo_format; 1205 1206 bool is_tiling_rotated; 1207 bool per_pixel_alpha; 1208 bool pre_multiplied_alpha; 1209 bool global_alpha; 1210 int global_alpha_value; 1211 bool visible; 1212 bool flip_immediate; 1213 bool horizontal_mirror; 1214 int layer_index; 1215 1216 union surface_update_flags update_flags; 1217 bool flip_int_enabled; 1218 bool skip_manual_trigger; 1219 1220 /* private to DC core */ 1221 struct dc_plane_status status; 1222 struct dc_context *ctx; 1223 1224 /* HACK: Workaround for forcing full reprogramming under some conditions */ 1225 bool force_full_update; 1226 1227 bool is_phantom; // TODO: Change mall_stream_config into mall_plane_config instead 1228 1229 /* private to dc_surface.c */ 1230 enum dc_irq_source irq_source; 1231 struct kref refcount; 1232 struct tg_color visual_confirm_color; 1233 1234 bool is_statically_allocated; 1235 }; 1236 1237 struct dc_plane_info { 1238 struct plane_size plane_size; 1239 union dc_tiling_info tiling_info; 1240 struct dc_plane_dcc_param dcc; 1241 enum surface_pixel_format format; 1242 enum dc_rotation_angle rotation; 1243 enum plane_stereo_format stereo_format; 1244 enum dc_color_space color_space; 1245 bool horizontal_mirror; 1246 bool visible; 1247 bool per_pixel_alpha; 1248 bool pre_multiplied_alpha; 1249 bool global_alpha; 1250 int global_alpha_value; 1251 bool input_csc_enabled; 1252 int layer_index; 1253 }; 1254 1255 struct dc_scaling_info { 1256 struct rect src_rect; 1257 struct rect dst_rect; 1258 struct rect clip_rect; 1259 struct scaling_taps scaling_quality; 1260 }; 1261 1262 struct dc_surface_update { 1263 struct dc_plane_state *surface; 1264 1265 /* isr safe update parameters. null means no updates */ 1266 const struct dc_flip_addrs *flip_addr; 1267 const struct dc_plane_info *plane_info; 1268 const struct dc_scaling_info *scaling_info; 1269 struct fixed31_32 hdr_mult; 1270 /* following updates require alloc/sleep/spin that is not isr safe, 1271 * null means no updates 1272 */ 1273 const struct dc_gamma *gamma; 1274 const struct dc_transfer_func *in_transfer_func; 1275 1276 const struct dc_csc_transform *input_csc_color_matrix; 1277 const struct fixed31_32 *coeff_reduction_factor; 1278 const struct dc_transfer_func *func_shaper; 1279 const struct dc_3dlut *lut3d_func; 1280 const struct dc_transfer_func *blend_tf; 1281 const struct colorspace_transform *gamut_remap_matrix; 1282 }; 1283 1284 /* 1285 * Create a new surface with default parameters; 1286 */ 1287 struct dc_plane_state *dc_create_plane_state(struct dc *dc); 1288 const struct dc_plane_status *dc_plane_get_status( 1289 const struct dc_plane_state *plane_state); 1290 1291 void dc_plane_state_retain(struct dc_plane_state *plane_state); 1292 void dc_plane_state_release(struct dc_plane_state *plane_state); 1293 1294 void dc_gamma_retain(struct dc_gamma *dc_gamma); 1295 void dc_gamma_release(struct dc_gamma **dc_gamma); 1296 struct dc_gamma *dc_create_gamma(void); 1297 1298 void dc_transfer_func_retain(struct dc_transfer_func *dc_tf); 1299 void dc_transfer_func_release(struct dc_transfer_func *dc_tf); 1300 struct dc_transfer_func *dc_create_transfer_func(void); 1301 1302 struct dc_3dlut *dc_create_3dlut_func(void); 1303 void dc_3dlut_func_release(struct dc_3dlut *lut); 1304 void dc_3dlut_func_retain(struct dc_3dlut *lut); 1305 1306 void dc_post_update_surfaces_to_stream( 1307 struct dc *dc); 1308 1309 #include "dc_stream.h" 1310 1311 /** 1312 * struct dc_validation_set - Struct to store surface/stream associations for validation 1313 */ 1314 struct dc_validation_set { 1315 /** 1316 * @stream: Stream state properties 1317 */ 1318 struct dc_stream_state *stream; 1319 1320 /** 1321 * @plane_state: Surface state 1322 */ 1323 struct dc_plane_state *plane_states[MAX_SURFACES]; 1324 1325 /** 1326 * @plane_count: Total of active planes 1327 */ 1328 uint8_t plane_count; 1329 }; 1330 1331 bool dc_validate_boot_timing(const struct dc *dc, 1332 const struct dc_sink *sink, 1333 struct dc_crtc_timing *crtc_timing); 1334 1335 enum dc_status dc_validate_plane(struct dc *dc, const struct dc_plane_state *plane_state); 1336 1337 void get_clock_requirements_for_state(struct dc_state *state, struct AsicStateEx *info); 1338 1339 enum dc_status dc_validate_with_context(struct dc *dc, 1340 const struct dc_validation_set set[], 1341 int set_count, 1342 struct dc_state *context, 1343 bool fast_validate); 1344 1345 bool dc_set_generic_gpio_for_stereo(bool enable, 1346 struct gpio_service *gpio_service); 1347 1348 /* 1349 * fast_validate: we return after determining if we can support the new state, 1350 * but before we populate the programming info 1351 */ 1352 enum dc_status dc_validate_global_state( 1353 struct dc *dc, 1354 struct dc_state *new_ctx, 1355 bool fast_validate); 1356 1357 1358 void dc_resource_state_construct( 1359 const struct dc *dc, 1360 struct dc_state *dst_ctx); 1361 1362 bool dc_acquire_release_mpc_3dlut( 1363 struct dc *dc, bool acquire, 1364 struct dc_stream_state *stream, 1365 struct dc_3dlut **lut, 1366 struct dc_transfer_func **shaper); 1367 1368 void dc_resource_state_copy_construct( 1369 const struct dc_state *src_ctx, 1370 struct dc_state *dst_ctx); 1371 1372 void dc_resource_state_copy_construct_current( 1373 const struct dc *dc, 1374 struct dc_state *dst_ctx); 1375 1376 void dc_resource_state_destruct(struct dc_state *context); 1377 1378 bool dc_resource_is_dsc_encoding_supported(const struct dc *dc); 1379 1380 enum dc_status dc_commit_streams(struct dc *dc, 1381 struct dc_stream_state *streams[], 1382 uint8_t stream_count); 1383 1384 struct dc_state *dc_create_state(struct dc *dc); 1385 struct dc_state *dc_copy_state(struct dc_state *src_ctx); 1386 void dc_retain_state(struct dc_state *context); 1387 void dc_release_state(struct dc_state *context); 1388 1389 struct dc_plane_state *dc_get_surface_for_mpcc(struct dc *dc, 1390 struct dc_stream_state *stream, 1391 int mpcc_inst); 1392 1393 1394 uint32_t dc_get_opp_for_plane(struct dc *dc, struct dc_plane_state *plane); 1395 1396 /* The function returns minimum bandwidth required to drive a given timing 1397 * return - minimum required timing bandwidth in kbps. 1398 */ 1399 uint32_t dc_bandwidth_in_kbps_from_timing(const struct dc_crtc_timing *timing); 1400 1401 /* Link Interfaces */ 1402 /* 1403 * A link contains one or more sinks and their connected status. 1404 * The currently active signal type (HDMI, DP-SST, DP-MST) is also reported. 1405 */ 1406 struct dc_link { 1407 struct dc_sink *remote_sinks[MAX_SINKS_PER_LINK]; 1408 unsigned int sink_count; 1409 struct dc_sink *local_sink; 1410 unsigned int link_index; 1411 enum dc_connection_type type; 1412 enum signal_type connector_signal; 1413 enum dc_irq_source irq_source_hpd; 1414 enum dc_irq_source irq_source_hpd_rx;/* aka DP Short Pulse */ 1415 1416 bool is_hpd_filter_disabled; 1417 bool dp_ss_off; 1418 1419 /** 1420 * @link_state_valid: 1421 * 1422 * If there is no link and local sink, this variable should be set to 1423 * false. Otherwise, it should be set to true; usually, the function 1424 * core_link_enable_stream sets this field to true. 1425 */ 1426 bool link_state_valid; 1427 bool aux_access_disabled; 1428 bool sync_lt_in_progress; 1429 bool skip_stream_reenable; 1430 bool is_internal_display; 1431 /** @todo Rename. Flag an endpoint as having a programmable mapping to a DIG encoder. */ 1432 bool is_dig_mapping_flexible; 1433 bool hpd_status; /* HPD status of link without physical HPD pin. */ 1434 bool is_hpd_pending; /* Indicates a new received hpd */ 1435 bool is_automated; /* Indicates automated testing */ 1436 1437 bool edp_sink_present; 1438 1439 struct dp_trace dp_trace; 1440 1441 /* caps is the same as reported_link_cap. link_traing use 1442 * reported_link_cap. Will clean up. TODO 1443 */ 1444 struct dc_link_settings reported_link_cap; 1445 struct dc_link_settings verified_link_cap; 1446 struct dc_link_settings cur_link_settings; 1447 struct dc_lane_settings cur_lane_setting[LANE_COUNT_DP_MAX]; 1448 struct dc_link_settings preferred_link_setting; 1449 /* preferred_training_settings are override values that 1450 * come from DM. DM is responsible for the memory 1451 * management of the override pointers. 1452 */ 1453 struct dc_link_training_overrides preferred_training_settings; 1454 struct dp_audio_test_data audio_test_data; 1455 1456 uint8_t ddc_hw_inst; 1457 1458 uint8_t hpd_src; 1459 1460 uint8_t link_enc_hw_inst; 1461 /* DIG link encoder ID. Used as index in link encoder resource pool. 1462 * For links with fixed mapping to DIG, this is not changed after dc_link 1463 * object creation. 1464 */ 1465 enum engine_id eng_id; 1466 1467 bool test_pattern_enabled; 1468 union compliance_test_state compliance_test_state; 1469 1470 void *priv; 1471 1472 struct ddc_service *ddc; 1473 1474 enum dp_panel_mode panel_mode; 1475 bool aux_mode; 1476 1477 /* Private to DC core */ 1478 1479 const struct dc *dc; 1480 1481 struct dc_context *ctx; 1482 1483 struct panel_cntl *panel_cntl; 1484 struct link_encoder *link_enc; 1485 struct graphics_object_id link_id; 1486 /* Endpoint type distinguishes display endpoints which do not have entries 1487 * in the BIOS connector table from those that do. Helps when tracking link 1488 * encoder to display endpoint assignments. 1489 */ 1490 enum display_endpoint_type ep_type; 1491 union ddi_channel_mapping ddi_channel_mapping; 1492 struct connector_device_tag_info device_tag; 1493 struct dpcd_caps dpcd_caps; 1494 uint32_t dongle_max_pix_clk; 1495 unsigned short chip_caps; 1496 unsigned int dpcd_sink_count; 1497 struct hdcp_caps hdcp_caps; 1498 enum edp_revision edp_revision; 1499 union dpcd_sink_ext_caps dpcd_sink_ext_caps; 1500 1501 struct psr_settings psr_settings; 1502 1503 /* Drive settings read from integrated info table */ 1504 struct dc_lane_settings bios_forced_drive_settings; 1505 1506 /* Vendor specific LTTPR workaround variables */ 1507 uint8_t vendor_specific_lttpr_link_rate_wa; 1508 bool apply_vendor_specific_lttpr_link_rate_wa; 1509 1510 /* MST record stream using this link */ 1511 struct link_flags { 1512 bool dp_keep_receiver_powered; 1513 bool dp_skip_DID2; 1514 bool dp_skip_reset_segment; 1515 bool dp_skip_fs_144hz; 1516 bool dp_mot_reset_segment; 1517 /* Some USB4 docks do not handle turning off MST DSC once it has been enabled. */ 1518 bool dpia_mst_dsc_always_on; 1519 /* Forced DPIA into TBT3 compatibility mode. */ 1520 bool dpia_forced_tbt3_mode; 1521 bool dongle_mode_timing_override; 1522 bool blank_stream_on_ocs_change; 1523 } wa_flags; 1524 struct link_mst_stream_allocation_table mst_stream_alloc_table; 1525 1526 struct dc_link_status link_status; 1527 struct dprx_states dprx_states; 1528 1529 struct gpio *hpd_gpio; 1530 enum dc_link_fec_state fec_state; 1531 bool link_powered_externally; // Used to bypass hardware sequencing delays when panel is powered down forcibly 1532 1533 struct dc_panel_config panel_config; 1534 struct phy_state phy_state; 1535 // BW ALLOCATON USB4 ONLY 1536 struct dc_dpia_bw_alloc dpia_bw_alloc_config; 1537 }; 1538 1539 /* Return an enumerated dc_link. 1540 * dc_link order is constant and determined at 1541 * boot time. They cannot be created or destroyed. 1542 * Use dc_get_caps() to get number of links. 1543 */ 1544 struct dc_link *dc_get_link_at_index(struct dc *dc, uint32_t link_index); 1545 1546 /* Return instance id of the edp link. Inst 0 is primary edp link. */ 1547 bool dc_get_edp_link_panel_inst(const struct dc *dc, 1548 const struct dc_link *link, 1549 unsigned int *inst_out); 1550 1551 /* Return an array of link pointers to edp links. */ 1552 void dc_get_edp_links(const struct dc *dc, 1553 struct dc_link **edp_links, 1554 int *edp_num); 1555 1556 /* The function initiates detection handshake over the given link. It first 1557 * determines if there are display connections over the link. If so it initiates 1558 * detection protocols supported by the connected receiver device. The function 1559 * contains protocol specific handshake sequences which are sometimes mandatory 1560 * to establish a proper connection between TX and RX. So it is always 1561 * recommended to call this function as the first link operation upon HPD event 1562 * or power up event. Upon completion, the function will update link structure 1563 * in place based on latest RX capabilities. The function may also cause dpms 1564 * to be reset to off for all currently enabled streams to the link. It is DM's 1565 * responsibility to serialize detection and DPMS updates. 1566 * 1567 * @reason - Indicate which event triggers this detection. dc may customize 1568 * detection flow depending on the triggering events. 1569 * return false - if detection is not fully completed. This could happen when 1570 * there is an unrecoverable error during detection or detection is partially 1571 * completed (detection has been delegated to dm mst manager ie. 1572 * link->connection_type == dc_connection_mst_branch when returning false). 1573 * return true - detection is completed, link has been fully updated with latest 1574 * detection result. 1575 */ 1576 bool dc_link_detect(struct dc_link *link, enum dc_detect_reason reason); 1577 1578 struct dc_sink_init_data; 1579 1580 /* When link connection type is dc_connection_mst_branch, remote sink can be 1581 * added to the link. The interface creates a remote sink and associates it with 1582 * current link. The sink will be retained by link until remove remote sink is 1583 * called. 1584 * 1585 * @dc_link - link the remote sink will be added to. 1586 * @edid - byte array of EDID raw data. 1587 * @len - size of the edid in byte 1588 * @init_data - 1589 */ 1590 struct dc_sink *dc_link_add_remote_sink( 1591 struct dc_link *dc_link, 1592 const uint8_t *edid, 1593 int len, 1594 struct dc_sink_init_data *init_data); 1595 1596 /* Remove remote sink from a link with dc_connection_mst_branch connection type. 1597 * @link - link the sink should be removed from 1598 * @sink - sink to be removed. 1599 */ 1600 void dc_link_remove_remote_sink( 1601 struct dc_link *link, 1602 struct dc_sink *sink); 1603 1604 /* Enable HPD interrupt handler for a given link */ 1605 void dc_link_enable_hpd(const struct dc_link *link); 1606 1607 /* Disable HPD interrupt handler for a given link */ 1608 void dc_link_disable_hpd(const struct dc_link *link); 1609 1610 /* determine if there is a sink connected to the link 1611 * 1612 * @type - dc_connection_single if connected, dc_connection_none otherwise. 1613 * return - false if an unexpected error occurs, true otherwise. 1614 * 1615 * NOTE: This function doesn't detect downstream sink connections i.e 1616 * dc_connection_mst_branch, dc_connection_sst_branch. In this case, it will 1617 * return dc_connection_single if the branch device is connected despite of 1618 * downstream sink's connection status. 1619 */ 1620 bool dc_link_detect_connection_type(struct dc_link *link, 1621 enum dc_connection_type *type); 1622 1623 /* query current hpd pin value 1624 * return - true HPD is asserted (HPD high), false otherwise (HPD low) 1625 * 1626 */ 1627 bool dc_link_get_hpd_state(struct dc_link *link); 1628 1629 /* Getter for cached link status from given link */ 1630 const struct dc_link_status *dc_link_get_status(const struct dc_link *link); 1631 1632 /* enable/disable hardware HPD filter. 1633 * 1634 * @link - The link the HPD pin is associated with. 1635 * @enable = true - enable hardware HPD filter. HPD event will only queued to irq 1636 * handler once after no HPD change has been detected within dc default HPD 1637 * filtering interval since last HPD event. i.e if display keeps toggling hpd 1638 * pulses within default HPD interval, no HPD event will be received until HPD 1639 * toggles have stopped. Then HPD event will be queued to irq handler once after 1640 * dc default HPD filtering interval since last HPD event. 1641 * 1642 * @enable = false - disable hardware HPD filter. HPD event will be queued 1643 * immediately to irq handler after no HPD change has been detected within 1644 * IRQ_HPD (aka HPD short pulse) interval (i.e 2ms). 1645 */ 1646 void dc_link_enable_hpd_filter(struct dc_link *link, bool enable); 1647 1648 /* submit i2c read/write payloads through ddc channel 1649 * @link_index - index to a link with ddc in i2c mode 1650 * @cmd - i2c command structure 1651 * return - true if success, false otherwise. 1652 */ 1653 bool dc_submit_i2c( 1654 struct dc *dc, 1655 uint32_t link_index, 1656 struct i2c_command *cmd); 1657 1658 /* submit i2c read/write payloads through oem channel 1659 * @link_index - index to a link with ddc in i2c mode 1660 * @cmd - i2c command structure 1661 * return - true if success, false otherwise. 1662 */ 1663 bool dc_submit_i2c_oem( 1664 struct dc *dc, 1665 struct i2c_command *cmd); 1666 1667 enum aux_return_code_type; 1668 /* Attempt to transfer the given aux payload. This function does not perform 1669 * retries or handle error states. The reply is returned in the payload->reply 1670 * and the result through operation_result. Returns the number of bytes 1671 * transferred,or -1 on a failure. 1672 */ 1673 int dc_link_aux_transfer_raw(struct ddc_service *ddc, 1674 struct aux_payload *payload, 1675 enum aux_return_code_type *operation_result); 1676 1677 bool dc_is_oem_i2c_device_present( 1678 struct dc *dc, 1679 size_t slave_address 1680 ); 1681 1682 /* return true if the connected receiver supports the hdcp version */ 1683 bool dc_link_is_hdcp14(struct dc_link *link, enum signal_type signal); 1684 bool dc_link_is_hdcp22(struct dc_link *link, enum signal_type signal); 1685 1686 /* Notify DC about DP RX Interrupt (aka DP IRQ_HPD). 1687 * 1688 * TODO - When defer_handling is true the function will have a different purpose. 1689 * It no longer does complete hpd rx irq handling. We should create a separate 1690 * interface specifically for this case. 1691 * 1692 * Return: 1693 * true - Downstream port status changed. DM should call DC to do the 1694 * detection. 1695 * false - no change in Downstream port status. No further action required 1696 * from DM. 1697 */ 1698 bool dc_link_handle_hpd_rx_irq(struct dc_link *dc_link, 1699 union hpd_irq_data *hpd_irq_dpcd_data, bool *out_link_loss, 1700 bool defer_handling, bool *has_left_work); 1701 /* handle DP specs define test automation sequence*/ 1702 void dc_link_dp_handle_automated_test(struct dc_link *link); 1703 1704 /* handle DP Link loss sequence and try to recover RX link loss with best 1705 * effort 1706 */ 1707 void dc_link_dp_handle_link_loss(struct dc_link *link); 1708 1709 /* Determine if hpd rx irq should be handled or ignored 1710 * return true - hpd rx irq should be handled. 1711 * return false - it is safe to ignore hpd rx irq event 1712 */ 1713 bool dc_link_dp_allow_hpd_rx_irq(const struct dc_link *link); 1714 1715 /* Determine if link loss is indicated with a given hpd_irq_dpcd_data. 1716 * @link - link the hpd irq data associated with 1717 * @hpd_irq_dpcd_data - input hpd irq data 1718 * return - true if hpd irq data indicates a link lost 1719 */ 1720 bool dc_link_check_link_loss_status(struct dc_link *link, 1721 union hpd_irq_data *hpd_irq_dpcd_data); 1722 1723 /* Read hpd rx irq data from a given link 1724 * @link - link where the hpd irq data should be read from 1725 * @irq_data - output hpd irq data 1726 * return - DC_OK if hpd irq data is read successfully, otherwise hpd irq data 1727 * read has failed. 1728 */ 1729 enum dc_status dc_link_dp_read_hpd_rx_irq_data( 1730 struct dc_link *link, 1731 union hpd_irq_data *irq_data); 1732 1733 /* The function clears recorded DP RX states in the link. DM should call this 1734 * function when it is resuming from S3 power state to previously connected links. 1735 * 1736 * TODO - in the future we should consider to expand link resume interface to 1737 * support clearing previous rx states. So we don't have to rely on dm to call 1738 * this interface explicitly. 1739 */ 1740 void dc_link_clear_dprx_states(struct dc_link *link); 1741 1742 /* Destruct the mst topology of the link and reset the allocated payload table 1743 * 1744 * NOTE: this should only be called if DM chooses not to call dc_link_detect but 1745 * still wants to reset MST topology on an unplug event */ 1746 bool dc_link_reset_cur_dp_mst_topology(struct dc_link *link); 1747 1748 /* The function calculates effective DP link bandwidth when a given link is 1749 * using the given link settings. 1750 * 1751 * return - total effective link bandwidth in kbps. 1752 */ 1753 uint32_t dc_link_bandwidth_kbps( 1754 const struct dc_link *link, 1755 const struct dc_link_settings *link_setting); 1756 1757 /* The function takes a snapshot of current link resource allocation state 1758 * @dc: pointer to dc of the dm calling this 1759 * @map: a dc link resource snapshot defined internally to dc. 1760 * 1761 * DM needs to capture a snapshot of current link resource allocation mapping 1762 * and store it in its persistent storage. 1763 * 1764 * Some of the link resource is using first come first serve policy. 1765 * The allocation mapping depends on original hotplug order. This information 1766 * is lost after driver is loaded next time. The snapshot is used in order to 1767 * restore link resource to its previous state so user will get consistent 1768 * link capability allocation across reboot. 1769 * 1770 */ 1771 void dc_get_cur_link_res_map(const struct dc *dc, uint32_t *map); 1772 1773 /* This function restores link resource allocation state from a snapshot 1774 * @dc: pointer to dc of the dm calling this 1775 * @map: a dc link resource snapshot defined internally to dc. 1776 * 1777 * DM needs to call this function after initial link detection on boot and 1778 * before first commit streams to restore link resource allocation state 1779 * from previous boot session. 1780 * 1781 * Some of the link resource is using first come first serve policy. 1782 * The allocation mapping depends on original hotplug order. This information 1783 * is lost after driver is loaded next time. The snapshot is used in order to 1784 * restore link resource to its previous state so user will get consistent 1785 * link capability allocation across reboot. 1786 * 1787 */ 1788 void dc_restore_link_res_map(const struct dc *dc, uint32_t *map); 1789 1790 /* TODO: this is not meant to be exposed to DM. Should switch to stream update 1791 * interface i.e stream_update->dsc_config 1792 */ 1793 bool dc_link_update_dsc_config(struct pipe_ctx *pipe_ctx); 1794 1795 /* translate a raw link rate data to bandwidth in kbps */ 1796 uint32_t dc_link_bw_kbps_from_raw_frl_link_rate_data(const struct dc *dc, uint8_t bw); 1797 1798 /* determine the optimal bandwidth given link and required bw. 1799 * @link - current detected link 1800 * @req_bw - requested bandwidth in kbps 1801 * @link_settings - returned most optimal link settings that can fit the 1802 * requested bandwidth 1803 * return - false if link can't support requested bandwidth, true if link 1804 * settings is found. 1805 */ 1806 bool dc_link_decide_edp_link_settings(struct dc_link *link, 1807 struct dc_link_settings *link_settings, 1808 uint32_t req_bw); 1809 1810 /* return the max dp link settings can be driven by the link without considering 1811 * connected RX device and its capability 1812 */ 1813 bool dc_link_dp_get_max_link_enc_cap(const struct dc_link *link, 1814 struct dc_link_settings *max_link_enc_cap); 1815 1816 /* determine when the link is driving MST mode, what DP link channel coding 1817 * format will be used. The decision will remain unchanged until next HPD event. 1818 * 1819 * @link - a link with DP RX connection 1820 * return - if stream is committed to this link with MST signal type, type of 1821 * channel coding format dc will choose. 1822 */ 1823 enum dp_link_encoding dc_link_dp_mst_decide_link_encoding_format( 1824 const struct dc_link *link); 1825 1826 /* get max dp link settings the link can enable with all things considered. (i.e 1827 * TX/RX/Cable capabilities and dp override policies. 1828 * 1829 * @link - a link with DP RX connection 1830 * return - max dp link settings the link can enable. 1831 * 1832 */ 1833 const struct dc_link_settings *dc_link_get_link_cap(const struct dc_link *link); 1834 1835 /* Check if a RX (ex. DP sink, MST hub, passive or active dongle) is connected 1836 * to a link with dp connector signal type. 1837 * @link - a link with dp connector signal type 1838 * return - true if connected, false otherwise 1839 */ 1840 bool dc_link_is_dp_sink_present(struct dc_link *link); 1841 1842 /* Force DP lane settings update to main-link video signal and notify the change 1843 * to DP RX via DPCD. This is a debug interface used for video signal integrity 1844 * tuning purpose. The interface assumes link has already been enabled with DP 1845 * signal. 1846 * 1847 * @lt_settings - a container structure with desired hw_lane_settings 1848 */ 1849 void dc_link_set_drive_settings(struct dc *dc, 1850 struct link_training_settings *lt_settings, 1851 struct dc_link *link); 1852 1853 /* Enable a test pattern in Link or PHY layer in an active link for compliance 1854 * test or debugging purpose. The test pattern will remain until next un-plug. 1855 * 1856 * @link - active link with DP signal output enabled. 1857 * @test_pattern - desired test pattern to output. 1858 * NOTE: set to DP_TEST_PATTERN_VIDEO_MODE to disable previous test pattern. 1859 * @test_pattern_color_space - for video test pattern choose a desired color 1860 * space. 1861 * @p_link_settings - For PHY pattern choose a desired link settings 1862 * @p_custom_pattern - some test pattern will require a custom input to 1863 * customize some pattern details. Otherwise keep it to NULL. 1864 * @cust_pattern_size - size of the custom pattern input. 1865 * 1866 */ 1867 bool dc_link_dp_set_test_pattern( 1868 struct dc_link *link, 1869 enum dp_test_pattern test_pattern, 1870 enum dp_test_pattern_color_space test_pattern_color_space, 1871 const struct link_training_settings *p_link_settings, 1872 const unsigned char *p_custom_pattern, 1873 unsigned int cust_pattern_size); 1874 1875 /* Force DP link settings to always use a specific value until reboot to a 1876 * specific link. If link has already been enabled, the interface will also 1877 * switch to desired link settings immediately. This is a debug interface to 1878 * generic dp issue trouble shooting. 1879 */ 1880 void dc_link_set_preferred_link_settings(struct dc *dc, 1881 struct dc_link_settings *link_setting, 1882 struct dc_link *link); 1883 1884 /* Force DP link to customize a specific link training behavior by overriding to 1885 * standard DP specs defined protocol. This is a debug interface to trouble shoot 1886 * display specific link training issues or apply some display specific 1887 * workaround in link training. 1888 * 1889 * @link_settings - if not NULL, force preferred link settings to the link. 1890 * @lt_override - a set of override pointers. If any pointer is none NULL, dc 1891 * will apply this particular override in future link training. If NULL is 1892 * passed in, dc resets previous overrides. 1893 * NOTE: DM must keep the memory from override pointers until DM resets preferred 1894 * training settings. 1895 */ 1896 void dc_link_set_preferred_training_settings(struct dc *dc, 1897 struct dc_link_settings *link_setting, 1898 struct dc_link_training_overrides *lt_overrides, 1899 struct dc_link *link, 1900 bool skip_immediate_retrain); 1901 1902 /* return - true if FEC is supported with connected DP RX, false otherwise */ 1903 bool dc_link_is_fec_supported(const struct dc_link *link); 1904 1905 /* query FEC enablement policy to determine if FEC will be enabled by dc during 1906 * link enablement. 1907 * return - true if FEC should be enabled, false otherwise. 1908 */ 1909 bool dc_link_should_enable_fec(const struct dc_link *link); 1910 1911 /* determine lttpr mode the current link should be enabled with a specific link 1912 * settings. 1913 */ 1914 enum lttpr_mode dc_link_decide_lttpr_mode(struct dc_link *link, 1915 struct dc_link_settings *link_setting); 1916 1917 /* Force DP RX to update its power state. 1918 * NOTE: this interface doesn't update dp main-link. Calling this function will 1919 * cause DP TX main-link and DP RX power states out of sync. DM has to restore 1920 * RX power state back upon finish DM specific execution requiring DP RX in a 1921 * specific power state. 1922 * @on - true to set DP RX in D0 power state, false to set DP RX in D3 power 1923 * state. 1924 */ 1925 void dc_link_dp_receiver_power_ctrl(struct dc_link *link, bool on); 1926 1927 /* Force link to read base dp receiver caps from dpcd 000h - 00Fh and overwrite 1928 * current value read from extended receiver cap from 02200h - 0220Fh. 1929 * Some DP RX has problems of providing accurate DP receiver caps from extended 1930 * field, this interface is a workaround to revert link back to use base caps. 1931 */ 1932 void dc_link_overwrite_extended_receiver_cap( 1933 struct dc_link *link); 1934 1935 void dc_link_edp_panel_backlight_power_on(struct dc_link *link, 1936 bool wait_for_hpd); 1937 1938 /* Set backlight level of an embedded panel (eDP, LVDS). 1939 * backlight_pwm_u16_16 is unsigned 32 bit with 16 bit integer 1940 * and 16 bit fractional, where 1.0 is max backlight value. 1941 */ 1942 bool dc_link_set_backlight_level(const struct dc_link *dc_link, 1943 uint32_t backlight_pwm_u16_16, 1944 uint32_t frame_ramp); 1945 1946 /* Set/get nits-based backlight level of an embedded panel (eDP, LVDS). */ 1947 bool dc_link_set_backlight_level_nits(struct dc_link *link, 1948 bool isHDR, 1949 uint32_t backlight_millinits, 1950 uint32_t transition_time_in_ms); 1951 1952 bool dc_link_get_backlight_level_nits(struct dc_link *link, 1953 uint32_t *backlight_millinits, 1954 uint32_t *backlight_millinits_peak); 1955 1956 int dc_link_get_backlight_level(const struct dc_link *dc_link); 1957 1958 int dc_link_get_target_backlight_pwm(const struct dc_link *link); 1959 1960 bool dc_link_set_psr_allow_active(struct dc_link *dc_link, const bool *enable, 1961 bool wait, bool force_static, const unsigned int *power_opts); 1962 1963 bool dc_link_get_psr_state(const struct dc_link *dc_link, enum dc_psr_state *state); 1964 1965 bool dc_link_setup_psr(struct dc_link *dc_link, 1966 const struct dc_stream_state *stream, struct psr_config *psr_config, 1967 struct psr_context *psr_context); 1968 1969 /* On eDP links this function call will stall until T12 has elapsed. 1970 * If the panel is not in power off state, this function will return 1971 * immediately. 1972 */ 1973 bool dc_link_wait_for_t12(struct dc_link *link); 1974 1975 /* Determine if dp trace has been initialized to reflect upto date result * 1976 * return - true if trace is initialized and has valid data. False dp trace 1977 * doesn't have valid result. 1978 */ 1979 bool dc_dp_trace_is_initialized(struct dc_link *link); 1980 1981 /* Query a dp trace flag to indicate if the current dp trace data has been 1982 * logged before 1983 */ 1984 bool dc_dp_trace_is_logged(struct dc_link *link, 1985 bool in_detection); 1986 1987 /* Set dp trace flag to indicate whether DM has already logged the current dp 1988 * trace data. DM can set is_logged to true upon logging and check 1989 * dc_dp_trace_is_logged before logging to avoid logging the same result twice. 1990 */ 1991 void dc_dp_trace_set_is_logged_flag(struct dc_link *link, 1992 bool in_detection, 1993 bool is_logged); 1994 1995 /* Obtain driver time stamp for last dp link training end. The time stamp is 1996 * formatted based on dm_get_timestamp DM function. 1997 * @in_detection - true to get link training end time stamp of last link 1998 * training in detection sequence. false to get link training end time stamp 1999 * of last link training in commit (dpms) sequence 2000 */ 2001 unsigned long long dc_dp_trace_get_lt_end_timestamp(struct dc_link *link, 2002 bool in_detection); 2003 2004 /* Get how many link training attempts dc has done with latest sequence. 2005 * @in_detection - true to get link training count of last link 2006 * training in detection sequence. false to get link training count of last link 2007 * training in commit (dpms) sequence 2008 */ 2009 const struct dp_trace_lt_counts *dc_dp_trace_get_lt_counts(struct dc_link *link, 2010 bool in_detection); 2011 2012 /* Get how many link loss has happened since last link training attempts */ 2013 unsigned int dc_dp_trace_get_link_loss_count(struct dc_link *link); 2014 2015 /* 2016 * USB4 DPIA BW ALLOCATION PUBLIC FUNCTIONS 2017 */ 2018 /* 2019 * Send a request from DP-Tx requesting to allocate BW remotely after 2020 * allocating it locally. This will get processed by CM and a CB function 2021 * will be called. 2022 * 2023 * @link: pointer to the dc_link struct instance 2024 * @req_bw: The requested bw in Kbyte to allocated 2025 * 2026 * return: none 2027 */ 2028 void dc_link_set_usb4_req_bw_req(struct dc_link *link, int req_bw); 2029 2030 /* 2031 * Handle function for when the status of the Request above is complete. 2032 * We will find out the result of allocating on CM and update structs. 2033 * 2034 * @link: pointer to the dc_link struct instance 2035 * @bw: Allocated or Estimated BW depending on the result 2036 * @result: Response type 2037 * 2038 * return: none 2039 */ 2040 void dc_link_handle_usb4_bw_alloc_response(struct dc_link *link, 2041 uint8_t bw, uint8_t result); 2042 2043 /* 2044 * Handle the USB4 BW Allocation related functionality here: 2045 * Plug => Try to allocate max bw from timing parameters supported by the sink 2046 * Unplug => de-allocate bw 2047 * 2048 * @link: pointer to the dc_link struct instance 2049 * @peak_bw: Peak bw used by the link/sink 2050 * 2051 * return: allocated bw else return 0 2052 */ 2053 int dc_link_dp_dpia_handle_usb4_bandwidth_allocation_for_link( 2054 struct dc_link *link, int peak_bw); 2055 2056 /* 2057 * Validate the BW of all the valid DPIA links to make sure it doesn't exceed 2058 * available BW for each host router 2059 * 2060 * @dc: pointer to dc struct 2061 * @stream: pointer to all possible streams 2062 * @num_streams: number of valid DPIA streams 2063 * 2064 * return: TRUE if bw used by DPIAs doesn't exceed available BW else return FALSE 2065 */ 2066 bool dc_link_validate(struct dc *dc, const struct dc_stream_state *streams, 2067 const unsigned int count); 2068 2069 /* Sink Interfaces - A sink corresponds to a display output device */ 2070 2071 struct dc_container_id { 2072 // 128bit GUID in binary form 2073 unsigned char guid[16]; 2074 // 8 byte port ID -> ELD.PortID 2075 unsigned int portId[2]; 2076 // 128bit GUID in binary formufacturer name -> ELD.ManufacturerName 2077 unsigned short manufacturerName; 2078 // 2 byte product code -> ELD.ProductCode 2079 unsigned short productCode; 2080 }; 2081 2082 2083 struct dc_sink_dsc_caps { 2084 // 'true' if these are virtual DPCD's DSC caps (immediately upstream of sink in MST topology), 2085 // 'false' if they are sink's DSC caps 2086 bool is_virtual_dpcd_dsc; 2087 #if defined(CONFIG_DRM_AMD_DC_FP) 2088 // 'true' if MST topology supports DSC passthrough for sink 2089 // 'false' if MST topology does not support DSC passthrough 2090 bool is_dsc_passthrough_supported; 2091 #endif 2092 struct dsc_dec_dpcd_caps dsc_dec_caps; 2093 }; 2094 2095 struct dc_sink_fec_caps { 2096 bool is_rx_fec_supported; 2097 bool is_topology_fec_supported; 2098 }; 2099 2100 struct scdc_caps { 2101 union hdmi_scdc_manufacturer_OUI_data manufacturer_OUI; 2102 union hdmi_scdc_device_id_data device_id; 2103 }; 2104 2105 /* 2106 * The sink structure contains EDID and other display device properties 2107 */ 2108 struct dc_sink { 2109 enum signal_type sink_signal; 2110 struct dc_edid dc_edid; /* raw edid */ 2111 struct dc_edid_caps edid_caps; /* parse display caps */ 2112 struct dc_container_id *dc_container_id; 2113 uint32_t dongle_max_pix_clk; 2114 void *priv; 2115 struct stereo_3d_features features_3d[TIMING_3D_FORMAT_MAX]; 2116 bool converter_disable_audio; 2117 2118 struct scdc_caps scdc_caps; 2119 struct dc_sink_dsc_caps dsc_caps; 2120 struct dc_sink_fec_caps fec_caps; 2121 2122 bool is_vsc_sdp_colorimetry_supported; 2123 2124 /* private to DC core */ 2125 struct dc_link *link; 2126 struct dc_context *ctx; 2127 2128 uint32_t sink_id; 2129 2130 /* private to dc_sink.c */ 2131 // refcount must be the last member in dc_sink, since we want the 2132 // sink structure to be logically cloneable up to (but not including) 2133 // refcount 2134 struct kref refcount; 2135 }; 2136 2137 void dc_sink_retain(struct dc_sink *sink); 2138 void dc_sink_release(struct dc_sink *sink); 2139 2140 struct dc_sink_init_data { 2141 enum signal_type sink_signal; 2142 struct dc_link *link; 2143 uint32_t dongle_max_pix_clk; 2144 bool converter_disable_audio; 2145 }; 2146 2147 struct dc_sink *dc_sink_create(const struct dc_sink_init_data *init_params); 2148 2149 /* Newer interfaces */ 2150 struct dc_cursor { 2151 struct dc_plane_address address; 2152 struct dc_cursor_attributes attributes; 2153 }; 2154 2155 2156 /* Interrupt interfaces */ 2157 enum dc_irq_source dc_interrupt_to_irq_source( 2158 struct dc *dc, 2159 uint32_t src_id, 2160 uint32_t ext_id); 2161 bool dc_interrupt_set(struct dc *dc, enum dc_irq_source src, bool enable); 2162 void dc_interrupt_ack(struct dc *dc, enum dc_irq_source src); 2163 enum dc_irq_source dc_get_hpd_irq_source_at_index( 2164 struct dc *dc, uint32_t link_index); 2165 2166 void dc_notify_vsync_int_state(struct dc *dc, struct dc_stream_state *stream, bool enable); 2167 2168 /* Power Interfaces */ 2169 2170 void dc_set_power_state( 2171 struct dc *dc, 2172 enum dc_acpi_cm_power_state power_state); 2173 void dc_resume(struct dc *dc); 2174 2175 void dc_power_down_on_boot(struct dc *dc); 2176 2177 /* 2178 * HDCP Interfaces 2179 */ 2180 enum hdcp_message_status dc_process_hdcp_msg( 2181 enum signal_type signal, 2182 struct dc_link *link, 2183 struct hdcp_protection_message *message_info); 2184 bool dc_is_dmcu_initialized(struct dc *dc); 2185 2186 enum dc_status dc_set_clock(struct dc *dc, enum dc_clock_type clock_type, uint32_t clk_khz, uint32_t stepping); 2187 void dc_get_clock(struct dc *dc, enum dc_clock_type clock_type, struct dc_clock_config *clock_cfg); 2188 2189 bool dc_is_plane_eligible_for_idle_optimizations(struct dc *dc, struct dc_plane_state *plane, 2190 struct dc_cursor_attributes *cursor_attr); 2191 2192 void dc_allow_idle_optimizations(struct dc *dc, bool allow); 2193 2194 /* set min and max memory clock to lowest and highest DPM level, respectively */ 2195 void dc_unlock_memory_clock_frequency(struct dc *dc); 2196 2197 /* set min memory clock to the min required for current mode, max to maxDPM */ 2198 void dc_lock_memory_clock_frequency(struct dc *dc); 2199 2200 /* set soft max for memclk, to be used for AC/DC switching clock limitations */ 2201 void dc_enable_dcmode_clk_limit(struct dc *dc, bool enable); 2202 2203 /* cleanup on driver unload */ 2204 void dc_hardware_release(struct dc *dc); 2205 2206 /* disables fw based mclk switch */ 2207 void dc_mclk_switch_using_fw_based_vblank_stretch_shut_down(struct dc *dc); 2208 2209 bool dc_set_psr_allow_active(struct dc *dc, bool enable); 2210 void dc_z10_restore(const struct dc *dc); 2211 void dc_z10_save_init(struct dc *dc); 2212 2213 bool dc_is_dmub_outbox_supported(struct dc *dc); 2214 bool dc_enable_dmub_notifications(struct dc *dc); 2215 2216 void dc_enable_dmub_outbox(struct dc *dc); 2217 2218 bool dc_process_dmub_aux_transfer_async(struct dc *dc, 2219 uint32_t link_index, 2220 struct aux_payload *payload); 2221 2222 /* Get dc link index from dpia port index */ 2223 uint8_t get_link_index_from_dpia_port_index(const struct dc *dc, 2224 uint8_t dpia_port_index); 2225 2226 bool dc_process_dmub_set_config_async(struct dc *dc, 2227 uint32_t link_index, 2228 struct set_config_cmd_payload *payload, 2229 struct dmub_notification *notify); 2230 2231 enum dc_status dc_process_dmub_set_mst_slots(const struct dc *dc, 2232 uint32_t link_index, 2233 uint8_t mst_alloc_slots, 2234 uint8_t *mst_slots_in_use); 2235 2236 void dc_process_dmub_dpia_hpd_int_enable(const struct dc *dc, 2237 uint32_t hpd_int_enable); 2238 2239 void dc_print_dmub_diagnostic_data(const struct dc *dc); 2240 2241 /* DSC Interfaces */ 2242 #include "dc_dsc.h" 2243 2244 /* Disable acc mode Interfaces */ 2245 void dc_disable_accelerated_mode(struct dc *dc); 2246 2247 bool dc_is_timing_changed(struct dc_stream_state *cur_stream, 2248 struct dc_stream_state *new_stream); 2249 2250 #endif /* DC_INTERFACE_H_ */ 2251