1 /* 2 * Copyright 2012-14 Advanced Micro Devices, Inc. 3 * 4 * Permission is hereby granted, free of charge, to any person obtaining a 5 * copy of this software and associated documentation files (the "Software"), 6 * to deal in the Software without restriction, including without limitation 7 * the rights to use, copy, modify, merge, publish, distribute, sublicense, 8 * and/or sell copies of the Software, and to permit persons to whom the 9 * Software is furnished to do so, subject to the following conditions: 10 * 11 * The above copyright notice and this permission notice shall be included in 12 * all copies or substantial portions of the Software. 13 * 14 * THE SOFTWARE IS PROVIDED "AS IS", WITHOUT WARRANTY OF ANY KIND, EXPRESS OR 15 * IMPLIED, INCLUDING BUT NOT LIMITED TO THE WARRANTIES OF MERCHANTABILITY, 16 * FITNESS FOR A PARTICULAR PURPOSE AND NONINFRINGEMENT. IN NO EVENT SHALL 17 * THE COPYRIGHT HOLDER(S) OR AUTHOR(S) BE LIABLE FOR ANY CLAIM, DAMAGES OR 18 * OTHER LIABILITY, WHETHER IN AN ACTION OF CONTRACT, TORT OR OTHERWISE, 19 * ARISING FROM, OUT OF OR IN CONNECTION WITH THE SOFTWARE OR THE USE OR 20 * OTHER DEALINGS IN THE SOFTWARE. 21 * 22 * Authors: AMD 23 * 24 */ 25 26 #ifndef DC_INTERFACE_H_ 27 #define DC_INTERFACE_H_ 28 29 #include "dc_types.h" 30 #include "grph_object_defs.h" 31 #include "logger_types.h" 32 #if defined(CONFIG_DRM_AMD_DC_HDCP) 33 #include "hdcp_types.h" 34 #endif 35 #include "gpio_types.h" 36 #include "link_service_types.h" 37 #include "grph_object_ctrl_defs.h" 38 #include <inc/hw/opp.h> 39 40 #include "inc/hw_sequencer.h" 41 #include "inc/compressor.h" 42 #include "inc/hw/dmcu.h" 43 #include "dml/display_mode_lib.h" 44 45 #define DC_VER "3.2.112" 46 47 #define MAX_SURFACES 3 48 #define MAX_PLANES 6 49 #define MAX_STREAMS 6 50 #define MAX_SINKS_PER_LINK 4 51 52 /******************************************************************************* 53 * Display Core Interfaces 54 ******************************************************************************/ 55 struct dc_versions { 56 const char *dc_ver; 57 struct dmcu_version dmcu_version; 58 }; 59 60 enum dp_protocol_version { 61 DP_VERSION_1_4, 62 }; 63 64 enum dc_plane_type { 65 DC_PLANE_TYPE_INVALID, 66 DC_PLANE_TYPE_DCE_RGB, 67 DC_PLANE_TYPE_DCE_UNDERLAY, 68 DC_PLANE_TYPE_DCN_UNIVERSAL, 69 }; 70 71 struct dc_plane_cap { 72 enum dc_plane_type type; 73 uint32_t blends_with_above : 1; 74 uint32_t blends_with_below : 1; 75 uint32_t per_pixel_alpha : 1; 76 struct { 77 uint32_t argb8888 : 1; 78 uint32_t nv12 : 1; 79 uint32_t fp16 : 1; 80 uint32_t p010 : 1; 81 uint32_t ayuv : 1; 82 } pixel_format_support; 83 // max upscaling factor x1000 84 // upscaling factors are always >= 1 85 // for example, 1080p -> 8K is 4.0, or 4000 raw value 86 struct { 87 uint32_t argb8888; 88 uint32_t nv12; 89 uint32_t fp16; 90 } max_upscale_factor; 91 // max downscale factor x1000 92 // downscale factors are always <= 1 93 // for example, 8K -> 1080p is 0.25, or 250 raw value 94 struct { 95 uint32_t argb8888; 96 uint32_t nv12; 97 uint32_t fp16; 98 } max_downscale_factor; 99 // minimal width/height 100 uint32_t min_width; 101 uint32_t min_height; 102 }; 103 104 // Color management caps (DPP and MPC) 105 struct rom_curve_caps { 106 uint16_t srgb : 1; 107 uint16_t bt2020 : 1; 108 uint16_t gamma2_2 : 1; 109 uint16_t pq : 1; 110 uint16_t hlg : 1; 111 }; 112 113 struct dpp_color_caps { 114 uint16_t dcn_arch : 1; // all DCE generations treated the same 115 // input lut is different than most LUTs, just plain 256-entry lookup 116 uint16_t input_lut_shared : 1; // shared with DGAM 117 uint16_t icsc : 1; 118 uint16_t dgam_ram : 1; 119 uint16_t post_csc : 1; // before gamut remap 120 uint16_t gamma_corr : 1; 121 122 // hdr_mult and gamut remap always available in DPP (in that order) 123 // 3d lut implies shaper LUT, 124 // it may be shared with MPC - check MPC:shared_3d_lut flag 125 uint16_t hw_3d_lut : 1; 126 uint16_t ogam_ram : 1; // blnd gam 127 uint16_t ocsc : 1; 128 uint16_t dgam_rom_for_yuv : 1; 129 struct rom_curve_caps dgam_rom_caps; 130 struct rom_curve_caps ogam_rom_caps; 131 }; 132 133 struct mpc_color_caps { 134 uint16_t gamut_remap : 1; 135 uint16_t ogam_ram : 1; 136 uint16_t ocsc : 1; 137 uint16_t num_3dluts : 3; //3d lut always assumes a preceding shaper LUT 138 uint16_t shared_3d_lut:1; //can be in either DPP or MPC, but single instance 139 140 struct rom_curve_caps ogam_rom_caps; 141 }; 142 143 struct dc_color_caps { 144 struct dpp_color_caps dpp; 145 struct mpc_color_caps mpc; 146 }; 147 148 struct dc_caps { 149 uint32_t max_streams; 150 uint32_t max_links; 151 uint32_t max_audios; 152 uint32_t max_slave_planes; 153 uint32_t max_planes; 154 uint32_t max_downscale_ratio; 155 uint32_t i2c_speed_in_khz; 156 uint32_t i2c_speed_in_khz_hdcp; 157 uint32_t dmdata_alloc_size; 158 unsigned int max_cursor_size; 159 unsigned int max_video_width; 160 unsigned int min_horizontal_blanking_period; 161 int linear_pitch_alignment; 162 bool dcc_const_color; 163 bool dynamic_audio; 164 bool is_apu; 165 bool dual_link_dvi; 166 bool post_blend_color_processing; 167 bool force_dp_tps4_for_cp2520; 168 bool disable_dp_clk_share; 169 bool psp_setup_panel_mode; 170 bool extended_aux_timeout_support; 171 bool dmcub_support; 172 enum dp_protocol_version max_dp_protocol_version; 173 struct dc_plane_cap planes[MAX_PLANES]; 174 struct dc_color_caps color; 175 }; 176 177 struct dc_bug_wa { 178 bool no_connect_phy_config; 179 bool dedcn20_305_wa; 180 bool skip_clock_update; 181 bool lt_early_cr_pattern; 182 }; 183 184 struct dc_dcc_surface_param { 185 struct dc_size surface_size; 186 enum surface_pixel_format format; 187 enum swizzle_mode_values swizzle_mode; 188 enum dc_scan_direction scan; 189 }; 190 191 struct dc_dcc_setting { 192 unsigned int max_compressed_blk_size; 193 unsigned int max_uncompressed_blk_size; 194 bool independent_64b_blks; 195 #if defined(CONFIG_DRM_AMD_DC_DCN) 196 //These bitfields to be used starting with DCN 3.0 197 struct { 198 uint32_t dcc_256_64_64 : 1;//available in ASICs before DCN 3.0 (the worst compression case) 199 uint32_t dcc_128_128_uncontrained : 1; //available in ASICs before DCN 3.0 200 uint32_t dcc_256_128_128 : 1; //available starting with DCN 3.0 201 uint32_t dcc_256_256_unconstrained : 1; //available in ASICs before DCN 3.0 (the best compression case) 202 } dcc_controls; 203 #endif 204 }; 205 206 struct dc_surface_dcc_cap { 207 union { 208 struct { 209 struct dc_dcc_setting rgb; 210 } grph; 211 212 struct { 213 struct dc_dcc_setting luma; 214 struct dc_dcc_setting chroma; 215 } video; 216 }; 217 218 bool capable; 219 bool const_color_support; 220 }; 221 222 struct dc_static_screen_params { 223 struct { 224 bool force_trigger; 225 bool cursor_update; 226 bool surface_update; 227 bool overlay_update; 228 } triggers; 229 unsigned int num_frames; 230 }; 231 232 233 /* Surface update type is used by dc_update_surfaces_and_stream 234 * The update type is determined at the very beginning of the function based 235 * on parameters passed in and decides how much programming (or updating) is 236 * going to be done during the call. 237 * 238 * UPDATE_TYPE_FAST is used for really fast updates that do not require much 239 * logical calculations or hardware register programming. This update MUST be 240 * ISR safe on windows. Currently fast update will only be used to flip surface 241 * address. 242 * 243 * UPDATE_TYPE_MED is used for slower updates which require significant hw 244 * re-programming however do not affect bandwidth consumption or clock 245 * requirements. At present, this is the level at which front end updates 246 * that do not require us to run bw_calcs happen. These are in/out transfer func 247 * updates, viewport offset changes, recout size changes and pixel depth changes. 248 * This update can be done at ISR, but we want to minimize how often this happens. 249 * 250 * UPDATE_TYPE_FULL is slow. Really slow. This requires us to recalculate our 251 * bandwidth and clocks, possibly rearrange some pipes and reprogram anything front 252 * end related. Any time viewport dimensions, recout dimensions, scaling ratios or 253 * gamma need to be adjusted or pipe needs to be turned on (or disconnected) we do 254 * a full update. This cannot be done at ISR level and should be a rare event. 255 * Unless someone is stress testing mpo enter/exit, playing with colour or adjusting 256 * underscan we don't expect to see this call at all. 257 */ 258 259 enum surface_update_type { 260 UPDATE_TYPE_FAST, /* super fast, safe to execute in isr */ 261 UPDATE_TYPE_MED, /* ISR safe, most of programming needed, no bw/clk change*/ 262 UPDATE_TYPE_FULL, /* may need to shuffle resources */ 263 }; 264 265 /* Forward declaration*/ 266 struct dc; 267 struct dc_plane_state; 268 struct dc_state; 269 270 271 struct dc_cap_funcs { 272 bool (*get_dcc_compression_cap)(const struct dc *dc, 273 const struct dc_dcc_surface_param *input, 274 struct dc_surface_dcc_cap *output); 275 }; 276 277 struct link_training_settings; 278 279 280 /* Structure to hold configuration flags set by dm at dc creation. */ 281 struct dc_config { 282 bool gpu_vm_support; 283 bool disable_disp_pll_sharing; 284 bool fbc_support; 285 bool optimize_edp_link_rate; 286 bool disable_fractional_pwm; 287 bool allow_seamless_boot_optimization; 288 bool power_down_display_on_boot; 289 bool edp_not_connected; 290 bool force_enum_edp; 291 bool forced_clocks; 292 bool allow_lttpr_non_transparent_mode; 293 bool multi_mon_pp_mclk_switch; 294 bool disable_dmcu; 295 bool enable_4to1MPC; 296 #if defined(CONFIG_DRM_AMD_DC_DCN) 297 bool clamp_min_dcfclk; 298 #endif 299 }; 300 301 enum visual_confirm { 302 VISUAL_CONFIRM_DISABLE = 0, 303 VISUAL_CONFIRM_SURFACE = 1, 304 VISUAL_CONFIRM_HDR = 2, 305 VISUAL_CONFIRM_MPCTREE = 4, 306 VISUAL_CONFIRM_PSR = 5, 307 }; 308 309 enum dcc_option { 310 DCC_ENABLE = 0, 311 DCC_DISABLE = 1, 312 DCC_HALF_REQ_DISALBE = 2, 313 }; 314 315 enum pipe_split_policy { 316 MPC_SPLIT_DYNAMIC = 0, 317 MPC_SPLIT_AVOID = 1, 318 MPC_SPLIT_AVOID_MULT_DISP = 2, 319 }; 320 321 enum wm_report_mode { 322 WM_REPORT_DEFAULT = 0, 323 WM_REPORT_OVERRIDE = 1, 324 }; 325 enum dtm_pstate{ 326 dtm_level_p0 = 0,/*highest voltage*/ 327 dtm_level_p1, 328 dtm_level_p2, 329 dtm_level_p3, 330 dtm_level_p4,/*when active_display_count = 0*/ 331 }; 332 333 enum dcn_pwr_state { 334 DCN_PWR_STATE_UNKNOWN = -1, 335 DCN_PWR_STATE_MISSION_MODE = 0, 336 DCN_PWR_STATE_LOW_POWER = 3, 337 }; 338 339 /* 340 * For any clocks that may differ per pipe 341 * only the max is stored in this structure 342 */ 343 struct dc_clocks { 344 int dispclk_khz; 345 int actual_dispclk_khz; 346 int dppclk_khz; 347 int actual_dppclk_khz; 348 int disp_dpp_voltage_level_khz; 349 int dcfclk_khz; 350 int socclk_khz; 351 int dcfclk_deep_sleep_khz; 352 int fclk_khz; 353 int phyclk_khz; 354 int dramclk_khz; 355 bool p_state_change_support; 356 enum dcn_pwr_state pwr_state; 357 /* 358 * Elements below are not compared for the purposes of 359 * optimization required 360 */ 361 bool prev_p_state_change_support; 362 enum dtm_pstate dtm_level; 363 int max_supported_dppclk_khz; 364 int max_supported_dispclk_khz; 365 int bw_dppclk_khz; /*a copy of dppclk_khz*/ 366 int bw_dispclk_khz; 367 }; 368 369 struct dc_bw_validation_profile { 370 bool enable; 371 372 unsigned long long total_ticks; 373 unsigned long long voltage_level_ticks; 374 unsigned long long watermark_ticks; 375 unsigned long long rq_dlg_ticks; 376 377 unsigned long long total_count; 378 unsigned long long skip_fast_count; 379 unsigned long long skip_pass_count; 380 unsigned long long skip_fail_count; 381 }; 382 383 #define BW_VAL_TRACE_SETUP() \ 384 unsigned long long end_tick = 0; \ 385 unsigned long long voltage_level_tick = 0; \ 386 unsigned long long watermark_tick = 0; \ 387 unsigned long long start_tick = dc->debug.bw_val_profile.enable ? \ 388 dm_get_timestamp(dc->ctx) : 0 389 390 #define BW_VAL_TRACE_COUNT() \ 391 if (dc->debug.bw_val_profile.enable) \ 392 dc->debug.bw_val_profile.total_count++ 393 394 #define BW_VAL_TRACE_SKIP(status) \ 395 if (dc->debug.bw_val_profile.enable) { \ 396 if (!voltage_level_tick) \ 397 voltage_level_tick = dm_get_timestamp(dc->ctx); \ 398 dc->debug.bw_val_profile.skip_ ## status ## _count++; \ 399 } 400 401 #define BW_VAL_TRACE_END_VOLTAGE_LEVEL() \ 402 if (dc->debug.bw_val_profile.enable) \ 403 voltage_level_tick = dm_get_timestamp(dc->ctx) 404 405 #define BW_VAL_TRACE_END_WATERMARKS() \ 406 if (dc->debug.bw_val_profile.enable) \ 407 watermark_tick = dm_get_timestamp(dc->ctx) 408 409 #define BW_VAL_TRACE_FINISH() \ 410 if (dc->debug.bw_val_profile.enable) { \ 411 end_tick = dm_get_timestamp(dc->ctx); \ 412 dc->debug.bw_val_profile.total_ticks += end_tick - start_tick; \ 413 dc->debug.bw_val_profile.voltage_level_ticks += voltage_level_tick - start_tick; \ 414 if (watermark_tick) { \ 415 dc->debug.bw_val_profile.watermark_ticks += watermark_tick - voltage_level_tick; \ 416 dc->debug.bw_val_profile.rq_dlg_ticks += end_tick - watermark_tick; \ 417 } \ 418 } 419 420 union mem_low_power_enable_options { 421 struct { 422 bool i2c: 1; 423 bool dmcu: 1; 424 bool cm: 1; 425 bool mpc: 1; 426 bool optc: 1; 427 } bits; 428 uint32_t u32All; 429 }; 430 431 struct dc_debug_options { 432 enum visual_confirm visual_confirm; 433 bool sanity_checks; 434 bool max_disp_clk; 435 bool surface_trace; 436 bool timing_trace; 437 bool clock_trace; 438 bool validation_trace; 439 bool bandwidth_calcs_trace; 440 int max_downscale_src_width; 441 442 /* stutter efficiency related */ 443 bool disable_stutter; 444 bool use_max_lb; 445 enum dcc_option disable_dcc; 446 enum pipe_split_policy pipe_split_policy; 447 bool force_single_disp_pipe_split; 448 bool voltage_align_fclk; 449 450 bool disable_dfs_bypass; 451 bool disable_dpp_power_gate; 452 bool disable_hubp_power_gate; 453 bool disable_dsc_power_gate; 454 int dsc_min_slice_height_override; 455 int dsc_bpp_increment_div; 456 bool native422_support; 457 bool disable_pplib_wm_range; 458 enum wm_report_mode pplib_wm_report_mode; 459 unsigned int min_disp_clk_khz; 460 unsigned int min_dpp_clk_khz; 461 int sr_exit_time_dpm0_ns; 462 int sr_enter_plus_exit_time_dpm0_ns; 463 int sr_exit_time_ns; 464 int sr_enter_plus_exit_time_ns; 465 int urgent_latency_ns; 466 uint32_t underflow_assert_delay_us; 467 int percent_of_ideal_drambw; 468 int dram_clock_change_latency_ns; 469 bool optimized_watermark; 470 int always_scale; 471 bool disable_pplib_clock_request; 472 bool disable_clock_gate; 473 bool disable_mem_low_power; 474 bool disable_dmcu; 475 bool disable_psr; 476 bool force_abm_enable; 477 bool disable_stereo_support; 478 bool vsr_support; 479 bool performance_trace; 480 bool az_endpoint_mute_only; 481 bool always_use_regamma; 482 bool p010_mpo_support; 483 bool recovery_enabled; 484 bool avoid_vbios_exec_table; 485 bool scl_reset_length10; 486 bool hdmi20_disable; 487 bool skip_detection_link_training; 488 uint32_t edid_read_retry_times; 489 bool remove_disconnect_edp; 490 unsigned int force_odm_combine; //bit vector based on otg inst 491 #if defined(CONFIG_DRM_AMD_DC_DCN) 492 unsigned int force_odm_combine_4to1; //bit vector based on otg inst 493 #endif 494 unsigned int force_fclk_khz; 495 bool enable_tri_buf; 496 bool dmub_offload_enabled; 497 bool dmcub_emulation; 498 #if defined(CONFIG_DRM_AMD_DC_DCN) 499 bool disable_idle_power_optimizations; 500 #endif 501 bool dmub_command_table; /* for testing only */ 502 struct dc_bw_validation_profile bw_val_profile; 503 bool disable_fec; 504 bool disable_48mhz_pwrdwn; 505 /* This forces a hard min on the DCFCLK requested to SMU/PP 506 * watermarks are not affected. 507 */ 508 unsigned int force_min_dcfclk_mhz; 509 #if defined(CONFIG_DRM_AMD_DC_DCN) 510 int dwb_fi_phase; 511 #endif 512 bool disable_timing_sync; 513 bool cm_in_bypass; 514 int force_clock_mode;/*every mode change.*/ 515 516 bool disable_dram_clock_change_vactive_support; 517 bool validate_dml_output; 518 bool enable_dmcub_surface_flip; 519 bool usbc_combo_phy_reset_wa; 520 bool disable_dsc; 521 bool enable_dram_clock_change_one_display_vactive; 522 bool force_ignore_link_settings; 523 union mem_low_power_enable_options enable_mem_low_power; 524 }; 525 526 struct dc_debug_data { 527 uint32_t ltFailCount; 528 uint32_t i2cErrorCount; 529 uint32_t auxErrorCount; 530 }; 531 532 struct dc_phy_addr_space_config { 533 struct { 534 uint64_t start_addr; 535 uint64_t end_addr; 536 uint64_t fb_top; 537 uint64_t fb_offset; 538 uint64_t fb_base; 539 uint64_t agp_top; 540 uint64_t agp_bot; 541 uint64_t agp_base; 542 } system_aperture; 543 544 struct { 545 uint64_t page_table_start_addr; 546 uint64_t page_table_end_addr; 547 uint64_t page_table_base_addr; 548 } gart_config; 549 550 bool valid; 551 bool is_hvm_enabled; 552 uint64_t page_table_default_page_addr; 553 }; 554 555 struct dc_virtual_addr_space_config { 556 uint64_t page_table_base_addr; 557 uint64_t page_table_start_addr; 558 uint64_t page_table_end_addr; 559 uint32_t page_table_block_size_in_bytes; 560 uint8_t page_table_depth; // 1 = 1 level, 2 = 2 level, etc. 0 = invalid 561 }; 562 563 struct dc_bounding_box_overrides { 564 int sr_exit_time_ns; 565 int sr_enter_plus_exit_time_ns; 566 int urgent_latency_ns; 567 int percent_of_ideal_drambw; 568 int dram_clock_change_latency_ns; 569 int dummy_clock_change_latency_ns; 570 /* This forces a hard min on the DCFCLK we use 571 * for DML. Unlike the debug option for forcing 572 * DCFCLK, this override affects watermark calculations 573 */ 574 int min_dcfclk_mhz; 575 }; 576 577 struct dc_state; 578 struct resource_pool; 579 struct dce_hwseq; 580 struct gpu_info_soc_bounding_box_v1_0; 581 struct dc { 582 struct dc_versions versions; 583 struct dc_caps caps; 584 struct dc_cap_funcs cap_funcs; 585 struct dc_config config; 586 struct dc_debug_options debug; 587 struct dc_bounding_box_overrides bb_overrides; 588 struct dc_bug_wa work_arounds; 589 struct dc_context *ctx; 590 struct dc_phy_addr_space_config vm_pa_config; 591 592 uint8_t link_count; 593 struct dc_link *links[MAX_PIPES * 2]; 594 595 struct dc_state *current_state; 596 struct resource_pool *res_pool; 597 598 struct clk_mgr *clk_mgr; 599 600 /* Display Engine Clock levels */ 601 struct dm_pp_clock_levels sclk_lvls; 602 603 /* Inputs into BW and WM calculations. */ 604 struct bw_calcs_dceip *bw_dceip; 605 struct bw_calcs_vbios *bw_vbios; 606 #ifdef CONFIG_DRM_AMD_DC_DCN 607 struct dcn_soc_bounding_box *dcn_soc; 608 struct dcn_ip_params *dcn_ip; 609 struct display_mode_lib dml; 610 #endif 611 612 /* HW functions */ 613 struct hw_sequencer_funcs hwss; 614 struct dce_hwseq *hwseq; 615 616 /* Require to optimize clocks and bandwidth for added/removed planes */ 617 bool optimized_required; 618 bool wm_optimized_required; 619 #if defined(CONFIG_DRM_AMD_DC_DCN) 620 bool idle_optimizations_allowed; 621 #endif 622 623 /* Require to maintain clocks and bandwidth for UEFI enabled HW */ 624 int optimize_seamless_boot_streams; 625 626 /* FBC compressor */ 627 struct compressor *fbc_compressor; 628 629 struct dc_debug_data debug_data; 630 struct dpcd_vendor_signature vendor_signature; 631 632 const char *build_id; 633 struct vm_helper *vm_helper; 634 const struct gpu_info_soc_bounding_box_v1_0 *soc_bounding_box; 635 }; 636 637 enum frame_buffer_mode { 638 FRAME_BUFFER_MODE_LOCAL_ONLY = 0, 639 FRAME_BUFFER_MODE_ZFB_ONLY, 640 FRAME_BUFFER_MODE_MIXED_ZFB_AND_LOCAL, 641 } ; 642 643 struct dchub_init_data { 644 int64_t zfb_phys_addr_base; 645 int64_t zfb_mc_base_addr; 646 uint64_t zfb_size_in_byte; 647 enum frame_buffer_mode fb_mode; 648 bool dchub_initialzied; 649 bool dchub_info_valid; 650 }; 651 652 struct dc_init_data { 653 struct hw_asic_id asic_id; 654 void *driver; /* ctx */ 655 struct cgs_device *cgs_device; 656 struct dc_bounding_box_overrides bb_overrides; 657 658 int num_virtual_links; 659 /* 660 * If 'vbios_override' not NULL, it will be called instead 661 * of the real VBIOS. Intended use is Diagnostics on FPGA. 662 */ 663 struct dc_bios *vbios_override; 664 enum dce_environment dce_environment; 665 666 struct dmub_offload_funcs *dmub_if; 667 struct dc_reg_helper_state *dmub_offload; 668 669 struct dc_config flags; 670 uint64_t log_mask; 671 672 /** 673 * gpu_info FW provided soc bounding box struct or 0 if not 674 * available in FW 675 */ 676 const struct gpu_info_soc_bounding_box_v1_0 *soc_bounding_box; 677 struct dpcd_vendor_signature vendor_signature; 678 #if defined(CONFIG_DRM_AMD_DC_DCN) 679 bool force_smu_not_present; 680 #endif 681 bool force_ignore_link_settings; 682 }; 683 684 struct dc_callback_init { 685 #ifdef CONFIG_DRM_AMD_DC_HDCP 686 struct cp_psp cp_psp; 687 #else 688 uint8_t reserved; 689 #endif 690 }; 691 692 struct dc *dc_create(const struct dc_init_data *init_params); 693 void dc_hardware_init(struct dc *dc); 694 695 int dc_get_vmid_use_vector(struct dc *dc); 696 void dc_setup_vm_context(struct dc *dc, struct dc_virtual_addr_space_config *va_config, int vmid); 697 /* Returns the number of vmids supported */ 698 int dc_setup_system_context(struct dc *dc, struct dc_phy_addr_space_config *pa_config); 699 void dc_init_callbacks(struct dc *dc, 700 const struct dc_callback_init *init_params); 701 void dc_deinit_callbacks(struct dc *dc); 702 void dc_destroy(struct dc **dc); 703 704 /******************************************************************************* 705 * Surface Interfaces 706 ******************************************************************************/ 707 708 enum { 709 TRANSFER_FUNC_POINTS = 1025 710 }; 711 712 struct dc_hdr_static_metadata { 713 /* display chromaticities and white point in units of 0.00001 */ 714 unsigned int chromaticity_green_x; 715 unsigned int chromaticity_green_y; 716 unsigned int chromaticity_blue_x; 717 unsigned int chromaticity_blue_y; 718 unsigned int chromaticity_red_x; 719 unsigned int chromaticity_red_y; 720 unsigned int chromaticity_white_point_x; 721 unsigned int chromaticity_white_point_y; 722 723 uint32_t min_luminance; 724 uint32_t max_luminance; 725 uint32_t maximum_content_light_level; 726 uint32_t maximum_frame_average_light_level; 727 }; 728 729 enum dc_transfer_func_type { 730 TF_TYPE_PREDEFINED, 731 TF_TYPE_DISTRIBUTED_POINTS, 732 TF_TYPE_BYPASS, 733 TF_TYPE_HWPWL 734 }; 735 736 struct dc_transfer_func_distributed_points { 737 struct fixed31_32 red[TRANSFER_FUNC_POINTS]; 738 struct fixed31_32 green[TRANSFER_FUNC_POINTS]; 739 struct fixed31_32 blue[TRANSFER_FUNC_POINTS]; 740 741 uint16_t end_exponent; 742 uint16_t x_point_at_y1_red; 743 uint16_t x_point_at_y1_green; 744 uint16_t x_point_at_y1_blue; 745 }; 746 747 enum dc_transfer_func_predefined { 748 TRANSFER_FUNCTION_SRGB, 749 TRANSFER_FUNCTION_BT709, 750 TRANSFER_FUNCTION_PQ, 751 TRANSFER_FUNCTION_LINEAR, 752 TRANSFER_FUNCTION_UNITY, 753 TRANSFER_FUNCTION_HLG, 754 TRANSFER_FUNCTION_HLG12, 755 TRANSFER_FUNCTION_GAMMA22, 756 TRANSFER_FUNCTION_GAMMA24, 757 TRANSFER_FUNCTION_GAMMA26 758 }; 759 760 761 struct dc_transfer_func { 762 struct kref refcount; 763 enum dc_transfer_func_type type; 764 enum dc_transfer_func_predefined tf; 765 /* FP16 1.0 reference level in nits, default is 80 nits, only for PQ*/ 766 uint32_t sdr_ref_white_level; 767 union { 768 struct pwl_params pwl; 769 struct dc_transfer_func_distributed_points tf_pts; 770 }; 771 }; 772 773 774 union dc_3dlut_state { 775 struct { 776 uint32_t initialized:1; /*if 3dlut is went through color module for initialization */ 777 uint32_t rmu_idx_valid:1; /*if mux settings are valid*/ 778 uint32_t rmu_mux_num:3; /*index of mux to use*/ 779 uint32_t mpc_rmu0_mux:4; /*select mpcc on mux, one of the following : mpcc0, mpcc1, mpcc2, mpcc3*/ 780 uint32_t mpc_rmu1_mux:4; 781 uint32_t mpc_rmu2_mux:4; 782 uint32_t reserved:15; 783 } bits; 784 uint32_t raw; 785 }; 786 787 788 struct dc_3dlut { 789 struct kref refcount; 790 struct tetrahedral_params lut_3d; 791 struct fixed31_32 hdr_multiplier; 792 union dc_3dlut_state state; 793 }; 794 /* 795 * This structure is filled in by dc_surface_get_status and contains 796 * the last requested address and the currently active address so the called 797 * can determine if there are any outstanding flips 798 */ 799 struct dc_plane_status { 800 struct dc_plane_address requested_address; 801 struct dc_plane_address current_address; 802 bool is_flip_pending; 803 bool is_right_eye; 804 }; 805 806 union surface_update_flags { 807 808 struct { 809 uint32_t addr_update:1; 810 /* Medium updates */ 811 uint32_t dcc_change:1; 812 uint32_t color_space_change:1; 813 uint32_t horizontal_mirror_change:1; 814 uint32_t per_pixel_alpha_change:1; 815 uint32_t global_alpha_change:1; 816 uint32_t hdr_mult:1; 817 uint32_t rotation_change:1; 818 uint32_t swizzle_change:1; 819 uint32_t scaling_change:1; 820 uint32_t position_change:1; 821 uint32_t in_transfer_func_change:1; 822 uint32_t input_csc_change:1; 823 uint32_t coeff_reduction_change:1; 824 uint32_t output_tf_change:1; 825 uint32_t pixel_format_change:1; 826 uint32_t plane_size_change:1; 827 uint32_t gamut_remap_change:1; 828 829 /* Full updates */ 830 uint32_t new_plane:1; 831 uint32_t bpp_change:1; 832 uint32_t gamma_change:1; 833 uint32_t bandwidth_change:1; 834 uint32_t clock_change:1; 835 uint32_t stereo_format_change:1; 836 uint32_t full_update:1; 837 } bits; 838 839 uint32_t raw; 840 }; 841 842 struct dc_plane_state { 843 struct dc_plane_address address; 844 struct dc_plane_flip_time time; 845 bool triplebuffer_flips; 846 struct scaling_taps scaling_quality; 847 struct rect src_rect; 848 struct rect dst_rect; 849 struct rect clip_rect; 850 851 struct plane_size plane_size; 852 union dc_tiling_info tiling_info; 853 854 struct dc_plane_dcc_param dcc; 855 856 struct dc_gamma *gamma_correction; 857 struct dc_transfer_func *in_transfer_func; 858 struct dc_bias_and_scale *bias_and_scale; 859 struct dc_csc_transform input_csc_color_matrix; 860 struct fixed31_32 coeff_reduction_factor; 861 struct fixed31_32 hdr_mult; 862 struct colorspace_transform gamut_remap_matrix; 863 864 // TODO: No longer used, remove 865 struct dc_hdr_static_metadata hdr_static_ctx; 866 867 enum dc_color_space color_space; 868 869 struct dc_3dlut *lut3d_func; 870 struct dc_transfer_func *in_shaper_func; 871 struct dc_transfer_func *blend_tf; 872 873 #if defined(CONFIG_DRM_AMD_DC_DCN) 874 struct dc_transfer_func *gamcor_tf; 875 #endif 876 enum surface_pixel_format format; 877 enum dc_rotation_angle rotation; 878 enum plane_stereo_format stereo_format; 879 880 bool is_tiling_rotated; 881 bool per_pixel_alpha; 882 bool global_alpha; 883 int global_alpha_value; 884 bool visible; 885 bool flip_immediate; 886 bool horizontal_mirror; 887 int layer_index; 888 889 union surface_update_flags update_flags; 890 /* private to DC core */ 891 struct dc_plane_status status; 892 struct dc_context *ctx; 893 894 /* HACK: Workaround for forcing full reprogramming under some conditions */ 895 bool force_full_update; 896 897 /* private to dc_surface.c */ 898 enum dc_irq_source irq_source; 899 struct kref refcount; 900 }; 901 902 struct dc_plane_info { 903 struct plane_size plane_size; 904 union dc_tiling_info tiling_info; 905 struct dc_plane_dcc_param dcc; 906 enum surface_pixel_format format; 907 enum dc_rotation_angle rotation; 908 enum plane_stereo_format stereo_format; 909 enum dc_color_space color_space; 910 bool horizontal_mirror; 911 bool visible; 912 bool per_pixel_alpha; 913 bool global_alpha; 914 int global_alpha_value; 915 bool input_csc_enabled; 916 int layer_index; 917 }; 918 919 struct dc_scaling_info { 920 struct rect src_rect; 921 struct rect dst_rect; 922 struct rect clip_rect; 923 struct scaling_taps scaling_quality; 924 }; 925 926 struct dc_surface_update { 927 struct dc_plane_state *surface; 928 929 /* isr safe update parameters. null means no updates */ 930 const struct dc_flip_addrs *flip_addr; 931 const struct dc_plane_info *plane_info; 932 const struct dc_scaling_info *scaling_info; 933 struct fixed31_32 hdr_mult; 934 /* following updates require alloc/sleep/spin that is not isr safe, 935 * null means no updates 936 */ 937 const struct dc_gamma *gamma; 938 const struct dc_transfer_func *in_transfer_func; 939 940 const struct dc_csc_transform *input_csc_color_matrix; 941 const struct fixed31_32 *coeff_reduction_factor; 942 const struct dc_transfer_func *func_shaper; 943 const struct dc_3dlut *lut3d_func; 944 const struct dc_transfer_func *blend_tf; 945 const struct colorspace_transform *gamut_remap_matrix; 946 }; 947 948 /* 949 * Create a new surface with default parameters; 950 */ 951 struct dc_plane_state *dc_create_plane_state(struct dc *dc); 952 const struct dc_plane_status *dc_plane_get_status( 953 const struct dc_plane_state *plane_state); 954 955 void dc_plane_state_retain(struct dc_plane_state *plane_state); 956 void dc_plane_state_release(struct dc_plane_state *plane_state); 957 958 void dc_gamma_retain(struct dc_gamma *dc_gamma); 959 void dc_gamma_release(struct dc_gamma **dc_gamma); 960 struct dc_gamma *dc_create_gamma(void); 961 962 void dc_transfer_func_retain(struct dc_transfer_func *dc_tf); 963 void dc_transfer_func_release(struct dc_transfer_func *dc_tf); 964 struct dc_transfer_func *dc_create_transfer_func(void); 965 966 struct dc_3dlut *dc_create_3dlut_func(void); 967 void dc_3dlut_func_release(struct dc_3dlut *lut); 968 void dc_3dlut_func_retain(struct dc_3dlut *lut); 969 /* 970 * This structure holds a surface address. There could be multiple addresses 971 * in cases such as Stereo 3D, Planar YUV, etc. Other per-flip attributes such 972 * as frame durations and DCC format can also be set. 973 */ 974 struct dc_flip_addrs { 975 struct dc_plane_address address; 976 unsigned int flip_timestamp_in_us; 977 bool flip_immediate; 978 /* TODO: add flip duration for FreeSync */ 979 bool triplebuffer_flips; 980 }; 981 982 void dc_post_update_surfaces_to_stream( 983 struct dc *dc); 984 985 #include "dc_stream.h" 986 987 /* 988 * Structure to store surface/stream associations for validation 989 */ 990 struct dc_validation_set { 991 struct dc_stream_state *stream; 992 struct dc_plane_state *plane_states[MAX_SURFACES]; 993 uint8_t plane_count; 994 }; 995 996 bool dc_validate_seamless_boot_timing(const struct dc *dc, 997 const struct dc_sink *sink, 998 struct dc_crtc_timing *crtc_timing); 999 1000 enum dc_status dc_validate_plane(struct dc *dc, const struct dc_plane_state *plane_state); 1001 1002 void get_clock_requirements_for_state(struct dc_state *state, struct AsicStateEx *info); 1003 1004 bool dc_set_generic_gpio_for_stereo(bool enable, 1005 struct gpio_service *gpio_service); 1006 1007 /* 1008 * fast_validate: we return after determining if we can support the new state, 1009 * but before we populate the programming info 1010 */ 1011 enum dc_status dc_validate_global_state( 1012 struct dc *dc, 1013 struct dc_state *new_ctx, 1014 bool fast_validate); 1015 1016 1017 void dc_resource_state_construct( 1018 const struct dc *dc, 1019 struct dc_state *dst_ctx); 1020 1021 #if defined(CONFIG_DRM_AMD_DC_DCN) 1022 bool dc_acquire_release_mpc_3dlut( 1023 struct dc *dc, bool acquire, 1024 struct dc_stream_state *stream, 1025 struct dc_3dlut **lut, 1026 struct dc_transfer_func **shaper); 1027 #endif 1028 1029 void dc_resource_state_copy_construct( 1030 const struct dc_state *src_ctx, 1031 struct dc_state *dst_ctx); 1032 1033 void dc_resource_state_copy_construct_current( 1034 const struct dc *dc, 1035 struct dc_state *dst_ctx); 1036 1037 void dc_resource_state_destruct(struct dc_state *context); 1038 1039 bool dc_resource_is_dsc_encoding_supported(const struct dc *dc); 1040 1041 /* 1042 * TODO update to make it about validation sets 1043 * Set up streams and links associated to drive sinks 1044 * The streams parameter is an absolute set of all active streams. 1045 * 1046 * After this call: 1047 * Phy, Encoder, Timing Generator are programmed and enabled. 1048 * New streams are enabled with blank stream; no memory read. 1049 */ 1050 bool dc_commit_state(struct dc *dc, struct dc_state *context); 1051 1052 void dc_power_down_on_boot(struct dc *dc); 1053 1054 struct dc_state *dc_create_state(struct dc *dc); 1055 struct dc_state *dc_copy_state(struct dc_state *src_ctx); 1056 void dc_retain_state(struct dc_state *context); 1057 void dc_release_state(struct dc_state *context); 1058 1059 /******************************************************************************* 1060 * Link Interfaces 1061 ******************************************************************************/ 1062 1063 struct dpcd_caps { 1064 union dpcd_rev dpcd_rev; 1065 union max_lane_count max_ln_count; 1066 union max_down_spread max_down_spread; 1067 union dprx_feature dprx_feature; 1068 1069 /* valid only for eDP v1.4 or higher*/ 1070 uint8_t edp_supported_link_rates_count; 1071 enum dc_link_rate edp_supported_link_rates[8]; 1072 1073 /* dongle type (DP converter, CV smart dongle) */ 1074 enum display_dongle_type dongle_type; 1075 /* branch device or sink device */ 1076 bool is_branch_dev; 1077 /* Dongle's downstream count. */ 1078 union sink_count sink_count; 1079 /* If dongle_type == DISPLAY_DONGLE_DP_HDMI_CONVERTER, 1080 indicates 'Frame Sequential-to-lllFrame Pack' conversion capability.*/ 1081 struct dc_dongle_caps dongle_caps; 1082 1083 uint32_t sink_dev_id; 1084 int8_t sink_dev_id_str[6]; 1085 int8_t sink_hw_revision; 1086 int8_t sink_fw_revision[2]; 1087 1088 uint32_t branch_dev_id; 1089 int8_t branch_dev_name[6]; 1090 int8_t branch_hw_revision; 1091 int8_t branch_fw_revision[2]; 1092 1093 bool allow_invalid_MSA_timing_param; 1094 bool panel_mode_edp; 1095 bool dpcd_display_control_capable; 1096 bool ext_receiver_cap_field_present; 1097 bool dynamic_backlight_capable_edp; 1098 union dpcd_fec_capability fec_cap; 1099 struct dpcd_dsc_capabilities dsc_caps; 1100 struct dc_lttpr_caps lttpr_caps; 1101 struct psr_caps psr_caps; 1102 1103 }; 1104 1105 union dpcd_sink_ext_caps { 1106 struct { 1107 /* 0 - Sink supports backlight adjust via PWM during SDR/HDR mode 1108 * 1 - Sink supports backlight adjust via AUX during SDR/HDR mode. 1109 */ 1110 uint8_t sdr_aux_backlight_control : 1; 1111 uint8_t hdr_aux_backlight_control : 1; 1112 uint8_t reserved_1 : 2; 1113 uint8_t oled : 1; 1114 uint8_t reserved : 3; 1115 } bits; 1116 uint8_t raw; 1117 }; 1118 1119 #if defined(CONFIG_DRM_AMD_DC_HDCP) 1120 union hdcp_rx_caps { 1121 struct { 1122 uint8_t version; 1123 uint8_t reserved; 1124 struct { 1125 uint8_t repeater : 1; 1126 uint8_t hdcp_capable : 1; 1127 uint8_t reserved : 6; 1128 } byte0; 1129 } fields; 1130 uint8_t raw[3]; 1131 }; 1132 1133 union hdcp_bcaps { 1134 struct { 1135 uint8_t HDCP_CAPABLE:1; 1136 uint8_t REPEATER:1; 1137 uint8_t RESERVED:6; 1138 } bits; 1139 uint8_t raw; 1140 }; 1141 1142 struct hdcp_caps { 1143 union hdcp_rx_caps rx_caps; 1144 union hdcp_bcaps bcaps; 1145 }; 1146 #endif 1147 1148 #include "dc_link.h" 1149 1150 #if defined(CONFIG_DRM_AMD_DC_DCN) 1151 uint32_t dc_get_opp_for_plane(struct dc *dc, struct dc_plane_state *plane); 1152 1153 #endif 1154 /******************************************************************************* 1155 * Sink Interfaces - A sink corresponds to a display output device 1156 ******************************************************************************/ 1157 1158 struct dc_container_id { 1159 // 128bit GUID in binary form 1160 unsigned char guid[16]; 1161 // 8 byte port ID -> ELD.PortID 1162 unsigned int portId[2]; 1163 // 128bit GUID in binary formufacturer name -> ELD.ManufacturerName 1164 unsigned short manufacturerName; 1165 // 2 byte product code -> ELD.ProductCode 1166 unsigned short productCode; 1167 }; 1168 1169 1170 struct dc_sink_dsc_caps { 1171 // 'true' if these are virtual DPCD's DSC caps (immediately upstream of sink in MST topology), 1172 // 'false' if they are sink's DSC caps 1173 bool is_virtual_dpcd_dsc; 1174 struct dsc_dec_dpcd_caps dsc_dec_caps; 1175 }; 1176 1177 struct dc_sink_fec_caps { 1178 bool is_rx_fec_supported; 1179 bool is_topology_fec_supported; 1180 }; 1181 1182 /* 1183 * The sink structure contains EDID and other display device properties 1184 */ 1185 struct dc_sink { 1186 enum signal_type sink_signal; 1187 struct dc_edid dc_edid; /* raw edid */ 1188 struct dc_edid_caps edid_caps; /* parse display caps */ 1189 struct dc_container_id *dc_container_id; 1190 uint32_t dongle_max_pix_clk; 1191 void *priv; 1192 struct stereo_3d_features features_3d[TIMING_3D_FORMAT_MAX]; 1193 bool converter_disable_audio; 1194 1195 struct dc_sink_dsc_caps dsc_caps; 1196 struct dc_sink_fec_caps fec_caps; 1197 1198 bool is_vsc_sdp_colorimetry_supported; 1199 1200 /* private to DC core */ 1201 struct dc_link *link; 1202 struct dc_context *ctx; 1203 1204 uint32_t sink_id; 1205 1206 /* private to dc_sink.c */ 1207 // refcount must be the last member in dc_sink, since we want the 1208 // sink structure to be logically cloneable up to (but not including) 1209 // refcount 1210 struct kref refcount; 1211 }; 1212 1213 void dc_sink_retain(struct dc_sink *sink); 1214 void dc_sink_release(struct dc_sink *sink); 1215 1216 struct dc_sink_init_data { 1217 enum signal_type sink_signal; 1218 struct dc_link *link; 1219 uint32_t dongle_max_pix_clk; 1220 bool converter_disable_audio; 1221 }; 1222 1223 struct dc_sink *dc_sink_create(const struct dc_sink_init_data *init_params); 1224 1225 /* Newer interfaces */ 1226 struct dc_cursor { 1227 struct dc_plane_address address; 1228 struct dc_cursor_attributes attributes; 1229 }; 1230 1231 1232 /******************************************************************************* 1233 * Interrupt interfaces 1234 ******************************************************************************/ 1235 enum dc_irq_source dc_interrupt_to_irq_source( 1236 struct dc *dc, 1237 uint32_t src_id, 1238 uint32_t ext_id); 1239 bool dc_interrupt_set(struct dc *dc, enum dc_irq_source src, bool enable); 1240 void dc_interrupt_ack(struct dc *dc, enum dc_irq_source src); 1241 enum dc_irq_source dc_get_hpd_irq_source_at_index( 1242 struct dc *dc, uint32_t link_index); 1243 1244 /******************************************************************************* 1245 * Power Interfaces 1246 ******************************************************************************/ 1247 1248 void dc_set_power_state( 1249 struct dc *dc, 1250 enum dc_acpi_cm_power_state power_state); 1251 void dc_resume(struct dc *dc); 1252 1253 void dc_power_down_on_boot(struct dc *dc); 1254 1255 #if defined(CONFIG_DRM_AMD_DC_HDCP) 1256 /* 1257 * HDCP Interfaces 1258 */ 1259 enum hdcp_message_status dc_process_hdcp_msg( 1260 enum signal_type signal, 1261 struct dc_link *link, 1262 struct hdcp_protection_message *message_info); 1263 #endif 1264 bool dc_is_dmcu_initialized(struct dc *dc); 1265 1266 enum dc_status dc_set_clock(struct dc *dc, enum dc_clock_type clock_type, uint32_t clk_khz, uint32_t stepping); 1267 void dc_get_clock(struct dc *dc, enum dc_clock_type clock_type, struct dc_clock_config *clock_cfg); 1268 #if defined(CONFIG_DRM_AMD_DC_DCN) 1269 1270 bool dc_is_plane_eligible_for_idle_optimizations(struct dc *dc, 1271 struct dc_plane_state *plane); 1272 1273 void dc_allow_idle_optimizations(struct dc *dc, bool allow); 1274 1275 /* 1276 * blank all streams, and set min and max memory clock to 1277 * lowest and highest DPM level, respectively 1278 */ 1279 void dc_unlock_memory_clock_frequency(struct dc *dc); 1280 1281 /* 1282 * set min memory clock to the min required for current mode, 1283 * max to maxDPM, and unblank streams 1284 */ 1285 void dc_lock_memory_clock_frequency(struct dc *dc); 1286 1287 /* cleanup on driver unload */ 1288 void dc_hardware_release(struct dc *dc); 1289 1290 #endif 1291 1292 bool dc_set_psr_allow_active(struct dc *dc, bool enable); 1293 1294 /******************************************************************************* 1295 * DSC Interfaces 1296 ******************************************************************************/ 1297 #include "dc_dsc.h" 1298 #endif /* DC_INTERFACE_H_ */ 1299