1 /* 2 * Copyright 2012-14 Advanced Micro Devices, Inc. 3 * 4 * Permission is hereby granted, free of charge, to any person obtaining a 5 * copy of this software and associated documentation files (the "Software"), 6 * to deal in the Software without restriction, including without limitation 7 * the rights to use, copy, modify, merge, publish, distribute, sublicense, 8 * and/or sell copies of the Software, and to permit persons to whom the 9 * Software is furnished to do so, subject to the following conditions: 10 * 11 * The above copyright notice and this permission notice shall be included in 12 * all copies or substantial portions of the Software. 13 * 14 * THE SOFTWARE IS PROVIDED "AS IS", WITHOUT WARRANTY OF ANY KIND, EXPRESS OR 15 * IMPLIED, INCLUDING BUT NOT LIMITED TO THE WARRANTIES OF MERCHANTABILITY, 16 * FITNESS FOR A PARTICULAR PURPOSE AND NONINFRINGEMENT. IN NO EVENT SHALL 17 * THE COPYRIGHT HOLDER(S) OR AUTHOR(S) BE LIABLE FOR ANY CLAIM, DAMAGES OR 18 * OTHER LIABILITY, WHETHER IN AN ACTION OF CONTRACT, TORT OR OTHERWISE, 19 * ARISING FROM, OUT OF OR IN CONNECTION WITH THE SOFTWARE OR THE USE OR 20 * OTHER DEALINGS IN THE SOFTWARE. 21 * 22 * Authors: AMD 23 * 24 */ 25 26 #ifndef DC_INTERFACE_H_ 27 #define DC_INTERFACE_H_ 28 29 #include "dc_types.h" 30 #include "grph_object_defs.h" 31 #include "logger_types.h" 32 #include "hdcp_msg_types.h" 33 #include "gpio_types.h" 34 #include "link_service_types.h" 35 #include "grph_object_ctrl_defs.h" 36 #include <inc/hw/opp.h> 37 38 #include "inc/hw_sequencer.h" 39 #include "inc/compressor.h" 40 #include "inc/hw/dmcu.h" 41 #include "dml/display_mode_lib.h" 42 43 /* forward declaration */ 44 struct aux_payload; 45 struct set_config_cmd_payload; 46 struct dmub_notification; 47 48 #define DC_VER "3.2.235" 49 50 #define MAX_SURFACES 3 51 #define MAX_PLANES 6 52 #define MAX_STREAMS 6 53 #define MIN_VIEWPORT_SIZE 12 54 #define MAX_NUM_EDP 2 55 56 /* Display Core Interfaces */ 57 struct dc_versions { 58 const char *dc_ver; 59 struct dmcu_version dmcu_version; 60 }; 61 62 enum dp_protocol_version { 63 DP_VERSION_1_4, 64 }; 65 66 enum dc_plane_type { 67 DC_PLANE_TYPE_INVALID, 68 DC_PLANE_TYPE_DCE_RGB, 69 DC_PLANE_TYPE_DCE_UNDERLAY, 70 DC_PLANE_TYPE_DCN_UNIVERSAL, 71 }; 72 73 // Sizes defined as multiples of 64KB 74 enum det_size { 75 DET_SIZE_DEFAULT = 0, 76 DET_SIZE_192KB = 3, 77 DET_SIZE_256KB = 4, 78 DET_SIZE_320KB = 5, 79 DET_SIZE_384KB = 6 80 }; 81 82 83 struct dc_plane_cap { 84 enum dc_plane_type type; 85 uint32_t per_pixel_alpha : 1; 86 struct { 87 uint32_t argb8888 : 1; 88 uint32_t nv12 : 1; 89 uint32_t fp16 : 1; 90 uint32_t p010 : 1; 91 uint32_t ayuv : 1; 92 } pixel_format_support; 93 // max upscaling factor x1000 94 // upscaling factors are always >= 1 95 // for example, 1080p -> 8K is 4.0, or 4000 raw value 96 struct { 97 uint32_t argb8888; 98 uint32_t nv12; 99 uint32_t fp16; 100 } max_upscale_factor; 101 // max downscale factor x1000 102 // downscale factors are always <= 1 103 // for example, 8K -> 1080p is 0.25, or 250 raw value 104 struct { 105 uint32_t argb8888; 106 uint32_t nv12; 107 uint32_t fp16; 108 } max_downscale_factor; 109 // minimal width/height 110 uint32_t min_width; 111 uint32_t min_height; 112 }; 113 114 /** 115 * DOC: color-management-caps 116 * 117 * **Color management caps (DPP and MPC)** 118 * 119 * Modules/color calculates various color operations which are translated to 120 * abstracted HW. DCE 5-12 had almost no important changes, but starting with 121 * DCN1, every new generation comes with fairly major differences in color 122 * pipeline. Therefore, we abstract color pipe capabilities so modules/DM can 123 * decide mapping to HW block based on logical capabilities. 124 */ 125 126 /** 127 * struct rom_curve_caps - predefined transfer function caps for degamma and regamma 128 * @srgb: RGB color space transfer func 129 * @bt2020: BT.2020 transfer func 130 * @gamma2_2: standard gamma 131 * @pq: perceptual quantizer transfer function 132 * @hlg: hybrid log–gamma transfer function 133 */ 134 struct rom_curve_caps { 135 uint16_t srgb : 1; 136 uint16_t bt2020 : 1; 137 uint16_t gamma2_2 : 1; 138 uint16_t pq : 1; 139 uint16_t hlg : 1; 140 }; 141 142 /** 143 * struct dpp_color_caps - color pipeline capabilities for display pipe and 144 * plane blocks 145 * 146 * @dcn_arch: all DCE generations treated the same 147 * @input_lut_shared: shared with DGAM. Input LUT is different than most LUTs, 148 * just plain 256-entry lookup 149 * @icsc: input color space conversion 150 * @dgam_ram: programmable degamma LUT 151 * @post_csc: post color space conversion, before gamut remap 152 * @gamma_corr: degamma correction 153 * @hw_3d_lut: 3D LUT support. It implies a shaper LUT before. It may be shared 154 * with MPC by setting mpc:shared_3d_lut flag 155 * @ogam_ram: programmable out/blend gamma LUT 156 * @ocsc: output color space conversion 157 * @dgam_rom_for_yuv: pre-defined degamma LUT for YUV planes 158 * @dgam_rom_caps: pre-definied curve caps for degamma 1D LUT 159 * @ogam_rom_caps: pre-definied curve caps for regamma 1D LUT 160 * 161 * Note: hdr_mult and gamut remap (CTM) are always available in DPP (in that order) 162 */ 163 struct dpp_color_caps { 164 uint16_t dcn_arch : 1; 165 uint16_t input_lut_shared : 1; 166 uint16_t icsc : 1; 167 uint16_t dgam_ram : 1; 168 uint16_t post_csc : 1; 169 uint16_t gamma_corr : 1; 170 uint16_t hw_3d_lut : 1; 171 uint16_t ogam_ram : 1; 172 uint16_t ocsc : 1; 173 uint16_t dgam_rom_for_yuv : 1; 174 struct rom_curve_caps dgam_rom_caps; 175 struct rom_curve_caps ogam_rom_caps; 176 }; 177 178 /** 179 * struct mpc_color_caps - color pipeline capabilities for multiple pipe and 180 * plane combined blocks 181 * 182 * @gamut_remap: color transformation matrix 183 * @ogam_ram: programmable out gamma LUT 184 * @ocsc: output color space conversion matrix 185 * @num_3dluts: MPC 3D LUT; always assumes a preceding shaper LUT 186 * @shared_3d_lut: shared 3D LUT flag. Can be either DPP or MPC, but single 187 * instance 188 * @ogam_rom_caps: pre-definied curve caps for regamma 1D LUT 189 */ 190 struct mpc_color_caps { 191 uint16_t gamut_remap : 1; 192 uint16_t ogam_ram : 1; 193 uint16_t ocsc : 1; 194 uint16_t num_3dluts : 3; 195 uint16_t shared_3d_lut:1; 196 struct rom_curve_caps ogam_rom_caps; 197 }; 198 199 /** 200 * struct dc_color_caps - color pipes capabilities for DPP and MPC hw blocks 201 * @dpp: color pipes caps for DPP 202 * @mpc: color pipes caps for MPC 203 */ 204 struct dc_color_caps { 205 struct dpp_color_caps dpp; 206 struct mpc_color_caps mpc; 207 }; 208 209 struct dc_dmub_caps { 210 bool psr; 211 bool mclk_sw; 212 bool subvp_psr; 213 bool gecc_enable; 214 }; 215 216 struct dc_caps { 217 uint32_t max_streams; 218 uint32_t max_links; 219 uint32_t max_audios; 220 uint32_t max_slave_planes; 221 uint32_t max_slave_yuv_planes; 222 uint32_t max_slave_rgb_planes; 223 uint32_t max_planes; 224 uint32_t max_downscale_ratio; 225 uint32_t i2c_speed_in_khz; 226 uint32_t i2c_speed_in_khz_hdcp; 227 uint32_t dmdata_alloc_size; 228 unsigned int max_cursor_size; 229 unsigned int max_video_width; 230 unsigned int min_horizontal_blanking_period; 231 int linear_pitch_alignment; 232 bool dcc_const_color; 233 bool dynamic_audio; 234 bool is_apu; 235 bool dual_link_dvi; 236 bool post_blend_color_processing; 237 bool force_dp_tps4_for_cp2520; 238 bool disable_dp_clk_share; 239 bool psp_setup_panel_mode; 240 bool extended_aux_timeout_support; 241 bool dmcub_support; 242 bool zstate_support; 243 uint32_t num_of_internal_disp; 244 enum dp_protocol_version max_dp_protocol_version; 245 unsigned int mall_size_per_mem_channel; 246 unsigned int mall_size_total; 247 unsigned int cursor_cache_size; 248 struct dc_plane_cap planes[MAX_PLANES]; 249 struct dc_color_caps color; 250 struct dc_dmub_caps dmub_caps; 251 bool dp_hpo; 252 bool dp_hdmi21_pcon_support; 253 bool edp_dsc_support; 254 bool vbios_lttpr_aware; 255 bool vbios_lttpr_enable; 256 uint32_t max_otg_num; 257 uint32_t max_cab_allocation_bytes; 258 uint32_t cache_line_size; 259 uint32_t cache_num_ways; 260 uint16_t subvp_fw_processing_delay_us; 261 uint8_t subvp_drr_max_vblank_margin_us; 262 uint16_t subvp_prefetch_end_to_mall_start_us; 263 uint8_t subvp_swath_height_margin_lines; // subvp start line must be aligned to 2 x swath height 264 uint16_t subvp_pstate_allow_width_us; 265 uint16_t subvp_vertical_int_margin_us; 266 bool seamless_odm; 267 uint8_t subvp_drr_vblank_start_margin_us; 268 }; 269 270 struct dc_bug_wa { 271 bool no_connect_phy_config; 272 bool dedcn20_305_wa; 273 bool skip_clock_update; 274 bool lt_early_cr_pattern; 275 struct { 276 uint8_t uclk : 1; 277 uint8_t fclk : 1; 278 uint8_t dcfclk : 1; 279 uint8_t dcfclk_ds: 1; 280 } clock_update_disable_mask; 281 }; 282 struct dc_dcc_surface_param { 283 struct dc_size surface_size; 284 enum surface_pixel_format format; 285 enum swizzle_mode_values swizzle_mode; 286 enum dc_scan_direction scan; 287 }; 288 289 struct dc_dcc_setting { 290 unsigned int max_compressed_blk_size; 291 unsigned int max_uncompressed_blk_size; 292 bool independent_64b_blks; 293 //These bitfields to be used starting with DCN 294 struct { 295 uint32_t dcc_256_64_64 : 1;//available in ASICs before DCN (the worst compression case) 296 uint32_t dcc_128_128_uncontrained : 1; //available in ASICs before DCN 297 uint32_t dcc_256_128_128 : 1; //available starting with DCN 298 uint32_t dcc_256_256_unconstrained : 1; //available in ASICs before DCN (the best compression case) 299 } dcc_controls; 300 }; 301 302 struct dc_surface_dcc_cap { 303 union { 304 struct { 305 struct dc_dcc_setting rgb; 306 } grph; 307 308 struct { 309 struct dc_dcc_setting luma; 310 struct dc_dcc_setting chroma; 311 } video; 312 }; 313 314 bool capable; 315 bool const_color_support; 316 }; 317 318 struct dc_static_screen_params { 319 struct { 320 bool force_trigger; 321 bool cursor_update; 322 bool surface_update; 323 bool overlay_update; 324 } triggers; 325 unsigned int num_frames; 326 }; 327 328 329 /* Surface update type is used by dc_update_surfaces_and_stream 330 * The update type is determined at the very beginning of the function based 331 * on parameters passed in and decides how much programming (or updating) is 332 * going to be done during the call. 333 * 334 * UPDATE_TYPE_FAST is used for really fast updates that do not require much 335 * logical calculations or hardware register programming. This update MUST be 336 * ISR safe on windows. Currently fast update will only be used to flip surface 337 * address. 338 * 339 * UPDATE_TYPE_MED is used for slower updates which require significant hw 340 * re-programming however do not affect bandwidth consumption or clock 341 * requirements. At present, this is the level at which front end updates 342 * that do not require us to run bw_calcs happen. These are in/out transfer func 343 * updates, viewport offset changes, recout size changes and pixel depth changes. 344 * This update can be done at ISR, but we want to minimize how often this happens. 345 * 346 * UPDATE_TYPE_FULL is slow. Really slow. This requires us to recalculate our 347 * bandwidth and clocks, possibly rearrange some pipes and reprogram anything front 348 * end related. Any time viewport dimensions, recout dimensions, scaling ratios or 349 * gamma need to be adjusted or pipe needs to be turned on (or disconnected) we do 350 * a full update. This cannot be done at ISR level and should be a rare event. 351 * Unless someone is stress testing mpo enter/exit, playing with colour or adjusting 352 * underscan we don't expect to see this call at all. 353 */ 354 355 enum surface_update_type { 356 UPDATE_TYPE_FAST, /* super fast, safe to execute in isr */ 357 UPDATE_TYPE_MED, /* ISR safe, most of programming needed, no bw/clk change*/ 358 UPDATE_TYPE_FULL, /* may need to shuffle resources */ 359 }; 360 361 /* Forward declaration*/ 362 struct dc; 363 struct dc_plane_state; 364 struct dc_state; 365 366 367 struct dc_cap_funcs { 368 bool (*get_dcc_compression_cap)(const struct dc *dc, 369 const struct dc_dcc_surface_param *input, 370 struct dc_surface_dcc_cap *output); 371 }; 372 373 struct link_training_settings; 374 375 union allow_lttpr_non_transparent_mode { 376 struct { 377 bool DP1_4A : 1; 378 bool DP2_0 : 1; 379 } bits; 380 unsigned char raw; 381 }; 382 383 /* Structure to hold configuration flags set by dm at dc creation. */ 384 struct dc_config { 385 bool gpu_vm_support; 386 bool disable_disp_pll_sharing; 387 bool fbc_support; 388 bool disable_fractional_pwm; 389 bool allow_seamless_boot_optimization; 390 bool seamless_boot_edp_requested; 391 bool edp_not_connected; 392 bool edp_no_power_sequencing; 393 bool force_enum_edp; 394 bool forced_clocks; 395 union allow_lttpr_non_transparent_mode allow_lttpr_non_transparent_mode; 396 bool multi_mon_pp_mclk_switch; 397 bool disable_dmcu; 398 bool enable_4to1MPC; 399 bool enable_windowed_mpo_odm; 400 bool forceHBR2CP2520; // Used for switching between test patterns TPS4 and CP2520 401 uint32_t allow_edp_hotplug_detection; 402 bool clamp_min_dcfclk; 403 uint64_t vblank_alignment_dto_params; 404 uint8_t vblank_alignment_max_frame_time_diff; 405 bool is_asymmetric_memory; 406 bool is_single_rank_dimm; 407 bool is_vmin_only_asic; 408 bool use_pipe_ctx_sync_logic; 409 bool ignore_dpref_ss; 410 bool enable_mipi_converter_optimization; 411 bool use_default_clock_table; 412 bool force_bios_enable_lttpr; 413 uint8_t force_bios_fixed_vs; 414 int sdpif_request_limit_words_per_umc; 415 bool use_old_fixed_vs_sequence; 416 bool disable_subvp_drr; 417 }; 418 419 enum visual_confirm { 420 VISUAL_CONFIRM_DISABLE = 0, 421 VISUAL_CONFIRM_SURFACE = 1, 422 VISUAL_CONFIRM_HDR = 2, 423 VISUAL_CONFIRM_MPCTREE = 4, 424 VISUAL_CONFIRM_PSR = 5, 425 VISUAL_CONFIRM_SWAPCHAIN = 6, 426 VISUAL_CONFIRM_FAMS = 7, 427 VISUAL_CONFIRM_SWIZZLE = 9, 428 VISUAL_CONFIRM_SUBVP = 14, 429 }; 430 431 enum dc_psr_power_opts { 432 psr_power_opt_invalid = 0x0, 433 psr_power_opt_smu_opt_static_screen = 0x1, 434 psr_power_opt_z10_static_screen = 0x10, 435 psr_power_opt_ds_disable_allow = 0x100, 436 }; 437 438 enum dml_hostvm_override_opts { 439 DML_HOSTVM_NO_OVERRIDE = 0x0, 440 DML_HOSTVM_OVERRIDE_FALSE = 0x1, 441 DML_HOSTVM_OVERRIDE_TRUE = 0x2, 442 }; 443 444 enum dcc_option { 445 DCC_ENABLE = 0, 446 DCC_DISABLE = 1, 447 DCC_HALF_REQ_DISALBE = 2, 448 }; 449 450 /** 451 * enum pipe_split_policy - Pipe split strategy supported by DCN 452 * 453 * This enum is used to define the pipe split policy supported by DCN. By 454 * default, DC favors MPC_SPLIT_DYNAMIC. 455 */ 456 enum pipe_split_policy { 457 /** 458 * @MPC_SPLIT_DYNAMIC: DC will automatically decide how to split the 459 * pipe in order to bring the best trade-off between performance and 460 * power consumption. This is the recommended option. 461 */ 462 MPC_SPLIT_DYNAMIC = 0, 463 464 /** 465 * @MPC_SPLIT_AVOID: Avoid pipe split, which means that DC will not 466 * try any sort of split optimization. 467 */ 468 MPC_SPLIT_AVOID = 1, 469 470 /** 471 * @MPC_SPLIT_AVOID_MULT_DISP: With this option, DC will only try to 472 * optimize the pipe utilization when using a single display; if the 473 * user connects to a second display, DC will avoid pipe split. 474 */ 475 MPC_SPLIT_AVOID_MULT_DISP = 2, 476 }; 477 478 enum wm_report_mode { 479 WM_REPORT_DEFAULT = 0, 480 WM_REPORT_OVERRIDE = 1, 481 }; 482 enum dtm_pstate{ 483 dtm_level_p0 = 0,/*highest voltage*/ 484 dtm_level_p1, 485 dtm_level_p2, 486 dtm_level_p3, 487 dtm_level_p4,/*when active_display_count = 0*/ 488 }; 489 490 enum dcn_pwr_state { 491 DCN_PWR_STATE_UNKNOWN = -1, 492 DCN_PWR_STATE_MISSION_MODE = 0, 493 DCN_PWR_STATE_LOW_POWER = 3, 494 }; 495 496 enum dcn_zstate_support_state { 497 DCN_ZSTATE_SUPPORT_UNKNOWN, 498 DCN_ZSTATE_SUPPORT_ALLOW, 499 DCN_ZSTATE_SUPPORT_ALLOW_Z8_ONLY, 500 DCN_ZSTATE_SUPPORT_ALLOW_Z8_Z10_ONLY, 501 DCN_ZSTATE_SUPPORT_ALLOW_Z10_ONLY, 502 DCN_ZSTATE_SUPPORT_DISALLOW, 503 }; 504 505 /** 506 * struct dc_clocks - DC pipe clocks 507 * 508 * For any clocks that may differ per pipe only the max is stored in this 509 * structure 510 */ 511 struct dc_clocks { 512 int dispclk_khz; 513 int actual_dispclk_khz; 514 int dppclk_khz; 515 int actual_dppclk_khz; 516 int disp_dpp_voltage_level_khz; 517 int dcfclk_khz; 518 int socclk_khz; 519 int dcfclk_deep_sleep_khz; 520 int fclk_khz; 521 int phyclk_khz; 522 int dramclk_khz; 523 bool p_state_change_support; 524 enum dcn_zstate_support_state zstate_support; 525 bool dtbclk_en; 526 int ref_dtbclk_khz; 527 bool fclk_p_state_change_support; 528 enum dcn_pwr_state pwr_state; 529 /* 530 * Elements below are not compared for the purposes of 531 * optimization required 532 */ 533 bool prev_p_state_change_support; 534 bool fclk_prev_p_state_change_support; 535 int num_ways; 536 537 /* 538 * @fw_based_mclk_switching 539 * 540 * DC has a mechanism that leverage the variable refresh rate to switch 541 * memory clock in cases that we have a large latency to achieve the 542 * memory clock change and a short vblank window. DC has some 543 * requirements to enable this feature, and this field describes if the 544 * system support or not such a feature. 545 */ 546 bool fw_based_mclk_switching; 547 bool fw_based_mclk_switching_shut_down; 548 int prev_num_ways; 549 enum dtm_pstate dtm_level; 550 int max_supported_dppclk_khz; 551 int max_supported_dispclk_khz; 552 int bw_dppclk_khz; /*a copy of dppclk_khz*/ 553 int bw_dispclk_khz; 554 }; 555 556 struct dc_bw_validation_profile { 557 bool enable; 558 559 unsigned long long total_ticks; 560 unsigned long long voltage_level_ticks; 561 unsigned long long watermark_ticks; 562 unsigned long long rq_dlg_ticks; 563 564 unsigned long long total_count; 565 unsigned long long skip_fast_count; 566 unsigned long long skip_pass_count; 567 unsigned long long skip_fail_count; 568 }; 569 570 #define BW_VAL_TRACE_SETUP() \ 571 unsigned long long end_tick = 0; \ 572 unsigned long long voltage_level_tick = 0; \ 573 unsigned long long watermark_tick = 0; \ 574 unsigned long long start_tick = dc->debug.bw_val_profile.enable ? \ 575 dm_get_timestamp(dc->ctx) : 0 576 577 #define BW_VAL_TRACE_COUNT() \ 578 if (dc->debug.bw_val_profile.enable) \ 579 dc->debug.bw_val_profile.total_count++ 580 581 #define BW_VAL_TRACE_SKIP(status) \ 582 if (dc->debug.bw_val_profile.enable) { \ 583 if (!voltage_level_tick) \ 584 voltage_level_tick = dm_get_timestamp(dc->ctx); \ 585 dc->debug.bw_val_profile.skip_ ## status ## _count++; \ 586 } 587 588 #define BW_VAL_TRACE_END_VOLTAGE_LEVEL() \ 589 if (dc->debug.bw_val_profile.enable) \ 590 voltage_level_tick = dm_get_timestamp(dc->ctx) 591 592 #define BW_VAL_TRACE_END_WATERMARKS() \ 593 if (dc->debug.bw_val_profile.enable) \ 594 watermark_tick = dm_get_timestamp(dc->ctx) 595 596 #define BW_VAL_TRACE_FINISH() \ 597 if (dc->debug.bw_val_profile.enable) { \ 598 end_tick = dm_get_timestamp(dc->ctx); \ 599 dc->debug.bw_val_profile.total_ticks += end_tick - start_tick; \ 600 dc->debug.bw_val_profile.voltage_level_ticks += voltage_level_tick - start_tick; \ 601 if (watermark_tick) { \ 602 dc->debug.bw_val_profile.watermark_ticks += watermark_tick - voltage_level_tick; \ 603 dc->debug.bw_val_profile.rq_dlg_ticks += end_tick - watermark_tick; \ 604 } \ 605 } 606 607 union mem_low_power_enable_options { 608 struct { 609 bool vga: 1; 610 bool i2c: 1; 611 bool dmcu: 1; 612 bool dscl: 1; 613 bool cm: 1; 614 bool mpc: 1; 615 bool optc: 1; 616 bool vpg: 1; 617 bool afmt: 1; 618 } bits; 619 uint32_t u32All; 620 }; 621 622 union root_clock_optimization_options { 623 struct { 624 bool dpp: 1; 625 bool dsc: 1; 626 bool hdmistream: 1; 627 bool hdmichar: 1; 628 bool dpstream: 1; 629 bool symclk32_se: 1; 630 bool symclk32_le: 1; 631 bool symclk_fe: 1; 632 bool physymclk: 1; 633 bool dpiasymclk: 1; 634 uint32_t reserved: 22; 635 } bits; 636 uint32_t u32All; 637 }; 638 639 union dpia_debug_options { 640 struct { 641 uint32_t disable_dpia:1; /* bit 0 */ 642 uint32_t force_non_lttpr:1; /* bit 1 */ 643 uint32_t extend_aux_rd_interval:1; /* bit 2 */ 644 uint32_t disable_mst_dsc_work_around:1; /* bit 3 */ 645 uint32_t enable_force_tbt3_work_around:1; /* bit 4 */ 646 uint32_t reserved:27; 647 } bits; 648 uint32_t raw; 649 }; 650 651 /* AUX wake work around options 652 * 0: enable/disable work around 653 * 1: use default timeout LINK_AUX_WAKE_TIMEOUT_MS 654 * 15-2: reserved 655 * 31-16: timeout in ms 656 */ 657 union aux_wake_wa_options { 658 struct { 659 uint32_t enable_wa : 1; 660 uint32_t use_default_timeout : 1; 661 uint32_t rsvd: 14; 662 uint32_t timeout_ms : 16; 663 } bits; 664 uint32_t raw; 665 }; 666 667 struct dc_debug_data { 668 uint32_t ltFailCount; 669 uint32_t i2cErrorCount; 670 uint32_t auxErrorCount; 671 }; 672 673 struct dc_phy_addr_space_config { 674 struct { 675 uint64_t start_addr; 676 uint64_t end_addr; 677 uint64_t fb_top; 678 uint64_t fb_offset; 679 uint64_t fb_base; 680 uint64_t agp_top; 681 uint64_t agp_bot; 682 uint64_t agp_base; 683 } system_aperture; 684 685 struct { 686 uint64_t page_table_start_addr; 687 uint64_t page_table_end_addr; 688 uint64_t page_table_base_addr; 689 bool base_addr_is_mc_addr; 690 } gart_config; 691 692 bool valid; 693 bool is_hvm_enabled; 694 uint64_t page_table_default_page_addr; 695 }; 696 697 struct dc_virtual_addr_space_config { 698 uint64_t page_table_base_addr; 699 uint64_t page_table_start_addr; 700 uint64_t page_table_end_addr; 701 uint32_t page_table_block_size_in_bytes; 702 uint8_t page_table_depth; // 1 = 1 level, 2 = 2 level, etc. 0 = invalid 703 }; 704 705 struct dc_bounding_box_overrides { 706 int sr_exit_time_ns; 707 int sr_enter_plus_exit_time_ns; 708 int sr_exit_z8_time_ns; 709 int sr_enter_plus_exit_z8_time_ns; 710 int urgent_latency_ns; 711 int percent_of_ideal_drambw; 712 int dram_clock_change_latency_ns; 713 int dummy_clock_change_latency_ns; 714 int fclk_clock_change_latency_ns; 715 /* This forces a hard min on the DCFCLK we use 716 * for DML. Unlike the debug option for forcing 717 * DCFCLK, this override affects watermark calculations 718 */ 719 int min_dcfclk_mhz; 720 }; 721 722 struct dc_state; 723 struct resource_pool; 724 struct dce_hwseq; 725 struct link_service; 726 727 /** 728 * struct dc_debug_options - DC debug struct 729 * 730 * This struct provides a simple mechanism for developers to change some 731 * configurations, enable/disable features, and activate extra debug options. 732 * This can be very handy to narrow down whether some specific feature is 733 * causing an issue or not. 734 */ 735 struct dc_debug_options { 736 bool native422_support; 737 bool disable_dsc; 738 enum visual_confirm visual_confirm; 739 int visual_confirm_rect_height; 740 741 bool sanity_checks; 742 bool max_disp_clk; 743 bool surface_trace; 744 bool timing_trace; 745 bool clock_trace; 746 bool validation_trace; 747 bool bandwidth_calcs_trace; 748 int max_downscale_src_width; 749 750 /* stutter efficiency related */ 751 bool disable_stutter; 752 bool use_max_lb; 753 enum dcc_option disable_dcc; 754 755 /** 756 * @pipe_split_policy: Define which pipe split policy is used by the 757 * display core. 758 */ 759 enum pipe_split_policy pipe_split_policy; 760 bool force_single_disp_pipe_split; 761 bool voltage_align_fclk; 762 bool disable_min_fclk; 763 764 bool disable_dfs_bypass; 765 bool disable_dpp_power_gate; 766 bool disable_hubp_power_gate; 767 bool disable_dsc_power_gate; 768 int dsc_min_slice_height_override; 769 int dsc_bpp_increment_div; 770 bool disable_pplib_wm_range; 771 enum wm_report_mode pplib_wm_report_mode; 772 unsigned int min_disp_clk_khz; 773 unsigned int min_dpp_clk_khz; 774 unsigned int min_dram_clk_khz; 775 int sr_exit_time_dpm0_ns; 776 int sr_enter_plus_exit_time_dpm0_ns; 777 int sr_exit_time_ns; 778 int sr_enter_plus_exit_time_ns; 779 int sr_exit_z8_time_ns; 780 int sr_enter_plus_exit_z8_time_ns; 781 int urgent_latency_ns; 782 uint32_t underflow_assert_delay_us; 783 int percent_of_ideal_drambw; 784 int dram_clock_change_latency_ns; 785 bool optimized_watermark; 786 int always_scale; 787 bool disable_pplib_clock_request; 788 bool disable_clock_gate; 789 bool disable_mem_low_power; 790 bool pstate_enabled; 791 bool disable_dmcu; 792 bool force_abm_enable; 793 bool disable_stereo_support; 794 bool vsr_support; 795 bool performance_trace; 796 bool az_endpoint_mute_only; 797 bool always_use_regamma; 798 bool recovery_enabled; 799 bool avoid_vbios_exec_table; 800 bool scl_reset_length10; 801 bool hdmi20_disable; 802 bool skip_detection_link_training; 803 uint32_t edid_read_retry_times; 804 unsigned int force_odm_combine; //bit vector based on otg inst 805 unsigned int seamless_boot_odm_combine; 806 unsigned int force_odm_combine_4to1; //bit vector based on otg inst 807 int minimum_z8_residency_time; 808 bool disable_z9_mpc; 809 unsigned int force_fclk_khz; 810 bool enable_tri_buf; 811 bool dmub_offload_enabled; 812 bool dmcub_emulation; 813 bool disable_idle_power_optimizations; 814 unsigned int mall_size_override; 815 unsigned int mall_additional_timer_percent; 816 bool mall_error_as_fatal; 817 bool dmub_command_table; /* for testing only */ 818 struct dc_bw_validation_profile bw_val_profile; 819 bool disable_fec; 820 bool disable_48mhz_pwrdwn; 821 /* This forces a hard min on the DCFCLK requested to SMU/PP 822 * watermarks are not affected. 823 */ 824 unsigned int force_min_dcfclk_mhz; 825 int dwb_fi_phase; 826 bool disable_timing_sync; 827 bool cm_in_bypass; 828 int force_clock_mode;/*every mode change.*/ 829 830 bool disable_dram_clock_change_vactive_support; 831 bool validate_dml_output; 832 bool enable_dmcub_surface_flip; 833 bool usbc_combo_phy_reset_wa; 834 bool enable_dram_clock_change_one_display_vactive; 835 /* TODO - remove once tested */ 836 bool legacy_dp2_lt; 837 bool set_mst_en_for_sst; 838 bool disable_uhbr; 839 bool force_dp2_lt_fallback_method; 840 bool ignore_cable_id; 841 union mem_low_power_enable_options enable_mem_low_power; 842 union root_clock_optimization_options root_clock_optimization; 843 bool hpo_optimization; 844 bool force_vblank_alignment; 845 846 /* Enable dmub aux for legacy ddc */ 847 bool enable_dmub_aux_for_legacy_ddc; 848 bool disable_fams; 849 /* FEC/PSR1 sequence enable delay in 100us */ 850 uint8_t fec_enable_delay_in100us; 851 bool enable_driver_sequence_debug; 852 enum det_size crb_alloc_policy; 853 int crb_alloc_policy_min_disp_count; 854 bool disable_z10; 855 bool enable_z9_disable_interface; 856 bool psr_skip_crtc_disable; 857 union dpia_debug_options dpia_debug; 858 bool disable_fixed_vs_aux_timeout_wa; 859 bool force_disable_subvp; 860 bool force_subvp_mclk_switch; 861 bool allow_sw_cursor_fallback; 862 unsigned int force_subvp_num_ways; 863 unsigned int force_mall_ss_num_ways; 864 bool alloc_extra_way_for_cursor; 865 uint32_t subvp_extra_lines; 866 bool force_usr_allow; 867 /* uses value at boot and disables switch */ 868 bool disable_dtb_ref_clk_switch; 869 bool extended_blank_optimization; 870 union aux_wake_wa_options aux_wake_wa; 871 uint32_t mst_start_top_delay; 872 uint8_t psr_power_use_phy_fsm; 873 enum dml_hostvm_override_opts dml_hostvm_override; 874 bool dml_disallow_alternate_prefetch_modes; 875 bool use_legacy_soc_bb_mechanism; 876 bool exit_idle_opt_for_cursor_updates; 877 bool enable_single_display_2to1_odm_policy; 878 bool enable_double_buffered_dsc_pg_support; 879 bool enable_dp_dig_pixel_rate_div_policy; 880 enum lttpr_mode lttpr_mode_override; 881 unsigned int dsc_delay_factor_wa_x1000; 882 unsigned int min_prefetch_in_strobe_ns; 883 bool disable_unbounded_requesting; 884 bool dig_fifo_off_in_blank; 885 bool temp_mst_deallocation_sequence; 886 bool override_dispclk_programming; 887 bool disable_fpo_optimizations; 888 bool support_eDP1_5; 889 uint32_t fpo_vactive_margin_us; 890 bool disable_fpo_vactive; 891 bool disable_boot_optimizations; 892 bool override_odm_optimization; 893 bool minimize_dispclk_using_odm; 894 bool disable_subvp_high_refresh; 895 bool disable_dp_plus_plus_wa; 896 }; 897 898 struct gpu_info_soc_bounding_box_v1_0; 899 struct dc { 900 struct dc_debug_options debug; 901 struct dc_versions versions; 902 struct dc_caps caps; 903 struct dc_cap_funcs cap_funcs; 904 struct dc_config config; 905 struct dc_bounding_box_overrides bb_overrides; 906 struct dc_bug_wa work_arounds; 907 struct dc_context *ctx; 908 struct dc_phy_addr_space_config vm_pa_config; 909 910 uint8_t link_count; 911 struct dc_link *links[MAX_PIPES * 2]; 912 struct link_service *link_srv; 913 914 struct dc_state *current_state; 915 struct resource_pool *res_pool; 916 917 struct clk_mgr *clk_mgr; 918 919 /* Display Engine Clock levels */ 920 struct dm_pp_clock_levels sclk_lvls; 921 922 /* Inputs into BW and WM calculations. */ 923 struct bw_calcs_dceip *bw_dceip; 924 struct bw_calcs_vbios *bw_vbios; 925 struct dcn_soc_bounding_box *dcn_soc; 926 struct dcn_ip_params *dcn_ip; 927 struct display_mode_lib dml; 928 929 /* HW functions */ 930 struct hw_sequencer_funcs hwss; 931 struct dce_hwseq *hwseq; 932 933 /* Require to optimize clocks and bandwidth for added/removed planes */ 934 bool optimized_required; 935 bool wm_optimized_required; 936 bool idle_optimizations_allowed; 937 bool enable_c20_dtm_b0; 938 939 /* Require to maintain clocks and bandwidth for UEFI enabled HW */ 940 941 /* FBC compressor */ 942 struct compressor *fbc_compressor; 943 944 struct dc_debug_data debug_data; 945 struct dpcd_vendor_signature vendor_signature; 946 947 const char *build_id; 948 struct vm_helper *vm_helper; 949 950 uint32_t *dcn_reg_offsets; 951 uint32_t *nbio_reg_offsets; 952 953 /* Scratch memory */ 954 struct { 955 struct { 956 /* 957 * For matching clock_limits table in driver with table 958 * from PMFW. 959 */ 960 struct _vcs_dpi_voltage_scaling_st clock_limits[DC__VOLTAGE_STATES]; 961 } update_bw_bounding_box; 962 } scratch; 963 }; 964 965 enum frame_buffer_mode { 966 FRAME_BUFFER_MODE_LOCAL_ONLY = 0, 967 FRAME_BUFFER_MODE_ZFB_ONLY, 968 FRAME_BUFFER_MODE_MIXED_ZFB_AND_LOCAL, 969 } ; 970 971 struct dchub_init_data { 972 int64_t zfb_phys_addr_base; 973 int64_t zfb_mc_base_addr; 974 uint64_t zfb_size_in_byte; 975 enum frame_buffer_mode fb_mode; 976 bool dchub_initialzied; 977 bool dchub_info_valid; 978 }; 979 980 struct dc_init_data { 981 struct hw_asic_id asic_id; 982 void *driver; /* ctx */ 983 struct cgs_device *cgs_device; 984 struct dc_bounding_box_overrides bb_overrides; 985 986 int num_virtual_links; 987 /* 988 * If 'vbios_override' not NULL, it will be called instead 989 * of the real VBIOS. Intended use is Diagnostics on FPGA. 990 */ 991 struct dc_bios *vbios_override; 992 enum dce_environment dce_environment; 993 994 struct dmub_offload_funcs *dmub_if; 995 struct dc_reg_helper_state *dmub_offload; 996 997 struct dc_config flags; 998 uint64_t log_mask; 999 1000 struct dpcd_vendor_signature vendor_signature; 1001 bool force_smu_not_present; 1002 /* 1003 * IP offset for run time initializaion of register addresses 1004 * 1005 * DCN3.5+ will fail dc_create() if these fields are null for them. They are 1006 * applicable starting with DCN32/321 and are not used for ASICs upstreamed 1007 * before them. 1008 */ 1009 uint32_t *dcn_reg_offsets; 1010 uint32_t *nbio_reg_offsets; 1011 }; 1012 1013 struct dc_callback_init { 1014 struct cp_psp cp_psp; 1015 }; 1016 1017 struct dc *dc_create(const struct dc_init_data *init_params); 1018 void dc_hardware_init(struct dc *dc); 1019 1020 int dc_get_vmid_use_vector(struct dc *dc); 1021 void dc_setup_vm_context(struct dc *dc, struct dc_virtual_addr_space_config *va_config, int vmid); 1022 /* Returns the number of vmids supported */ 1023 int dc_setup_system_context(struct dc *dc, struct dc_phy_addr_space_config *pa_config); 1024 void dc_init_callbacks(struct dc *dc, 1025 const struct dc_callback_init *init_params); 1026 void dc_deinit_callbacks(struct dc *dc); 1027 void dc_destroy(struct dc **dc); 1028 1029 /* Surface Interfaces */ 1030 1031 enum { 1032 TRANSFER_FUNC_POINTS = 1025 1033 }; 1034 1035 struct dc_hdr_static_metadata { 1036 /* display chromaticities and white point in units of 0.00001 */ 1037 unsigned int chromaticity_green_x; 1038 unsigned int chromaticity_green_y; 1039 unsigned int chromaticity_blue_x; 1040 unsigned int chromaticity_blue_y; 1041 unsigned int chromaticity_red_x; 1042 unsigned int chromaticity_red_y; 1043 unsigned int chromaticity_white_point_x; 1044 unsigned int chromaticity_white_point_y; 1045 1046 uint32_t min_luminance; 1047 uint32_t max_luminance; 1048 uint32_t maximum_content_light_level; 1049 uint32_t maximum_frame_average_light_level; 1050 }; 1051 1052 enum dc_transfer_func_type { 1053 TF_TYPE_PREDEFINED, 1054 TF_TYPE_DISTRIBUTED_POINTS, 1055 TF_TYPE_BYPASS, 1056 TF_TYPE_HWPWL 1057 }; 1058 1059 struct dc_transfer_func_distributed_points { 1060 struct fixed31_32 red[TRANSFER_FUNC_POINTS]; 1061 struct fixed31_32 green[TRANSFER_FUNC_POINTS]; 1062 struct fixed31_32 blue[TRANSFER_FUNC_POINTS]; 1063 1064 uint16_t end_exponent; 1065 uint16_t x_point_at_y1_red; 1066 uint16_t x_point_at_y1_green; 1067 uint16_t x_point_at_y1_blue; 1068 }; 1069 1070 enum dc_transfer_func_predefined { 1071 TRANSFER_FUNCTION_SRGB, 1072 TRANSFER_FUNCTION_BT709, 1073 TRANSFER_FUNCTION_PQ, 1074 TRANSFER_FUNCTION_LINEAR, 1075 TRANSFER_FUNCTION_UNITY, 1076 TRANSFER_FUNCTION_HLG, 1077 TRANSFER_FUNCTION_HLG12, 1078 TRANSFER_FUNCTION_GAMMA22, 1079 TRANSFER_FUNCTION_GAMMA24, 1080 TRANSFER_FUNCTION_GAMMA26 1081 }; 1082 1083 1084 struct dc_transfer_func { 1085 struct kref refcount; 1086 enum dc_transfer_func_type type; 1087 enum dc_transfer_func_predefined tf; 1088 /* FP16 1.0 reference level in nits, default is 80 nits, only for PQ*/ 1089 uint32_t sdr_ref_white_level; 1090 union { 1091 struct pwl_params pwl; 1092 struct dc_transfer_func_distributed_points tf_pts; 1093 }; 1094 }; 1095 1096 1097 union dc_3dlut_state { 1098 struct { 1099 uint32_t initialized:1; /*if 3dlut is went through color module for initialization */ 1100 uint32_t rmu_idx_valid:1; /*if mux settings are valid*/ 1101 uint32_t rmu_mux_num:3; /*index of mux to use*/ 1102 uint32_t mpc_rmu0_mux:4; /*select mpcc on mux, one of the following : mpcc0, mpcc1, mpcc2, mpcc3*/ 1103 uint32_t mpc_rmu1_mux:4; 1104 uint32_t mpc_rmu2_mux:4; 1105 uint32_t reserved:15; 1106 } bits; 1107 uint32_t raw; 1108 }; 1109 1110 1111 struct dc_3dlut { 1112 struct kref refcount; 1113 struct tetrahedral_params lut_3d; 1114 struct fixed31_32 hdr_multiplier; 1115 union dc_3dlut_state state; 1116 }; 1117 /* 1118 * This structure is filled in by dc_surface_get_status and contains 1119 * the last requested address and the currently active address so the called 1120 * can determine if there are any outstanding flips 1121 */ 1122 struct dc_plane_status { 1123 struct dc_plane_address requested_address; 1124 struct dc_plane_address current_address; 1125 bool is_flip_pending; 1126 bool is_right_eye; 1127 }; 1128 1129 union surface_update_flags { 1130 1131 struct { 1132 uint32_t addr_update:1; 1133 /* Medium updates */ 1134 uint32_t dcc_change:1; 1135 uint32_t color_space_change:1; 1136 uint32_t horizontal_mirror_change:1; 1137 uint32_t per_pixel_alpha_change:1; 1138 uint32_t global_alpha_change:1; 1139 uint32_t hdr_mult:1; 1140 uint32_t rotation_change:1; 1141 uint32_t swizzle_change:1; 1142 uint32_t scaling_change:1; 1143 uint32_t position_change:1; 1144 uint32_t in_transfer_func_change:1; 1145 uint32_t input_csc_change:1; 1146 uint32_t coeff_reduction_change:1; 1147 uint32_t output_tf_change:1; 1148 uint32_t pixel_format_change:1; 1149 uint32_t plane_size_change:1; 1150 uint32_t gamut_remap_change:1; 1151 1152 /* Full updates */ 1153 uint32_t new_plane:1; 1154 uint32_t bpp_change:1; 1155 uint32_t gamma_change:1; 1156 uint32_t bandwidth_change:1; 1157 uint32_t clock_change:1; 1158 uint32_t stereo_format_change:1; 1159 uint32_t lut_3d:1; 1160 uint32_t tmz_changed:1; 1161 uint32_t full_update:1; 1162 } bits; 1163 1164 uint32_t raw; 1165 }; 1166 1167 struct dc_plane_state { 1168 struct dc_plane_address address; 1169 struct dc_plane_flip_time time; 1170 bool triplebuffer_flips; 1171 struct scaling_taps scaling_quality; 1172 struct rect src_rect; 1173 struct rect dst_rect; 1174 struct rect clip_rect; 1175 1176 struct plane_size plane_size; 1177 union dc_tiling_info tiling_info; 1178 1179 struct dc_plane_dcc_param dcc; 1180 1181 struct dc_gamma *gamma_correction; 1182 struct dc_transfer_func *in_transfer_func; 1183 struct dc_bias_and_scale *bias_and_scale; 1184 struct dc_csc_transform input_csc_color_matrix; 1185 struct fixed31_32 coeff_reduction_factor; 1186 struct fixed31_32 hdr_mult; 1187 struct colorspace_transform gamut_remap_matrix; 1188 1189 // TODO: No longer used, remove 1190 struct dc_hdr_static_metadata hdr_static_ctx; 1191 1192 enum dc_color_space color_space; 1193 1194 struct dc_3dlut *lut3d_func; 1195 struct dc_transfer_func *in_shaper_func; 1196 struct dc_transfer_func *blend_tf; 1197 1198 struct dc_transfer_func *gamcor_tf; 1199 enum surface_pixel_format format; 1200 enum dc_rotation_angle rotation; 1201 enum plane_stereo_format stereo_format; 1202 1203 bool is_tiling_rotated; 1204 bool per_pixel_alpha; 1205 bool pre_multiplied_alpha; 1206 bool global_alpha; 1207 int global_alpha_value; 1208 bool visible; 1209 bool flip_immediate; 1210 bool horizontal_mirror; 1211 int layer_index; 1212 1213 union surface_update_flags update_flags; 1214 bool flip_int_enabled; 1215 bool skip_manual_trigger; 1216 1217 /* private to DC core */ 1218 struct dc_plane_status status; 1219 struct dc_context *ctx; 1220 1221 /* HACK: Workaround for forcing full reprogramming under some conditions */ 1222 bool force_full_update; 1223 1224 bool is_phantom; // TODO: Change mall_stream_config into mall_plane_config instead 1225 1226 /* private to dc_surface.c */ 1227 enum dc_irq_source irq_source; 1228 struct kref refcount; 1229 struct tg_color visual_confirm_color; 1230 1231 bool is_statically_allocated; 1232 }; 1233 1234 struct dc_plane_info { 1235 struct plane_size plane_size; 1236 union dc_tiling_info tiling_info; 1237 struct dc_plane_dcc_param dcc; 1238 enum surface_pixel_format format; 1239 enum dc_rotation_angle rotation; 1240 enum plane_stereo_format stereo_format; 1241 enum dc_color_space color_space; 1242 bool horizontal_mirror; 1243 bool visible; 1244 bool per_pixel_alpha; 1245 bool pre_multiplied_alpha; 1246 bool global_alpha; 1247 int global_alpha_value; 1248 bool input_csc_enabled; 1249 int layer_index; 1250 }; 1251 1252 struct dc_scaling_info { 1253 struct rect src_rect; 1254 struct rect dst_rect; 1255 struct rect clip_rect; 1256 struct scaling_taps scaling_quality; 1257 }; 1258 1259 struct dc_surface_update { 1260 struct dc_plane_state *surface; 1261 1262 /* isr safe update parameters. null means no updates */ 1263 const struct dc_flip_addrs *flip_addr; 1264 const struct dc_plane_info *plane_info; 1265 const struct dc_scaling_info *scaling_info; 1266 struct fixed31_32 hdr_mult; 1267 /* following updates require alloc/sleep/spin that is not isr safe, 1268 * null means no updates 1269 */ 1270 const struct dc_gamma *gamma; 1271 const struct dc_transfer_func *in_transfer_func; 1272 1273 const struct dc_csc_transform *input_csc_color_matrix; 1274 const struct fixed31_32 *coeff_reduction_factor; 1275 const struct dc_transfer_func *func_shaper; 1276 const struct dc_3dlut *lut3d_func; 1277 const struct dc_transfer_func *blend_tf; 1278 const struct colorspace_transform *gamut_remap_matrix; 1279 }; 1280 1281 /* 1282 * Create a new surface with default parameters; 1283 */ 1284 struct dc_plane_state *dc_create_plane_state(struct dc *dc); 1285 const struct dc_plane_status *dc_plane_get_status( 1286 const struct dc_plane_state *plane_state); 1287 1288 void dc_plane_state_retain(struct dc_plane_state *plane_state); 1289 void dc_plane_state_release(struct dc_plane_state *plane_state); 1290 1291 void dc_gamma_retain(struct dc_gamma *dc_gamma); 1292 void dc_gamma_release(struct dc_gamma **dc_gamma); 1293 struct dc_gamma *dc_create_gamma(void); 1294 1295 void dc_transfer_func_retain(struct dc_transfer_func *dc_tf); 1296 void dc_transfer_func_release(struct dc_transfer_func *dc_tf); 1297 struct dc_transfer_func *dc_create_transfer_func(void); 1298 1299 struct dc_3dlut *dc_create_3dlut_func(void); 1300 void dc_3dlut_func_release(struct dc_3dlut *lut); 1301 void dc_3dlut_func_retain(struct dc_3dlut *lut); 1302 1303 void dc_post_update_surfaces_to_stream( 1304 struct dc *dc); 1305 1306 #include "dc_stream.h" 1307 1308 /** 1309 * struct dc_validation_set - Struct to store surface/stream associations for validation 1310 */ 1311 struct dc_validation_set { 1312 /** 1313 * @stream: Stream state properties 1314 */ 1315 struct dc_stream_state *stream; 1316 1317 /** 1318 * @plane_state: Surface state 1319 */ 1320 struct dc_plane_state *plane_states[MAX_SURFACES]; 1321 1322 /** 1323 * @plane_count: Total of active planes 1324 */ 1325 uint8_t plane_count; 1326 }; 1327 1328 bool dc_validate_boot_timing(const struct dc *dc, 1329 const struct dc_sink *sink, 1330 struct dc_crtc_timing *crtc_timing); 1331 1332 enum dc_status dc_validate_plane(struct dc *dc, const struct dc_plane_state *plane_state); 1333 1334 void get_clock_requirements_for_state(struct dc_state *state, struct AsicStateEx *info); 1335 1336 enum dc_status dc_validate_with_context(struct dc *dc, 1337 const struct dc_validation_set set[], 1338 int set_count, 1339 struct dc_state *context, 1340 bool fast_validate); 1341 1342 bool dc_set_generic_gpio_for_stereo(bool enable, 1343 struct gpio_service *gpio_service); 1344 1345 /* 1346 * fast_validate: we return after determining if we can support the new state, 1347 * but before we populate the programming info 1348 */ 1349 enum dc_status dc_validate_global_state( 1350 struct dc *dc, 1351 struct dc_state *new_ctx, 1352 bool fast_validate); 1353 1354 1355 void dc_resource_state_construct( 1356 const struct dc *dc, 1357 struct dc_state *dst_ctx); 1358 1359 bool dc_acquire_release_mpc_3dlut( 1360 struct dc *dc, bool acquire, 1361 struct dc_stream_state *stream, 1362 struct dc_3dlut **lut, 1363 struct dc_transfer_func **shaper); 1364 1365 void dc_resource_state_copy_construct( 1366 const struct dc_state *src_ctx, 1367 struct dc_state *dst_ctx); 1368 1369 void dc_resource_state_copy_construct_current( 1370 const struct dc *dc, 1371 struct dc_state *dst_ctx); 1372 1373 void dc_resource_state_destruct(struct dc_state *context); 1374 1375 bool dc_resource_is_dsc_encoding_supported(const struct dc *dc); 1376 1377 enum dc_status dc_commit_streams(struct dc *dc, 1378 struct dc_stream_state *streams[], 1379 uint8_t stream_count); 1380 1381 struct dc_state *dc_create_state(struct dc *dc); 1382 struct dc_state *dc_copy_state(struct dc_state *src_ctx); 1383 void dc_retain_state(struct dc_state *context); 1384 void dc_release_state(struct dc_state *context); 1385 1386 struct dc_plane_state *dc_get_surface_for_mpcc(struct dc *dc, 1387 struct dc_stream_state *stream, 1388 int mpcc_inst); 1389 1390 1391 uint32_t dc_get_opp_for_plane(struct dc *dc, struct dc_plane_state *plane); 1392 1393 /* The function returns minimum bandwidth required to drive a given timing 1394 * return - minimum required timing bandwidth in kbps. 1395 */ 1396 uint32_t dc_bandwidth_in_kbps_from_timing(const struct dc_crtc_timing *timing); 1397 1398 /* Link Interfaces */ 1399 /* 1400 * A link contains one or more sinks and their connected status. 1401 * The currently active signal type (HDMI, DP-SST, DP-MST) is also reported. 1402 */ 1403 struct dc_link { 1404 struct dc_sink *remote_sinks[MAX_SINKS_PER_LINK]; 1405 unsigned int sink_count; 1406 struct dc_sink *local_sink; 1407 unsigned int link_index; 1408 enum dc_connection_type type; 1409 enum signal_type connector_signal; 1410 enum dc_irq_source irq_source_hpd; 1411 enum dc_irq_source irq_source_hpd_rx;/* aka DP Short Pulse */ 1412 1413 bool is_hpd_filter_disabled; 1414 bool dp_ss_off; 1415 1416 /** 1417 * @link_state_valid: 1418 * 1419 * If there is no link and local sink, this variable should be set to 1420 * false. Otherwise, it should be set to true; usually, the function 1421 * core_link_enable_stream sets this field to true. 1422 */ 1423 bool link_state_valid; 1424 bool aux_access_disabled; 1425 bool sync_lt_in_progress; 1426 bool skip_stream_reenable; 1427 bool is_internal_display; 1428 /** @todo Rename. Flag an endpoint as having a programmable mapping to a DIG encoder. */ 1429 bool is_dig_mapping_flexible; 1430 bool hpd_status; /* HPD status of link without physical HPD pin. */ 1431 bool is_hpd_pending; /* Indicates a new received hpd */ 1432 bool is_automated; /* Indicates automated testing */ 1433 1434 bool edp_sink_present; 1435 1436 struct dp_trace dp_trace; 1437 1438 /* caps is the same as reported_link_cap. link_traing use 1439 * reported_link_cap. Will clean up. TODO 1440 */ 1441 struct dc_link_settings reported_link_cap; 1442 struct dc_link_settings verified_link_cap; 1443 struct dc_link_settings cur_link_settings; 1444 struct dc_lane_settings cur_lane_setting[LANE_COUNT_DP_MAX]; 1445 struct dc_link_settings preferred_link_setting; 1446 /* preferred_training_settings are override values that 1447 * come from DM. DM is responsible for the memory 1448 * management of the override pointers. 1449 */ 1450 struct dc_link_training_overrides preferred_training_settings; 1451 struct dp_audio_test_data audio_test_data; 1452 1453 uint8_t ddc_hw_inst; 1454 1455 uint8_t hpd_src; 1456 1457 uint8_t link_enc_hw_inst; 1458 /* DIG link encoder ID. Used as index in link encoder resource pool. 1459 * For links with fixed mapping to DIG, this is not changed after dc_link 1460 * object creation. 1461 */ 1462 enum engine_id eng_id; 1463 1464 bool test_pattern_enabled; 1465 union compliance_test_state compliance_test_state; 1466 1467 void *priv; 1468 1469 struct ddc_service *ddc; 1470 1471 enum dp_panel_mode panel_mode; 1472 bool aux_mode; 1473 1474 /* Private to DC core */ 1475 1476 const struct dc *dc; 1477 1478 struct dc_context *ctx; 1479 1480 struct panel_cntl *panel_cntl; 1481 struct link_encoder *link_enc; 1482 struct graphics_object_id link_id; 1483 /* Endpoint type distinguishes display endpoints which do not have entries 1484 * in the BIOS connector table from those that do. Helps when tracking link 1485 * encoder to display endpoint assignments. 1486 */ 1487 enum display_endpoint_type ep_type; 1488 union ddi_channel_mapping ddi_channel_mapping; 1489 struct connector_device_tag_info device_tag; 1490 struct dpcd_caps dpcd_caps; 1491 uint32_t dongle_max_pix_clk; 1492 unsigned short chip_caps; 1493 unsigned int dpcd_sink_count; 1494 struct hdcp_caps hdcp_caps; 1495 enum edp_revision edp_revision; 1496 union dpcd_sink_ext_caps dpcd_sink_ext_caps; 1497 1498 struct psr_settings psr_settings; 1499 1500 /* Drive settings read from integrated info table */ 1501 struct dc_lane_settings bios_forced_drive_settings; 1502 1503 /* Vendor specific LTTPR workaround variables */ 1504 uint8_t vendor_specific_lttpr_link_rate_wa; 1505 bool apply_vendor_specific_lttpr_link_rate_wa; 1506 1507 /* MST record stream using this link */ 1508 struct link_flags { 1509 bool dp_keep_receiver_powered; 1510 bool dp_skip_DID2; 1511 bool dp_skip_reset_segment; 1512 bool dp_skip_fs_144hz; 1513 bool dp_mot_reset_segment; 1514 /* Some USB4 docks do not handle turning off MST DSC once it has been enabled. */ 1515 bool dpia_mst_dsc_always_on; 1516 /* Forced DPIA into TBT3 compatibility mode. */ 1517 bool dpia_forced_tbt3_mode; 1518 bool dongle_mode_timing_override; 1519 bool blank_stream_on_ocs_change; 1520 } wa_flags; 1521 struct link_mst_stream_allocation_table mst_stream_alloc_table; 1522 1523 struct dc_link_status link_status; 1524 struct dprx_states dprx_states; 1525 1526 struct gpio *hpd_gpio; 1527 enum dc_link_fec_state fec_state; 1528 bool link_powered_externally; // Used to bypass hardware sequencing delays when panel is powered down forcibly 1529 1530 struct dc_panel_config panel_config; 1531 struct phy_state phy_state; 1532 // BW ALLOCATON USB4 ONLY 1533 struct dc_dpia_bw_alloc dpia_bw_alloc_config; 1534 }; 1535 1536 /* Return an enumerated dc_link. 1537 * dc_link order is constant and determined at 1538 * boot time. They cannot be created or destroyed. 1539 * Use dc_get_caps() to get number of links. 1540 */ 1541 struct dc_link *dc_get_link_at_index(struct dc *dc, uint32_t link_index); 1542 1543 /* Return instance id of the edp link. Inst 0 is primary edp link. */ 1544 bool dc_get_edp_link_panel_inst(const struct dc *dc, 1545 const struct dc_link *link, 1546 unsigned int *inst_out); 1547 1548 /* Return an array of link pointers to edp links. */ 1549 void dc_get_edp_links(const struct dc *dc, 1550 struct dc_link **edp_links, 1551 int *edp_num); 1552 1553 /* The function initiates detection handshake over the given link. It first 1554 * determines if there are display connections over the link. If so it initiates 1555 * detection protocols supported by the connected receiver device. The function 1556 * contains protocol specific handshake sequences which are sometimes mandatory 1557 * to establish a proper connection between TX and RX. So it is always 1558 * recommended to call this function as the first link operation upon HPD event 1559 * or power up event. Upon completion, the function will update link structure 1560 * in place based on latest RX capabilities. The function may also cause dpms 1561 * to be reset to off for all currently enabled streams to the link. It is DM's 1562 * responsibility to serialize detection and DPMS updates. 1563 * 1564 * @reason - Indicate which event triggers this detection. dc may customize 1565 * detection flow depending on the triggering events. 1566 * return false - if detection is not fully completed. This could happen when 1567 * there is an unrecoverable error during detection or detection is partially 1568 * completed (detection has been delegated to dm mst manager ie. 1569 * link->connection_type == dc_connection_mst_branch when returning false). 1570 * return true - detection is completed, link has been fully updated with latest 1571 * detection result. 1572 */ 1573 bool dc_link_detect(struct dc_link *link, enum dc_detect_reason reason); 1574 1575 struct dc_sink_init_data; 1576 1577 /* When link connection type is dc_connection_mst_branch, remote sink can be 1578 * added to the link. The interface creates a remote sink and associates it with 1579 * current link. The sink will be retained by link until remove remote sink is 1580 * called. 1581 * 1582 * @dc_link - link the remote sink will be added to. 1583 * @edid - byte array of EDID raw data. 1584 * @len - size of the edid in byte 1585 * @init_data - 1586 */ 1587 struct dc_sink *dc_link_add_remote_sink( 1588 struct dc_link *dc_link, 1589 const uint8_t *edid, 1590 int len, 1591 struct dc_sink_init_data *init_data); 1592 1593 /* Remove remote sink from a link with dc_connection_mst_branch connection type. 1594 * @link - link the sink should be removed from 1595 * @sink - sink to be removed. 1596 */ 1597 void dc_link_remove_remote_sink( 1598 struct dc_link *link, 1599 struct dc_sink *sink); 1600 1601 /* Enable HPD interrupt handler for a given link */ 1602 void dc_link_enable_hpd(const struct dc_link *link); 1603 1604 /* Disable HPD interrupt handler for a given link */ 1605 void dc_link_disable_hpd(const struct dc_link *link); 1606 1607 /* determine if there is a sink connected to the link 1608 * 1609 * @type - dc_connection_single if connected, dc_connection_none otherwise. 1610 * return - false if an unexpected error occurs, true otherwise. 1611 * 1612 * NOTE: This function doesn't detect downstream sink connections i.e 1613 * dc_connection_mst_branch, dc_connection_sst_branch. In this case, it will 1614 * return dc_connection_single if the branch device is connected despite of 1615 * downstream sink's connection status. 1616 */ 1617 bool dc_link_detect_connection_type(struct dc_link *link, 1618 enum dc_connection_type *type); 1619 1620 /* query current hpd pin value 1621 * return - true HPD is asserted (HPD high), false otherwise (HPD low) 1622 * 1623 */ 1624 bool dc_link_get_hpd_state(struct dc_link *link); 1625 1626 /* Getter for cached link status from given link */ 1627 const struct dc_link_status *dc_link_get_status(const struct dc_link *link); 1628 1629 /* enable/disable hardware HPD filter. 1630 * 1631 * @link - The link the HPD pin is associated with. 1632 * @enable = true - enable hardware HPD filter. HPD event will only queued to irq 1633 * handler once after no HPD change has been detected within dc default HPD 1634 * filtering interval since last HPD event. i.e if display keeps toggling hpd 1635 * pulses within default HPD interval, no HPD event will be received until HPD 1636 * toggles have stopped. Then HPD event will be queued to irq handler once after 1637 * dc default HPD filtering interval since last HPD event. 1638 * 1639 * @enable = false - disable hardware HPD filter. HPD event will be queued 1640 * immediately to irq handler after no HPD change has been detected within 1641 * IRQ_HPD (aka HPD short pulse) interval (i.e 2ms). 1642 */ 1643 void dc_link_enable_hpd_filter(struct dc_link *link, bool enable); 1644 1645 /* submit i2c read/write payloads through ddc channel 1646 * @link_index - index to a link with ddc in i2c mode 1647 * @cmd - i2c command structure 1648 * return - true if success, false otherwise. 1649 */ 1650 bool dc_submit_i2c( 1651 struct dc *dc, 1652 uint32_t link_index, 1653 struct i2c_command *cmd); 1654 1655 /* submit i2c read/write payloads through oem channel 1656 * @link_index - index to a link with ddc in i2c mode 1657 * @cmd - i2c command structure 1658 * return - true if success, false otherwise. 1659 */ 1660 bool dc_submit_i2c_oem( 1661 struct dc *dc, 1662 struct i2c_command *cmd); 1663 1664 enum aux_return_code_type; 1665 /* Attempt to transfer the given aux payload. This function does not perform 1666 * retries or handle error states. The reply is returned in the payload->reply 1667 * and the result through operation_result. Returns the number of bytes 1668 * transferred,or -1 on a failure. 1669 */ 1670 int dc_link_aux_transfer_raw(struct ddc_service *ddc, 1671 struct aux_payload *payload, 1672 enum aux_return_code_type *operation_result); 1673 1674 bool dc_is_oem_i2c_device_present( 1675 struct dc *dc, 1676 size_t slave_address 1677 ); 1678 1679 /* return true if the connected receiver supports the hdcp version */ 1680 bool dc_link_is_hdcp14(struct dc_link *link, enum signal_type signal); 1681 bool dc_link_is_hdcp22(struct dc_link *link, enum signal_type signal); 1682 1683 /* Notify DC about DP RX Interrupt (aka DP IRQ_HPD). 1684 * 1685 * TODO - When defer_handling is true the function will have a different purpose. 1686 * It no longer does complete hpd rx irq handling. We should create a separate 1687 * interface specifically for this case. 1688 * 1689 * Return: 1690 * true - Downstream port status changed. DM should call DC to do the 1691 * detection. 1692 * false - no change in Downstream port status. No further action required 1693 * from DM. 1694 */ 1695 bool dc_link_handle_hpd_rx_irq(struct dc_link *dc_link, 1696 union hpd_irq_data *hpd_irq_dpcd_data, bool *out_link_loss, 1697 bool defer_handling, bool *has_left_work); 1698 /* handle DP specs define test automation sequence*/ 1699 void dc_link_dp_handle_automated_test(struct dc_link *link); 1700 1701 /* handle DP Link loss sequence and try to recover RX link loss with best 1702 * effort 1703 */ 1704 void dc_link_dp_handle_link_loss(struct dc_link *link); 1705 1706 /* Determine if hpd rx irq should be handled or ignored 1707 * return true - hpd rx irq should be handled. 1708 * return false - it is safe to ignore hpd rx irq event 1709 */ 1710 bool dc_link_dp_allow_hpd_rx_irq(const struct dc_link *link); 1711 1712 /* Determine if link loss is indicated with a given hpd_irq_dpcd_data. 1713 * @link - link the hpd irq data associated with 1714 * @hpd_irq_dpcd_data - input hpd irq data 1715 * return - true if hpd irq data indicates a link lost 1716 */ 1717 bool dc_link_check_link_loss_status(struct dc_link *link, 1718 union hpd_irq_data *hpd_irq_dpcd_data); 1719 1720 /* Read hpd rx irq data from a given link 1721 * @link - link where the hpd irq data should be read from 1722 * @irq_data - output hpd irq data 1723 * return - DC_OK if hpd irq data is read successfully, otherwise hpd irq data 1724 * read has failed. 1725 */ 1726 enum dc_status dc_link_dp_read_hpd_rx_irq_data( 1727 struct dc_link *link, 1728 union hpd_irq_data *irq_data); 1729 1730 /* The function clears recorded DP RX states in the link. DM should call this 1731 * function when it is resuming from S3 power state to previously connected links. 1732 * 1733 * TODO - in the future we should consider to expand link resume interface to 1734 * support clearing previous rx states. So we don't have to rely on dm to call 1735 * this interface explicitly. 1736 */ 1737 void dc_link_clear_dprx_states(struct dc_link *link); 1738 1739 /* Destruct the mst topology of the link and reset the allocated payload table 1740 * 1741 * NOTE: this should only be called if DM chooses not to call dc_link_detect but 1742 * still wants to reset MST topology on an unplug event */ 1743 bool dc_link_reset_cur_dp_mst_topology(struct dc_link *link); 1744 1745 /* The function calculates effective DP link bandwidth when a given link is 1746 * using the given link settings. 1747 * 1748 * return - total effective link bandwidth in kbps. 1749 */ 1750 uint32_t dc_link_bandwidth_kbps( 1751 const struct dc_link *link, 1752 const struct dc_link_settings *link_setting); 1753 1754 /* The function takes a snapshot of current link resource allocation state 1755 * @dc: pointer to dc of the dm calling this 1756 * @map: a dc link resource snapshot defined internally to dc. 1757 * 1758 * DM needs to capture a snapshot of current link resource allocation mapping 1759 * and store it in its persistent storage. 1760 * 1761 * Some of the link resource is using first come first serve policy. 1762 * The allocation mapping depends on original hotplug order. This information 1763 * is lost after driver is loaded next time. The snapshot is used in order to 1764 * restore link resource to its previous state so user will get consistent 1765 * link capability allocation across reboot. 1766 * 1767 */ 1768 void dc_get_cur_link_res_map(const struct dc *dc, uint32_t *map); 1769 1770 /* This function restores link resource allocation state from a snapshot 1771 * @dc: pointer to dc of the dm calling this 1772 * @map: a dc link resource snapshot defined internally to dc. 1773 * 1774 * DM needs to call this function after initial link detection on boot and 1775 * before first commit streams to restore link resource allocation state 1776 * from previous boot session. 1777 * 1778 * Some of the link resource is using first come first serve policy. 1779 * The allocation mapping depends on original hotplug order. This information 1780 * is lost after driver is loaded next time. The snapshot is used in order to 1781 * restore link resource to its previous state so user will get consistent 1782 * link capability allocation across reboot. 1783 * 1784 */ 1785 void dc_restore_link_res_map(const struct dc *dc, uint32_t *map); 1786 1787 /* TODO: this is not meant to be exposed to DM. Should switch to stream update 1788 * interface i.e stream_update->dsc_config 1789 */ 1790 bool dc_link_update_dsc_config(struct pipe_ctx *pipe_ctx); 1791 1792 /* translate a raw link rate data to bandwidth in kbps */ 1793 uint32_t dc_link_bw_kbps_from_raw_frl_link_rate_data(const struct dc *dc, uint8_t bw); 1794 1795 /* determine the optimal bandwidth given link and required bw. 1796 * @link - current detected link 1797 * @req_bw - requested bandwidth in kbps 1798 * @link_settings - returned most optimal link settings that can fit the 1799 * requested bandwidth 1800 * return - false if link can't support requested bandwidth, true if link 1801 * settings is found. 1802 */ 1803 bool dc_link_decide_edp_link_settings(struct dc_link *link, 1804 struct dc_link_settings *link_settings, 1805 uint32_t req_bw); 1806 1807 /* return the max dp link settings can be driven by the link without considering 1808 * connected RX device and its capability 1809 */ 1810 bool dc_link_dp_get_max_link_enc_cap(const struct dc_link *link, 1811 struct dc_link_settings *max_link_enc_cap); 1812 1813 /* determine when the link is driving MST mode, what DP link channel coding 1814 * format will be used. The decision will remain unchanged until next HPD event. 1815 * 1816 * @link - a link with DP RX connection 1817 * return - if stream is committed to this link with MST signal type, type of 1818 * channel coding format dc will choose. 1819 */ 1820 enum dp_link_encoding dc_link_dp_mst_decide_link_encoding_format( 1821 const struct dc_link *link); 1822 1823 /* get max dp link settings the link can enable with all things considered. (i.e 1824 * TX/RX/Cable capabilities and dp override policies. 1825 * 1826 * @link - a link with DP RX connection 1827 * return - max dp link settings the link can enable. 1828 * 1829 */ 1830 const struct dc_link_settings *dc_link_get_link_cap(const struct dc_link *link); 1831 1832 /* Check if a RX (ex. DP sink, MST hub, passive or active dongle) is connected 1833 * to a link with dp connector signal type. 1834 * @link - a link with dp connector signal type 1835 * return - true if connected, false otherwise 1836 */ 1837 bool dc_link_is_dp_sink_present(struct dc_link *link); 1838 1839 /* Force DP lane settings update to main-link video signal and notify the change 1840 * to DP RX via DPCD. This is a debug interface used for video signal integrity 1841 * tuning purpose. The interface assumes link has already been enabled with DP 1842 * signal. 1843 * 1844 * @lt_settings - a container structure with desired hw_lane_settings 1845 */ 1846 void dc_link_set_drive_settings(struct dc *dc, 1847 struct link_training_settings *lt_settings, 1848 struct dc_link *link); 1849 1850 /* Enable a test pattern in Link or PHY layer in an active link for compliance 1851 * test or debugging purpose. The test pattern will remain until next un-plug. 1852 * 1853 * @link - active link with DP signal output enabled. 1854 * @test_pattern - desired test pattern to output. 1855 * NOTE: set to DP_TEST_PATTERN_VIDEO_MODE to disable previous test pattern. 1856 * @test_pattern_color_space - for video test pattern choose a desired color 1857 * space. 1858 * @p_link_settings - For PHY pattern choose a desired link settings 1859 * @p_custom_pattern - some test pattern will require a custom input to 1860 * customize some pattern details. Otherwise keep it to NULL. 1861 * @cust_pattern_size - size of the custom pattern input. 1862 * 1863 */ 1864 bool dc_link_dp_set_test_pattern( 1865 struct dc_link *link, 1866 enum dp_test_pattern test_pattern, 1867 enum dp_test_pattern_color_space test_pattern_color_space, 1868 const struct link_training_settings *p_link_settings, 1869 const unsigned char *p_custom_pattern, 1870 unsigned int cust_pattern_size); 1871 1872 /* Force DP link settings to always use a specific value until reboot to a 1873 * specific link. If link has already been enabled, the interface will also 1874 * switch to desired link settings immediately. This is a debug interface to 1875 * generic dp issue trouble shooting. 1876 */ 1877 void dc_link_set_preferred_link_settings(struct dc *dc, 1878 struct dc_link_settings *link_setting, 1879 struct dc_link *link); 1880 1881 /* Force DP link to customize a specific link training behavior by overriding to 1882 * standard DP specs defined protocol. This is a debug interface to trouble shoot 1883 * display specific link training issues or apply some display specific 1884 * workaround in link training. 1885 * 1886 * @link_settings - if not NULL, force preferred link settings to the link. 1887 * @lt_override - a set of override pointers. If any pointer is none NULL, dc 1888 * will apply this particular override in future link training. If NULL is 1889 * passed in, dc resets previous overrides. 1890 * NOTE: DM must keep the memory from override pointers until DM resets preferred 1891 * training settings. 1892 */ 1893 void dc_link_set_preferred_training_settings(struct dc *dc, 1894 struct dc_link_settings *link_setting, 1895 struct dc_link_training_overrides *lt_overrides, 1896 struct dc_link *link, 1897 bool skip_immediate_retrain); 1898 1899 /* return - true if FEC is supported with connected DP RX, false otherwise */ 1900 bool dc_link_is_fec_supported(const struct dc_link *link); 1901 1902 /* query FEC enablement policy to determine if FEC will be enabled by dc during 1903 * link enablement. 1904 * return - true if FEC should be enabled, false otherwise. 1905 */ 1906 bool dc_link_should_enable_fec(const struct dc_link *link); 1907 1908 /* determine lttpr mode the current link should be enabled with a specific link 1909 * settings. 1910 */ 1911 enum lttpr_mode dc_link_decide_lttpr_mode(struct dc_link *link, 1912 struct dc_link_settings *link_setting); 1913 1914 /* Force DP RX to update its power state. 1915 * NOTE: this interface doesn't update dp main-link. Calling this function will 1916 * cause DP TX main-link and DP RX power states out of sync. DM has to restore 1917 * RX power state back upon finish DM specific execution requiring DP RX in a 1918 * specific power state. 1919 * @on - true to set DP RX in D0 power state, false to set DP RX in D3 power 1920 * state. 1921 */ 1922 void dc_link_dp_receiver_power_ctrl(struct dc_link *link, bool on); 1923 1924 /* Force link to read base dp receiver caps from dpcd 000h - 00Fh and overwrite 1925 * current value read from extended receiver cap from 02200h - 0220Fh. 1926 * Some DP RX has problems of providing accurate DP receiver caps from extended 1927 * field, this interface is a workaround to revert link back to use base caps. 1928 */ 1929 void dc_link_overwrite_extended_receiver_cap( 1930 struct dc_link *link); 1931 1932 void dc_link_edp_panel_backlight_power_on(struct dc_link *link, 1933 bool wait_for_hpd); 1934 1935 /* Set backlight level of an embedded panel (eDP, LVDS). 1936 * backlight_pwm_u16_16 is unsigned 32 bit with 16 bit integer 1937 * and 16 bit fractional, where 1.0 is max backlight value. 1938 */ 1939 bool dc_link_set_backlight_level(const struct dc_link *dc_link, 1940 uint32_t backlight_pwm_u16_16, 1941 uint32_t frame_ramp); 1942 1943 /* Set/get nits-based backlight level of an embedded panel (eDP, LVDS). */ 1944 bool dc_link_set_backlight_level_nits(struct dc_link *link, 1945 bool isHDR, 1946 uint32_t backlight_millinits, 1947 uint32_t transition_time_in_ms); 1948 1949 bool dc_link_get_backlight_level_nits(struct dc_link *link, 1950 uint32_t *backlight_millinits, 1951 uint32_t *backlight_millinits_peak); 1952 1953 int dc_link_get_backlight_level(const struct dc_link *dc_link); 1954 1955 int dc_link_get_target_backlight_pwm(const struct dc_link *link); 1956 1957 bool dc_link_set_psr_allow_active(struct dc_link *dc_link, const bool *enable, 1958 bool wait, bool force_static, const unsigned int *power_opts); 1959 1960 bool dc_link_get_psr_state(const struct dc_link *dc_link, enum dc_psr_state *state); 1961 1962 bool dc_link_setup_psr(struct dc_link *dc_link, 1963 const struct dc_stream_state *stream, struct psr_config *psr_config, 1964 struct psr_context *psr_context); 1965 1966 /* On eDP links this function call will stall until T12 has elapsed. 1967 * If the panel is not in power off state, this function will return 1968 * immediately. 1969 */ 1970 bool dc_link_wait_for_t12(struct dc_link *link); 1971 1972 /* Determine if dp trace has been initialized to reflect upto date result * 1973 * return - true if trace is initialized and has valid data. False dp trace 1974 * doesn't have valid result. 1975 */ 1976 bool dc_dp_trace_is_initialized(struct dc_link *link); 1977 1978 /* Query a dp trace flag to indicate if the current dp trace data has been 1979 * logged before 1980 */ 1981 bool dc_dp_trace_is_logged(struct dc_link *link, 1982 bool in_detection); 1983 1984 /* Set dp trace flag to indicate whether DM has already logged the current dp 1985 * trace data. DM can set is_logged to true upon logging and check 1986 * dc_dp_trace_is_logged before logging to avoid logging the same result twice. 1987 */ 1988 void dc_dp_trace_set_is_logged_flag(struct dc_link *link, 1989 bool in_detection, 1990 bool is_logged); 1991 1992 /* Obtain driver time stamp for last dp link training end. The time stamp is 1993 * formatted based on dm_get_timestamp DM function. 1994 * @in_detection - true to get link training end time stamp of last link 1995 * training in detection sequence. false to get link training end time stamp 1996 * of last link training in commit (dpms) sequence 1997 */ 1998 unsigned long long dc_dp_trace_get_lt_end_timestamp(struct dc_link *link, 1999 bool in_detection); 2000 2001 /* Get how many link training attempts dc has done with latest sequence. 2002 * @in_detection - true to get link training count of last link 2003 * training in detection sequence. false to get link training count of last link 2004 * training in commit (dpms) sequence 2005 */ 2006 const struct dp_trace_lt_counts *dc_dp_trace_get_lt_counts(struct dc_link *link, 2007 bool in_detection); 2008 2009 /* Get how many link loss has happened since last link training attempts */ 2010 unsigned int dc_dp_trace_get_link_loss_count(struct dc_link *link); 2011 2012 /* 2013 * USB4 DPIA BW ALLOCATION PUBLIC FUNCTIONS 2014 */ 2015 /* 2016 * Send a request from DP-Tx requesting to allocate BW remotely after 2017 * allocating it locally. This will get processed by CM and a CB function 2018 * will be called. 2019 * 2020 * @link: pointer to the dc_link struct instance 2021 * @req_bw: The requested bw in Kbyte to allocated 2022 * 2023 * return: none 2024 */ 2025 void dc_link_set_usb4_req_bw_req(struct dc_link *link, int req_bw); 2026 2027 /* 2028 * Handle function for when the status of the Request above is complete. 2029 * We will find out the result of allocating on CM and update structs. 2030 * 2031 * @link: pointer to the dc_link struct instance 2032 * @bw: Allocated or Estimated BW depending on the result 2033 * @result: Response type 2034 * 2035 * return: none 2036 */ 2037 void dc_link_handle_usb4_bw_alloc_response(struct dc_link *link, 2038 uint8_t bw, uint8_t result); 2039 2040 /* 2041 * Handle the USB4 BW Allocation related functionality here: 2042 * Plug => Try to allocate max bw from timing parameters supported by the sink 2043 * Unplug => de-allocate bw 2044 * 2045 * @link: pointer to the dc_link struct instance 2046 * @peak_bw: Peak bw used by the link/sink 2047 * 2048 * return: allocated bw else return 0 2049 */ 2050 int dc_link_dp_dpia_handle_usb4_bandwidth_allocation_for_link( 2051 struct dc_link *link, int peak_bw); 2052 2053 /* 2054 * Validate the BW of all the valid DPIA links to make sure it doesn't exceed 2055 * available BW for each host router 2056 * 2057 * @dc: pointer to dc struct 2058 * @stream: pointer to all possible streams 2059 * @num_streams: number of valid DPIA streams 2060 * 2061 * return: TRUE if bw used by DPIAs doesn't exceed available BW else return FALSE 2062 */ 2063 bool dc_link_validate(struct dc *dc, const struct dc_stream_state *streams, 2064 const unsigned int count); 2065 2066 /* Sink Interfaces - A sink corresponds to a display output device */ 2067 2068 struct dc_container_id { 2069 // 128bit GUID in binary form 2070 unsigned char guid[16]; 2071 // 8 byte port ID -> ELD.PortID 2072 unsigned int portId[2]; 2073 // 128bit GUID in binary formufacturer name -> ELD.ManufacturerName 2074 unsigned short manufacturerName; 2075 // 2 byte product code -> ELD.ProductCode 2076 unsigned short productCode; 2077 }; 2078 2079 2080 struct dc_sink_dsc_caps { 2081 // 'true' if these are virtual DPCD's DSC caps (immediately upstream of sink in MST topology), 2082 // 'false' if they are sink's DSC caps 2083 bool is_virtual_dpcd_dsc; 2084 #if defined(CONFIG_DRM_AMD_DC_FP) 2085 // 'true' if MST topology supports DSC passthrough for sink 2086 // 'false' if MST topology does not support DSC passthrough 2087 bool is_dsc_passthrough_supported; 2088 #endif 2089 struct dsc_dec_dpcd_caps dsc_dec_caps; 2090 }; 2091 2092 struct dc_sink_fec_caps { 2093 bool is_rx_fec_supported; 2094 bool is_topology_fec_supported; 2095 }; 2096 2097 struct scdc_caps { 2098 union hdmi_scdc_manufacturer_OUI_data manufacturer_OUI; 2099 union hdmi_scdc_device_id_data device_id; 2100 }; 2101 2102 /* 2103 * The sink structure contains EDID and other display device properties 2104 */ 2105 struct dc_sink { 2106 enum signal_type sink_signal; 2107 struct dc_edid dc_edid; /* raw edid */ 2108 struct dc_edid_caps edid_caps; /* parse display caps */ 2109 struct dc_container_id *dc_container_id; 2110 uint32_t dongle_max_pix_clk; 2111 void *priv; 2112 struct stereo_3d_features features_3d[TIMING_3D_FORMAT_MAX]; 2113 bool converter_disable_audio; 2114 2115 struct scdc_caps scdc_caps; 2116 struct dc_sink_dsc_caps dsc_caps; 2117 struct dc_sink_fec_caps fec_caps; 2118 2119 bool is_vsc_sdp_colorimetry_supported; 2120 2121 /* private to DC core */ 2122 struct dc_link *link; 2123 struct dc_context *ctx; 2124 2125 uint32_t sink_id; 2126 2127 /* private to dc_sink.c */ 2128 // refcount must be the last member in dc_sink, since we want the 2129 // sink structure to be logically cloneable up to (but not including) 2130 // refcount 2131 struct kref refcount; 2132 }; 2133 2134 void dc_sink_retain(struct dc_sink *sink); 2135 void dc_sink_release(struct dc_sink *sink); 2136 2137 struct dc_sink_init_data { 2138 enum signal_type sink_signal; 2139 struct dc_link *link; 2140 uint32_t dongle_max_pix_clk; 2141 bool converter_disable_audio; 2142 }; 2143 2144 struct dc_sink *dc_sink_create(const struct dc_sink_init_data *init_params); 2145 2146 /* Newer interfaces */ 2147 struct dc_cursor { 2148 struct dc_plane_address address; 2149 struct dc_cursor_attributes attributes; 2150 }; 2151 2152 2153 /* Interrupt interfaces */ 2154 enum dc_irq_source dc_interrupt_to_irq_source( 2155 struct dc *dc, 2156 uint32_t src_id, 2157 uint32_t ext_id); 2158 bool dc_interrupt_set(struct dc *dc, enum dc_irq_source src, bool enable); 2159 void dc_interrupt_ack(struct dc *dc, enum dc_irq_source src); 2160 enum dc_irq_source dc_get_hpd_irq_source_at_index( 2161 struct dc *dc, uint32_t link_index); 2162 2163 void dc_notify_vsync_int_state(struct dc *dc, struct dc_stream_state *stream, bool enable); 2164 2165 /* Power Interfaces */ 2166 2167 void dc_set_power_state( 2168 struct dc *dc, 2169 enum dc_acpi_cm_power_state power_state); 2170 void dc_resume(struct dc *dc); 2171 2172 void dc_power_down_on_boot(struct dc *dc); 2173 2174 /* 2175 * HDCP Interfaces 2176 */ 2177 enum hdcp_message_status dc_process_hdcp_msg( 2178 enum signal_type signal, 2179 struct dc_link *link, 2180 struct hdcp_protection_message *message_info); 2181 bool dc_is_dmcu_initialized(struct dc *dc); 2182 2183 enum dc_status dc_set_clock(struct dc *dc, enum dc_clock_type clock_type, uint32_t clk_khz, uint32_t stepping); 2184 void dc_get_clock(struct dc *dc, enum dc_clock_type clock_type, struct dc_clock_config *clock_cfg); 2185 2186 bool dc_is_plane_eligible_for_idle_optimizations(struct dc *dc, struct dc_plane_state *plane, 2187 struct dc_cursor_attributes *cursor_attr); 2188 2189 void dc_allow_idle_optimizations(struct dc *dc, bool allow); 2190 2191 /* set min and max memory clock to lowest and highest DPM level, respectively */ 2192 void dc_unlock_memory_clock_frequency(struct dc *dc); 2193 2194 /* set min memory clock to the min required for current mode, max to maxDPM */ 2195 void dc_lock_memory_clock_frequency(struct dc *dc); 2196 2197 /* set soft max for memclk, to be used for AC/DC switching clock limitations */ 2198 void dc_enable_dcmode_clk_limit(struct dc *dc, bool enable); 2199 2200 /* cleanup on driver unload */ 2201 void dc_hardware_release(struct dc *dc); 2202 2203 /* disables fw based mclk switch */ 2204 void dc_mclk_switch_using_fw_based_vblank_stretch_shut_down(struct dc *dc); 2205 2206 bool dc_set_psr_allow_active(struct dc *dc, bool enable); 2207 void dc_z10_restore(const struct dc *dc); 2208 void dc_z10_save_init(struct dc *dc); 2209 2210 bool dc_is_dmub_outbox_supported(struct dc *dc); 2211 bool dc_enable_dmub_notifications(struct dc *dc); 2212 2213 void dc_enable_dmub_outbox(struct dc *dc); 2214 2215 bool dc_process_dmub_aux_transfer_async(struct dc *dc, 2216 uint32_t link_index, 2217 struct aux_payload *payload); 2218 2219 /* Get dc link index from dpia port index */ 2220 uint8_t get_link_index_from_dpia_port_index(const struct dc *dc, 2221 uint8_t dpia_port_index); 2222 2223 bool dc_process_dmub_set_config_async(struct dc *dc, 2224 uint32_t link_index, 2225 struct set_config_cmd_payload *payload, 2226 struct dmub_notification *notify); 2227 2228 enum dc_status dc_process_dmub_set_mst_slots(const struct dc *dc, 2229 uint32_t link_index, 2230 uint8_t mst_alloc_slots, 2231 uint8_t *mst_slots_in_use); 2232 2233 void dc_process_dmub_dpia_hpd_int_enable(const struct dc *dc, 2234 uint32_t hpd_int_enable); 2235 2236 /* DSC Interfaces */ 2237 #include "dc_dsc.h" 2238 2239 /* Disable acc mode Interfaces */ 2240 void dc_disable_accelerated_mode(struct dc *dc); 2241 2242 bool dc_is_timing_changed(struct dc_stream_state *cur_stream, 2243 struct dc_stream_state *new_stream); 2244 2245 #endif /* DC_INTERFACE_H_ */ 2246