1 /* 2 * Copyright 2012-14 Advanced Micro Devices, Inc. 3 * 4 * Permission is hereby granted, free of charge, to any person obtaining a 5 * copy of this software and associated documentation files (the "Software"), 6 * to deal in the Software without restriction, including without limitation 7 * the rights to use, copy, modify, merge, publish, distribute, sublicense, 8 * and/or sell copies of the Software, and to permit persons to whom the 9 * Software is furnished to do so, subject to the following conditions: 10 * 11 * The above copyright notice and this permission notice shall be included in 12 * all copies or substantial portions of the Software. 13 * 14 * THE SOFTWARE IS PROVIDED "AS IS", WITHOUT WARRANTY OF ANY KIND, EXPRESS OR 15 * IMPLIED, INCLUDING BUT NOT LIMITED TO THE WARRANTIES OF MERCHANTABILITY, 16 * FITNESS FOR A PARTICULAR PURPOSE AND NONINFRINGEMENT. IN NO EVENT SHALL 17 * THE COPYRIGHT HOLDER(S) OR AUTHOR(S) BE LIABLE FOR ANY CLAIM, DAMAGES OR 18 * OTHER LIABILITY, WHETHER IN AN ACTION OF CONTRACT, TORT OR OTHERWISE, 19 * ARISING FROM, OUT OF OR IN CONNECTION WITH THE SOFTWARE OR THE USE OR 20 * OTHER DEALINGS IN THE SOFTWARE. 21 * 22 * Authors: AMD 23 * 24 */ 25 26 #ifndef DC_INTERFACE_H_ 27 #define DC_INTERFACE_H_ 28 29 #include "dc_types.h" 30 #include "grph_object_defs.h" 31 #include "logger_types.h" 32 #if defined(CONFIG_DRM_AMD_DC_HDCP) 33 #include "hdcp_types.h" 34 #endif 35 #include "gpio_types.h" 36 #include "link_service_types.h" 37 #include "grph_object_ctrl_defs.h" 38 #include <inc/hw/opp.h> 39 40 #include "inc/hw_sequencer.h" 41 #include "inc/compressor.h" 42 #include "inc/hw/dmcu.h" 43 #include "dml/display_mode_lib.h" 44 45 /* forward declaration */ 46 struct aux_payload; 47 struct set_config_cmd_payload; 48 struct dmub_notification; 49 50 #define DC_VER "3.2.198" 51 52 #define MAX_SURFACES 3 53 #define MAX_PLANES 6 54 #define MAX_STREAMS 6 55 #define MAX_SINKS_PER_LINK 4 56 #define MIN_VIEWPORT_SIZE 12 57 #define MAX_NUM_EDP 2 58 59 /******************************************************************************* 60 * Display Core Interfaces 61 ******************************************************************************/ 62 struct dc_versions { 63 const char *dc_ver; 64 struct dmcu_version dmcu_version; 65 }; 66 67 enum dp_protocol_version { 68 DP_VERSION_1_4, 69 }; 70 71 enum dc_plane_type { 72 DC_PLANE_TYPE_INVALID, 73 DC_PLANE_TYPE_DCE_RGB, 74 DC_PLANE_TYPE_DCE_UNDERLAY, 75 DC_PLANE_TYPE_DCN_UNIVERSAL, 76 }; 77 78 // Sizes defined as multiples of 64KB 79 enum det_size { 80 DET_SIZE_DEFAULT = 0, 81 DET_SIZE_192KB = 3, 82 DET_SIZE_256KB = 4, 83 DET_SIZE_320KB = 5, 84 DET_SIZE_384KB = 6 85 }; 86 87 88 struct dc_plane_cap { 89 enum dc_plane_type type; 90 uint32_t blends_with_above : 1; 91 uint32_t blends_with_below : 1; 92 uint32_t per_pixel_alpha : 1; 93 struct { 94 uint32_t argb8888 : 1; 95 uint32_t nv12 : 1; 96 uint32_t fp16 : 1; 97 uint32_t p010 : 1; 98 uint32_t ayuv : 1; 99 } pixel_format_support; 100 // max upscaling factor x1000 101 // upscaling factors are always >= 1 102 // for example, 1080p -> 8K is 4.0, or 4000 raw value 103 struct { 104 uint32_t argb8888; 105 uint32_t nv12; 106 uint32_t fp16; 107 } max_upscale_factor; 108 // max downscale factor x1000 109 // downscale factors are always <= 1 110 // for example, 8K -> 1080p is 0.25, or 250 raw value 111 struct { 112 uint32_t argb8888; 113 uint32_t nv12; 114 uint32_t fp16; 115 } max_downscale_factor; 116 // minimal width/height 117 uint32_t min_width; 118 uint32_t min_height; 119 }; 120 121 // Color management caps (DPP and MPC) 122 struct rom_curve_caps { 123 uint16_t srgb : 1; 124 uint16_t bt2020 : 1; 125 uint16_t gamma2_2 : 1; 126 uint16_t pq : 1; 127 uint16_t hlg : 1; 128 }; 129 130 struct dpp_color_caps { 131 uint16_t dcn_arch : 1; // all DCE generations treated the same 132 // input lut is different than most LUTs, just plain 256-entry lookup 133 uint16_t input_lut_shared : 1; // shared with DGAM 134 uint16_t icsc : 1; 135 uint16_t dgam_ram : 1; 136 uint16_t post_csc : 1; // before gamut remap 137 uint16_t gamma_corr : 1; 138 139 // hdr_mult and gamut remap always available in DPP (in that order) 140 // 3d lut implies shaper LUT, 141 // it may be shared with MPC - check MPC:shared_3d_lut flag 142 uint16_t hw_3d_lut : 1; 143 uint16_t ogam_ram : 1; // blnd gam 144 uint16_t ocsc : 1; 145 uint16_t dgam_rom_for_yuv : 1; 146 struct rom_curve_caps dgam_rom_caps; 147 struct rom_curve_caps ogam_rom_caps; 148 }; 149 150 struct mpc_color_caps { 151 uint16_t gamut_remap : 1; 152 uint16_t ogam_ram : 1; 153 uint16_t ocsc : 1; 154 uint16_t num_3dluts : 3; //3d lut always assumes a preceding shaper LUT 155 uint16_t shared_3d_lut:1; //can be in either DPP or MPC, but single instance 156 157 struct rom_curve_caps ogam_rom_caps; 158 }; 159 160 struct dc_color_caps { 161 struct dpp_color_caps dpp; 162 struct mpc_color_caps mpc; 163 }; 164 165 struct dc_dmub_caps { 166 bool psr; 167 bool mclk_sw; 168 }; 169 170 struct dc_caps { 171 uint32_t max_streams; 172 uint32_t max_links; 173 uint32_t max_audios; 174 uint32_t max_slave_planes; 175 uint32_t max_slave_yuv_planes; 176 uint32_t max_slave_rgb_planes; 177 uint32_t max_planes; 178 uint32_t max_downscale_ratio; 179 uint32_t i2c_speed_in_khz; 180 uint32_t i2c_speed_in_khz_hdcp; 181 uint32_t dmdata_alloc_size; 182 unsigned int max_cursor_size; 183 unsigned int max_video_width; 184 unsigned int min_horizontal_blanking_period; 185 int linear_pitch_alignment; 186 bool dcc_const_color; 187 bool dynamic_audio; 188 bool is_apu; 189 bool dual_link_dvi; 190 bool post_blend_color_processing; 191 bool force_dp_tps4_for_cp2520; 192 bool disable_dp_clk_share; 193 bool psp_setup_panel_mode; 194 bool extended_aux_timeout_support; 195 bool dmcub_support; 196 bool zstate_support; 197 uint32_t num_of_internal_disp; 198 enum dp_protocol_version max_dp_protocol_version; 199 unsigned int mall_size_per_mem_channel; 200 unsigned int mall_size_total; 201 unsigned int cursor_cache_size; 202 struct dc_plane_cap planes[MAX_PLANES]; 203 struct dc_color_caps color; 204 struct dc_dmub_caps dmub_caps; 205 bool dp_hpo; 206 bool dp_hdmi21_pcon_support; 207 bool edp_dsc_support; 208 bool vbios_lttpr_aware; 209 bool vbios_lttpr_enable; 210 uint32_t max_otg_num; 211 uint32_t max_cab_allocation_bytes; 212 uint32_t cache_line_size; 213 uint32_t cache_num_ways; 214 uint16_t subvp_fw_processing_delay_us; 215 uint16_t subvp_prefetch_end_to_mall_start_us; 216 uint8_t subvp_swath_height_margin_lines; // subvp start line must be aligned to 2 x swath height 217 uint16_t subvp_pstate_allow_width_us; 218 uint16_t subvp_vertical_int_margin_us; 219 bool seamless_odm; 220 }; 221 222 struct dc_bug_wa { 223 bool no_connect_phy_config; 224 bool dedcn20_305_wa; 225 bool skip_clock_update; 226 bool lt_early_cr_pattern; 227 }; 228 229 struct dc_dcc_surface_param { 230 struct dc_size surface_size; 231 enum surface_pixel_format format; 232 enum swizzle_mode_values swizzle_mode; 233 enum dc_scan_direction scan; 234 }; 235 236 struct dc_dcc_setting { 237 unsigned int max_compressed_blk_size; 238 unsigned int max_uncompressed_blk_size; 239 bool independent_64b_blks; 240 //These bitfields to be used starting with DCN 241 struct { 242 uint32_t dcc_256_64_64 : 1;//available in ASICs before DCN (the worst compression case) 243 uint32_t dcc_128_128_uncontrained : 1; //available in ASICs before DCN 244 uint32_t dcc_256_128_128 : 1; //available starting with DCN 245 uint32_t dcc_256_256_unconstrained : 1; //available in ASICs before DCN (the best compression case) 246 } dcc_controls; 247 }; 248 249 struct dc_surface_dcc_cap { 250 union { 251 struct { 252 struct dc_dcc_setting rgb; 253 } grph; 254 255 struct { 256 struct dc_dcc_setting luma; 257 struct dc_dcc_setting chroma; 258 } video; 259 }; 260 261 bool capable; 262 bool const_color_support; 263 }; 264 265 struct dc_static_screen_params { 266 struct { 267 bool force_trigger; 268 bool cursor_update; 269 bool surface_update; 270 bool overlay_update; 271 } triggers; 272 unsigned int num_frames; 273 }; 274 275 276 /* Surface update type is used by dc_update_surfaces_and_stream 277 * The update type is determined at the very beginning of the function based 278 * on parameters passed in and decides how much programming (or updating) is 279 * going to be done during the call. 280 * 281 * UPDATE_TYPE_FAST is used for really fast updates that do not require much 282 * logical calculations or hardware register programming. This update MUST be 283 * ISR safe on windows. Currently fast update will only be used to flip surface 284 * address. 285 * 286 * UPDATE_TYPE_MED is used for slower updates which require significant hw 287 * re-programming however do not affect bandwidth consumption or clock 288 * requirements. At present, this is the level at which front end updates 289 * that do not require us to run bw_calcs happen. These are in/out transfer func 290 * updates, viewport offset changes, recout size changes and pixel depth changes. 291 * This update can be done at ISR, but we want to minimize how often this happens. 292 * 293 * UPDATE_TYPE_FULL is slow. Really slow. This requires us to recalculate our 294 * bandwidth and clocks, possibly rearrange some pipes and reprogram anything front 295 * end related. Any time viewport dimensions, recout dimensions, scaling ratios or 296 * gamma need to be adjusted or pipe needs to be turned on (or disconnected) we do 297 * a full update. This cannot be done at ISR level and should be a rare event. 298 * Unless someone is stress testing mpo enter/exit, playing with colour or adjusting 299 * underscan we don't expect to see this call at all. 300 */ 301 302 enum surface_update_type { 303 UPDATE_TYPE_FAST, /* super fast, safe to execute in isr */ 304 UPDATE_TYPE_MED, /* ISR safe, most of programming needed, no bw/clk change*/ 305 UPDATE_TYPE_FULL, /* may need to shuffle resources */ 306 }; 307 308 /* Forward declaration*/ 309 struct dc; 310 struct dc_plane_state; 311 struct dc_state; 312 313 314 struct dc_cap_funcs { 315 bool (*get_dcc_compression_cap)(const struct dc *dc, 316 const struct dc_dcc_surface_param *input, 317 struct dc_surface_dcc_cap *output); 318 }; 319 320 struct link_training_settings; 321 322 union allow_lttpr_non_transparent_mode { 323 struct { 324 bool DP1_4A : 1; 325 bool DP2_0 : 1; 326 } bits; 327 unsigned char raw; 328 }; 329 330 /* Structure to hold configuration flags set by dm at dc creation. */ 331 struct dc_config { 332 bool gpu_vm_support; 333 bool disable_disp_pll_sharing; 334 bool fbc_support; 335 bool disable_fractional_pwm; 336 bool allow_seamless_boot_optimization; 337 bool seamless_boot_edp_requested; 338 bool edp_not_connected; 339 bool edp_no_power_sequencing; 340 bool force_enum_edp; 341 bool forced_clocks; 342 union allow_lttpr_non_transparent_mode allow_lttpr_non_transparent_mode; 343 bool multi_mon_pp_mclk_switch; 344 bool disable_dmcu; 345 bool enable_4to1MPC; 346 bool enable_windowed_mpo_odm; 347 uint32_t allow_edp_hotplug_detection; 348 bool clamp_min_dcfclk; 349 uint64_t vblank_alignment_dto_params; 350 uint8_t vblank_alignment_max_frame_time_diff; 351 bool is_asymmetric_memory; 352 bool is_single_rank_dimm; 353 bool use_pipe_ctx_sync_logic; 354 bool ignore_dpref_ss; 355 bool enable_mipi_converter_optimization; 356 bool use_default_clock_table; 357 }; 358 359 enum visual_confirm { 360 VISUAL_CONFIRM_DISABLE = 0, 361 VISUAL_CONFIRM_SURFACE = 1, 362 VISUAL_CONFIRM_HDR = 2, 363 VISUAL_CONFIRM_MPCTREE = 4, 364 VISUAL_CONFIRM_PSR = 5, 365 VISUAL_CONFIRM_SWAPCHAIN = 6, 366 VISUAL_CONFIRM_FAMS = 7, 367 VISUAL_CONFIRM_SWIZZLE = 9, 368 }; 369 370 enum dc_psr_power_opts { 371 psr_power_opt_invalid = 0x0, 372 psr_power_opt_smu_opt_static_screen = 0x1, 373 psr_power_opt_z10_static_screen = 0x10, 374 psr_power_opt_ds_disable_allow = 0x100, 375 }; 376 377 enum dml_hostvm_override_opts { 378 DML_HOSTVM_NO_OVERRIDE = 0x0, 379 DML_HOSTVM_OVERRIDE_FALSE = 0x1, 380 DML_HOSTVM_OVERRIDE_TRUE = 0x2, 381 }; 382 383 enum dcc_option { 384 DCC_ENABLE = 0, 385 DCC_DISABLE = 1, 386 DCC_HALF_REQ_DISALBE = 2, 387 }; 388 389 enum pipe_split_policy { 390 MPC_SPLIT_DYNAMIC = 0, 391 MPC_SPLIT_AVOID = 1, 392 MPC_SPLIT_AVOID_MULT_DISP = 2, 393 }; 394 395 enum wm_report_mode { 396 WM_REPORT_DEFAULT = 0, 397 WM_REPORT_OVERRIDE = 1, 398 }; 399 enum dtm_pstate{ 400 dtm_level_p0 = 0,/*highest voltage*/ 401 dtm_level_p1, 402 dtm_level_p2, 403 dtm_level_p3, 404 dtm_level_p4,/*when active_display_count = 0*/ 405 }; 406 407 enum dcn_pwr_state { 408 DCN_PWR_STATE_UNKNOWN = -1, 409 DCN_PWR_STATE_MISSION_MODE = 0, 410 DCN_PWR_STATE_LOW_POWER = 3, 411 }; 412 413 enum dcn_zstate_support_state { 414 DCN_ZSTATE_SUPPORT_UNKNOWN, 415 DCN_ZSTATE_SUPPORT_ALLOW, 416 DCN_ZSTATE_SUPPORT_ALLOW_Z10_ONLY, 417 DCN_ZSTATE_SUPPORT_DISALLOW, 418 }; 419 /* 420 * For any clocks that may differ per pipe 421 * only the max is stored in this structure 422 */ 423 struct dc_clocks { 424 int dispclk_khz; 425 int actual_dispclk_khz; 426 int dppclk_khz; 427 int actual_dppclk_khz; 428 int disp_dpp_voltage_level_khz; 429 int dcfclk_khz; 430 int socclk_khz; 431 int dcfclk_deep_sleep_khz; 432 int fclk_khz; 433 int phyclk_khz; 434 int dramclk_khz; 435 bool p_state_change_support; 436 enum dcn_zstate_support_state zstate_support; 437 bool dtbclk_en; 438 int ref_dtbclk_khz; 439 bool fclk_p_state_change_support; 440 enum dcn_pwr_state pwr_state; 441 /* 442 * Elements below are not compared for the purposes of 443 * optimization required 444 */ 445 bool prev_p_state_change_support; 446 bool fclk_prev_p_state_change_support; 447 int num_ways; 448 bool fw_based_mclk_switching; 449 bool fw_based_mclk_switching_shut_down; 450 int prev_num_ways; 451 enum dtm_pstate dtm_level; 452 int max_supported_dppclk_khz; 453 int max_supported_dispclk_khz; 454 int bw_dppclk_khz; /*a copy of dppclk_khz*/ 455 int bw_dispclk_khz; 456 }; 457 458 struct dc_bw_validation_profile { 459 bool enable; 460 461 unsigned long long total_ticks; 462 unsigned long long voltage_level_ticks; 463 unsigned long long watermark_ticks; 464 unsigned long long rq_dlg_ticks; 465 466 unsigned long long total_count; 467 unsigned long long skip_fast_count; 468 unsigned long long skip_pass_count; 469 unsigned long long skip_fail_count; 470 }; 471 472 #define BW_VAL_TRACE_SETUP() \ 473 unsigned long long end_tick = 0; \ 474 unsigned long long voltage_level_tick = 0; \ 475 unsigned long long watermark_tick = 0; \ 476 unsigned long long start_tick = dc->debug.bw_val_profile.enable ? \ 477 dm_get_timestamp(dc->ctx) : 0 478 479 #define BW_VAL_TRACE_COUNT() \ 480 if (dc->debug.bw_val_profile.enable) \ 481 dc->debug.bw_val_profile.total_count++ 482 483 #define BW_VAL_TRACE_SKIP(status) \ 484 if (dc->debug.bw_val_profile.enable) { \ 485 if (!voltage_level_tick) \ 486 voltage_level_tick = dm_get_timestamp(dc->ctx); \ 487 dc->debug.bw_val_profile.skip_ ## status ## _count++; \ 488 } 489 490 #define BW_VAL_TRACE_END_VOLTAGE_LEVEL() \ 491 if (dc->debug.bw_val_profile.enable) \ 492 voltage_level_tick = dm_get_timestamp(dc->ctx) 493 494 #define BW_VAL_TRACE_END_WATERMARKS() \ 495 if (dc->debug.bw_val_profile.enable) \ 496 watermark_tick = dm_get_timestamp(dc->ctx) 497 498 #define BW_VAL_TRACE_FINISH() \ 499 if (dc->debug.bw_val_profile.enable) { \ 500 end_tick = dm_get_timestamp(dc->ctx); \ 501 dc->debug.bw_val_profile.total_ticks += end_tick - start_tick; \ 502 dc->debug.bw_val_profile.voltage_level_ticks += voltage_level_tick - start_tick; \ 503 if (watermark_tick) { \ 504 dc->debug.bw_val_profile.watermark_ticks += watermark_tick - voltage_level_tick; \ 505 dc->debug.bw_val_profile.rq_dlg_ticks += end_tick - watermark_tick; \ 506 } \ 507 } 508 509 union mem_low_power_enable_options { 510 struct { 511 bool vga: 1; 512 bool i2c: 1; 513 bool dmcu: 1; 514 bool dscl: 1; 515 bool cm: 1; 516 bool mpc: 1; 517 bool optc: 1; 518 bool vpg: 1; 519 bool afmt: 1; 520 } bits; 521 uint32_t u32All; 522 }; 523 524 union root_clock_optimization_options { 525 struct { 526 bool dpp: 1; 527 bool dsc: 1; 528 bool hdmistream: 1; 529 bool hdmichar: 1; 530 bool dpstream: 1; 531 bool symclk32_se: 1; 532 bool symclk32_le: 1; 533 bool symclk_fe: 1; 534 bool physymclk: 1; 535 bool dpiasymclk: 1; 536 uint32_t reserved: 22; 537 } bits; 538 uint32_t u32All; 539 }; 540 541 union dpia_debug_options { 542 struct { 543 uint32_t disable_dpia:1; /* bit 0 */ 544 uint32_t force_non_lttpr:1; /* bit 1 */ 545 uint32_t extend_aux_rd_interval:1; /* bit 2 */ 546 uint32_t disable_mst_dsc_work_around:1; /* bit 3 */ 547 uint32_t enable_force_tbt3_work_around:1; /* bit 4 */ 548 uint32_t reserved:27; 549 } bits; 550 uint32_t raw; 551 }; 552 553 /* AUX wake work around options 554 * 0: enable/disable work around 555 * 1: use default timeout LINK_AUX_WAKE_TIMEOUT_MS 556 * 15-2: reserved 557 * 31-16: timeout in ms 558 */ 559 union aux_wake_wa_options { 560 struct { 561 uint32_t enable_wa : 1; 562 uint32_t use_default_timeout : 1; 563 uint32_t rsvd: 14; 564 uint32_t timeout_ms : 16; 565 } bits; 566 uint32_t raw; 567 }; 568 569 struct dc_debug_data { 570 uint32_t ltFailCount; 571 uint32_t i2cErrorCount; 572 uint32_t auxErrorCount; 573 }; 574 575 struct dc_phy_addr_space_config { 576 struct { 577 uint64_t start_addr; 578 uint64_t end_addr; 579 uint64_t fb_top; 580 uint64_t fb_offset; 581 uint64_t fb_base; 582 uint64_t agp_top; 583 uint64_t agp_bot; 584 uint64_t agp_base; 585 } system_aperture; 586 587 struct { 588 uint64_t page_table_start_addr; 589 uint64_t page_table_end_addr; 590 uint64_t page_table_base_addr; 591 bool base_addr_is_mc_addr; 592 } gart_config; 593 594 bool valid; 595 bool is_hvm_enabled; 596 uint64_t page_table_default_page_addr; 597 }; 598 599 struct dc_virtual_addr_space_config { 600 uint64_t page_table_base_addr; 601 uint64_t page_table_start_addr; 602 uint64_t page_table_end_addr; 603 uint32_t page_table_block_size_in_bytes; 604 uint8_t page_table_depth; // 1 = 1 level, 2 = 2 level, etc. 0 = invalid 605 }; 606 607 struct dc_bounding_box_overrides { 608 int sr_exit_time_ns; 609 int sr_enter_plus_exit_time_ns; 610 int urgent_latency_ns; 611 int percent_of_ideal_drambw; 612 int dram_clock_change_latency_ns; 613 int dummy_clock_change_latency_ns; 614 int fclk_clock_change_latency_ns; 615 /* This forces a hard min on the DCFCLK we use 616 * for DML. Unlike the debug option for forcing 617 * DCFCLK, this override affects watermark calculations 618 */ 619 int min_dcfclk_mhz; 620 }; 621 622 struct dc_state; 623 struct resource_pool; 624 struct dce_hwseq; 625 626 struct dc_debug_options { 627 bool native422_support; 628 bool disable_dsc; 629 enum visual_confirm visual_confirm; 630 int visual_confirm_rect_height; 631 632 bool sanity_checks; 633 bool max_disp_clk; 634 bool surface_trace; 635 bool timing_trace; 636 bool clock_trace; 637 bool validation_trace; 638 bool bandwidth_calcs_trace; 639 int max_downscale_src_width; 640 641 /* stutter efficiency related */ 642 bool disable_stutter; 643 bool use_max_lb; 644 enum dcc_option disable_dcc; 645 enum pipe_split_policy pipe_split_policy; 646 bool force_single_disp_pipe_split; 647 bool voltage_align_fclk; 648 bool disable_min_fclk; 649 650 bool disable_dfs_bypass; 651 bool disable_dpp_power_gate; 652 bool disable_hubp_power_gate; 653 bool disable_dsc_power_gate; 654 int dsc_min_slice_height_override; 655 int dsc_bpp_increment_div; 656 bool disable_pplib_wm_range; 657 enum wm_report_mode pplib_wm_report_mode; 658 unsigned int min_disp_clk_khz; 659 unsigned int min_dpp_clk_khz; 660 unsigned int min_dram_clk_khz; 661 int sr_exit_time_dpm0_ns; 662 int sr_enter_plus_exit_time_dpm0_ns; 663 int sr_exit_time_ns; 664 int sr_enter_plus_exit_time_ns; 665 int urgent_latency_ns; 666 uint32_t underflow_assert_delay_us; 667 int percent_of_ideal_drambw; 668 int dram_clock_change_latency_ns; 669 bool optimized_watermark; 670 int always_scale; 671 bool disable_pplib_clock_request; 672 bool disable_clock_gate; 673 bool disable_mem_low_power; 674 bool pstate_enabled; 675 bool disable_dmcu; 676 bool disable_psr; 677 bool force_abm_enable; 678 bool disable_stereo_support; 679 bool vsr_support; 680 bool performance_trace; 681 bool az_endpoint_mute_only; 682 bool always_use_regamma; 683 bool recovery_enabled; 684 bool avoid_vbios_exec_table; 685 bool scl_reset_length10; 686 bool hdmi20_disable; 687 bool skip_detection_link_training; 688 uint32_t edid_read_retry_times; 689 unsigned int force_odm_combine; //bit vector based on otg inst 690 unsigned int seamless_boot_odm_combine; 691 unsigned int force_odm_combine_4to1; //bit vector based on otg inst 692 bool disable_z9_mpc; 693 unsigned int force_fclk_khz; 694 bool enable_tri_buf; 695 bool dmub_offload_enabled; 696 bool dmcub_emulation; 697 bool disable_idle_power_optimizations; 698 unsigned int mall_size_override; 699 unsigned int mall_additional_timer_percent; 700 bool mall_error_as_fatal; 701 bool dmub_command_table; /* for testing only */ 702 struct dc_bw_validation_profile bw_val_profile; 703 bool disable_fec; 704 bool disable_48mhz_pwrdwn; 705 /* This forces a hard min on the DCFCLK requested to SMU/PP 706 * watermarks are not affected. 707 */ 708 unsigned int force_min_dcfclk_mhz; 709 int dwb_fi_phase; 710 bool disable_timing_sync; 711 bool cm_in_bypass; 712 int force_clock_mode;/*every mode change.*/ 713 714 bool disable_dram_clock_change_vactive_support; 715 bool validate_dml_output; 716 bool enable_dmcub_surface_flip; 717 bool usbc_combo_phy_reset_wa; 718 bool disable_dsc_edp; 719 unsigned int force_dsc_edp_policy; 720 bool enable_dram_clock_change_one_display_vactive; 721 /* TODO - remove once tested */ 722 bool legacy_dp2_lt; 723 bool set_mst_en_for_sst; 724 bool disable_uhbr; 725 bool force_dp2_lt_fallback_method; 726 bool ignore_cable_id; 727 union mem_low_power_enable_options enable_mem_low_power; 728 union root_clock_optimization_options root_clock_optimization; 729 bool hpo_optimization; 730 bool force_vblank_alignment; 731 732 /* Enable dmub aux for legacy ddc */ 733 bool enable_dmub_aux_for_legacy_ddc; 734 bool disable_fams; 735 bool optimize_edp_link_rate; /* eDP ILR */ 736 /* FEC/PSR1 sequence enable delay in 100us */ 737 uint8_t fec_enable_delay_in100us; 738 bool enable_driver_sequence_debug; 739 enum det_size crb_alloc_policy; 740 int crb_alloc_policy_min_disp_count; 741 bool disable_z10; 742 bool enable_z9_disable_interface; 743 bool enable_sw_cntl_psr; 744 union dpia_debug_options dpia_debug; 745 bool disable_fixed_vs_aux_timeout_wa; 746 bool force_disable_subvp; 747 bool force_subvp_mclk_switch; 748 bool allow_sw_cursor_fallback; 749 bool force_usr_allow; 750 /* uses value at boot and disables switch */ 751 bool disable_dtb_ref_clk_switch; 752 uint32_t fixed_vs_aux_delay_config_wa; 753 bool extended_blank_optimization; 754 union aux_wake_wa_options aux_wake_wa; 755 uint32_t mst_start_top_delay; 756 uint8_t psr_power_use_phy_fsm; 757 enum dml_hostvm_override_opts dml_hostvm_override; 758 bool dml_disallow_alternate_prefetch_modes; 759 bool use_legacy_soc_bb_mechanism; 760 bool exit_idle_opt_for_cursor_updates; 761 bool enable_single_display_2to1_odm_policy; 762 bool enable_dp_dig_pixel_rate_div_policy; 763 }; 764 765 struct gpu_info_soc_bounding_box_v1_0; 766 struct dc { 767 struct dc_debug_options debug; 768 struct dc_versions versions; 769 struct dc_caps caps; 770 struct dc_cap_funcs cap_funcs; 771 struct dc_config config; 772 struct dc_bounding_box_overrides bb_overrides; 773 struct dc_bug_wa work_arounds; 774 struct dc_context *ctx; 775 struct dc_phy_addr_space_config vm_pa_config; 776 777 uint8_t link_count; 778 struct dc_link *links[MAX_PIPES * 2]; 779 780 struct dc_state *current_state; 781 struct resource_pool *res_pool; 782 783 struct clk_mgr *clk_mgr; 784 785 /* Display Engine Clock levels */ 786 struct dm_pp_clock_levels sclk_lvls; 787 788 /* Inputs into BW and WM calculations. */ 789 struct bw_calcs_dceip *bw_dceip; 790 struct bw_calcs_vbios *bw_vbios; 791 struct dcn_soc_bounding_box *dcn_soc; 792 struct dcn_ip_params *dcn_ip; 793 struct display_mode_lib dml; 794 795 /* HW functions */ 796 struct hw_sequencer_funcs hwss; 797 struct dce_hwseq *hwseq; 798 799 /* Require to optimize clocks and bandwidth for added/removed planes */ 800 bool optimized_required; 801 bool wm_optimized_required; 802 bool idle_optimizations_allowed; 803 bool enable_c20_dtm_b0; 804 805 /* Require to maintain clocks and bandwidth for UEFI enabled HW */ 806 807 /* FBC compressor */ 808 struct compressor *fbc_compressor; 809 810 struct dc_debug_data debug_data; 811 struct dpcd_vendor_signature vendor_signature; 812 813 const char *build_id; 814 struct vm_helper *vm_helper; 815 816 uint32_t *dcn_reg_offsets; 817 uint32_t *nbio_reg_offsets; 818 }; 819 820 enum frame_buffer_mode { 821 FRAME_BUFFER_MODE_LOCAL_ONLY = 0, 822 FRAME_BUFFER_MODE_ZFB_ONLY, 823 FRAME_BUFFER_MODE_MIXED_ZFB_AND_LOCAL, 824 } ; 825 826 struct dchub_init_data { 827 int64_t zfb_phys_addr_base; 828 int64_t zfb_mc_base_addr; 829 uint64_t zfb_size_in_byte; 830 enum frame_buffer_mode fb_mode; 831 bool dchub_initialzied; 832 bool dchub_info_valid; 833 }; 834 835 struct dc_init_data { 836 struct hw_asic_id asic_id; 837 void *driver; /* ctx */ 838 struct cgs_device *cgs_device; 839 struct dc_bounding_box_overrides bb_overrides; 840 841 int num_virtual_links; 842 /* 843 * If 'vbios_override' not NULL, it will be called instead 844 * of the real VBIOS. Intended use is Diagnostics on FPGA. 845 */ 846 struct dc_bios *vbios_override; 847 enum dce_environment dce_environment; 848 849 struct dmub_offload_funcs *dmub_if; 850 struct dc_reg_helper_state *dmub_offload; 851 852 struct dc_config flags; 853 uint64_t log_mask; 854 855 struct dpcd_vendor_signature vendor_signature; 856 bool force_smu_not_present; 857 /* 858 * IP offset for run time initializaion of register addresses 859 * 860 * DCN3.5+ will fail dc_create() if these fields are null for them. They are 861 * applicable starting with DCN32/321 and are not used for ASICs upstreamed 862 * before them. 863 */ 864 uint32_t *dcn_reg_offsets; 865 uint32_t *nbio_reg_offsets; 866 }; 867 868 struct dc_callback_init { 869 #ifdef CONFIG_DRM_AMD_DC_HDCP 870 struct cp_psp cp_psp; 871 #else 872 uint8_t reserved; 873 #endif 874 }; 875 876 struct dc *dc_create(const struct dc_init_data *init_params); 877 void dc_hardware_init(struct dc *dc); 878 879 int dc_get_vmid_use_vector(struct dc *dc); 880 void dc_setup_vm_context(struct dc *dc, struct dc_virtual_addr_space_config *va_config, int vmid); 881 /* Returns the number of vmids supported */ 882 int dc_setup_system_context(struct dc *dc, struct dc_phy_addr_space_config *pa_config); 883 void dc_init_callbacks(struct dc *dc, 884 const struct dc_callback_init *init_params); 885 void dc_deinit_callbacks(struct dc *dc); 886 void dc_destroy(struct dc **dc); 887 888 /******************************************************************************* 889 * Surface Interfaces 890 ******************************************************************************/ 891 892 enum { 893 TRANSFER_FUNC_POINTS = 1025 894 }; 895 896 struct dc_hdr_static_metadata { 897 /* display chromaticities and white point in units of 0.00001 */ 898 unsigned int chromaticity_green_x; 899 unsigned int chromaticity_green_y; 900 unsigned int chromaticity_blue_x; 901 unsigned int chromaticity_blue_y; 902 unsigned int chromaticity_red_x; 903 unsigned int chromaticity_red_y; 904 unsigned int chromaticity_white_point_x; 905 unsigned int chromaticity_white_point_y; 906 907 uint32_t min_luminance; 908 uint32_t max_luminance; 909 uint32_t maximum_content_light_level; 910 uint32_t maximum_frame_average_light_level; 911 }; 912 913 enum dc_transfer_func_type { 914 TF_TYPE_PREDEFINED, 915 TF_TYPE_DISTRIBUTED_POINTS, 916 TF_TYPE_BYPASS, 917 TF_TYPE_HWPWL 918 }; 919 920 struct dc_transfer_func_distributed_points { 921 struct fixed31_32 red[TRANSFER_FUNC_POINTS]; 922 struct fixed31_32 green[TRANSFER_FUNC_POINTS]; 923 struct fixed31_32 blue[TRANSFER_FUNC_POINTS]; 924 925 uint16_t end_exponent; 926 uint16_t x_point_at_y1_red; 927 uint16_t x_point_at_y1_green; 928 uint16_t x_point_at_y1_blue; 929 }; 930 931 enum dc_transfer_func_predefined { 932 TRANSFER_FUNCTION_SRGB, 933 TRANSFER_FUNCTION_BT709, 934 TRANSFER_FUNCTION_PQ, 935 TRANSFER_FUNCTION_LINEAR, 936 TRANSFER_FUNCTION_UNITY, 937 TRANSFER_FUNCTION_HLG, 938 TRANSFER_FUNCTION_HLG12, 939 TRANSFER_FUNCTION_GAMMA22, 940 TRANSFER_FUNCTION_GAMMA24, 941 TRANSFER_FUNCTION_GAMMA26 942 }; 943 944 945 struct dc_transfer_func { 946 struct kref refcount; 947 enum dc_transfer_func_type type; 948 enum dc_transfer_func_predefined tf; 949 /* FP16 1.0 reference level in nits, default is 80 nits, only for PQ*/ 950 uint32_t sdr_ref_white_level; 951 union { 952 struct pwl_params pwl; 953 struct dc_transfer_func_distributed_points tf_pts; 954 }; 955 }; 956 957 958 union dc_3dlut_state { 959 struct { 960 uint32_t initialized:1; /*if 3dlut is went through color module for initialization */ 961 uint32_t rmu_idx_valid:1; /*if mux settings are valid*/ 962 uint32_t rmu_mux_num:3; /*index of mux to use*/ 963 uint32_t mpc_rmu0_mux:4; /*select mpcc on mux, one of the following : mpcc0, mpcc1, mpcc2, mpcc3*/ 964 uint32_t mpc_rmu1_mux:4; 965 uint32_t mpc_rmu2_mux:4; 966 uint32_t reserved:15; 967 } bits; 968 uint32_t raw; 969 }; 970 971 972 struct dc_3dlut { 973 struct kref refcount; 974 struct tetrahedral_params lut_3d; 975 struct fixed31_32 hdr_multiplier; 976 union dc_3dlut_state state; 977 }; 978 /* 979 * This structure is filled in by dc_surface_get_status and contains 980 * the last requested address and the currently active address so the called 981 * can determine if there are any outstanding flips 982 */ 983 struct dc_plane_status { 984 struct dc_plane_address requested_address; 985 struct dc_plane_address current_address; 986 bool is_flip_pending; 987 bool is_right_eye; 988 }; 989 990 union surface_update_flags { 991 992 struct { 993 uint32_t addr_update:1; 994 /* Medium updates */ 995 uint32_t dcc_change:1; 996 uint32_t color_space_change:1; 997 uint32_t horizontal_mirror_change:1; 998 uint32_t per_pixel_alpha_change:1; 999 uint32_t global_alpha_change:1; 1000 uint32_t hdr_mult:1; 1001 uint32_t rotation_change:1; 1002 uint32_t swizzle_change:1; 1003 uint32_t scaling_change:1; 1004 uint32_t position_change:1; 1005 uint32_t in_transfer_func_change:1; 1006 uint32_t input_csc_change:1; 1007 uint32_t coeff_reduction_change:1; 1008 uint32_t output_tf_change:1; 1009 uint32_t pixel_format_change:1; 1010 uint32_t plane_size_change:1; 1011 uint32_t gamut_remap_change:1; 1012 1013 /* Full updates */ 1014 uint32_t new_plane:1; 1015 uint32_t bpp_change:1; 1016 uint32_t gamma_change:1; 1017 uint32_t bandwidth_change:1; 1018 uint32_t clock_change:1; 1019 uint32_t stereo_format_change:1; 1020 uint32_t lut_3d:1; 1021 uint32_t full_update:1; 1022 } bits; 1023 1024 uint32_t raw; 1025 }; 1026 1027 struct dc_plane_state { 1028 struct dc_plane_address address; 1029 struct dc_plane_flip_time time; 1030 bool triplebuffer_flips; 1031 struct scaling_taps scaling_quality; 1032 struct rect src_rect; 1033 struct rect dst_rect; 1034 struct rect clip_rect; 1035 1036 struct plane_size plane_size; 1037 union dc_tiling_info tiling_info; 1038 1039 struct dc_plane_dcc_param dcc; 1040 1041 struct dc_gamma *gamma_correction; 1042 struct dc_transfer_func *in_transfer_func; 1043 struct dc_bias_and_scale *bias_and_scale; 1044 struct dc_csc_transform input_csc_color_matrix; 1045 struct fixed31_32 coeff_reduction_factor; 1046 struct fixed31_32 hdr_mult; 1047 struct colorspace_transform gamut_remap_matrix; 1048 1049 // TODO: No longer used, remove 1050 struct dc_hdr_static_metadata hdr_static_ctx; 1051 1052 enum dc_color_space color_space; 1053 1054 struct dc_3dlut *lut3d_func; 1055 struct dc_transfer_func *in_shaper_func; 1056 struct dc_transfer_func *blend_tf; 1057 1058 struct dc_transfer_func *gamcor_tf; 1059 enum surface_pixel_format format; 1060 enum dc_rotation_angle rotation; 1061 enum plane_stereo_format stereo_format; 1062 1063 bool is_tiling_rotated; 1064 bool per_pixel_alpha; 1065 bool pre_multiplied_alpha; 1066 bool global_alpha; 1067 int global_alpha_value; 1068 bool visible; 1069 bool flip_immediate; 1070 bool horizontal_mirror; 1071 int layer_index; 1072 1073 union surface_update_flags update_flags; 1074 bool flip_int_enabled; 1075 bool skip_manual_trigger; 1076 1077 /* private to DC core */ 1078 struct dc_plane_status status; 1079 struct dc_context *ctx; 1080 1081 /* HACK: Workaround for forcing full reprogramming under some conditions */ 1082 bool force_full_update; 1083 1084 bool is_phantom; // TODO: Change mall_stream_config into mall_plane_config instead 1085 1086 /* private to dc_surface.c */ 1087 enum dc_irq_source irq_source; 1088 struct kref refcount; 1089 }; 1090 1091 struct dc_plane_info { 1092 struct plane_size plane_size; 1093 union dc_tiling_info tiling_info; 1094 struct dc_plane_dcc_param dcc; 1095 enum surface_pixel_format format; 1096 enum dc_rotation_angle rotation; 1097 enum plane_stereo_format stereo_format; 1098 enum dc_color_space color_space; 1099 bool horizontal_mirror; 1100 bool visible; 1101 bool per_pixel_alpha; 1102 bool pre_multiplied_alpha; 1103 bool global_alpha; 1104 int global_alpha_value; 1105 bool input_csc_enabled; 1106 int layer_index; 1107 }; 1108 1109 struct dc_scaling_info { 1110 struct rect src_rect; 1111 struct rect dst_rect; 1112 struct rect clip_rect; 1113 struct scaling_taps scaling_quality; 1114 }; 1115 1116 struct dc_surface_update { 1117 struct dc_plane_state *surface; 1118 1119 /* isr safe update parameters. null means no updates */ 1120 const struct dc_flip_addrs *flip_addr; 1121 const struct dc_plane_info *plane_info; 1122 const struct dc_scaling_info *scaling_info; 1123 struct fixed31_32 hdr_mult; 1124 /* following updates require alloc/sleep/spin that is not isr safe, 1125 * null means no updates 1126 */ 1127 const struct dc_gamma *gamma; 1128 const struct dc_transfer_func *in_transfer_func; 1129 1130 const struct dc_csc_transform *input_csc_color_matrix; 1131 const struct fixed31_32 *coeff_reduction_factor; 1132 const struct dc_transfer_func *func_shaper; 1133 const struct dc_3dlut *lut3d_func; 1134 const struct dc_transfer_func *blend_tf; 1135 const struct colorspace_transform *gamut_remap_matrix; 1136 }; 1137 1138 /* 1139 * Create a new surface with default parameters; 1140 */ 1141 struct dc_plane_state *dc_create_plane_state(struct dc *dc); 1142 const struct dc_plane_status *dc_plane_get_status( 1143 const struct dc_plane_state *plane_state); 1144 1145 void dc_plane_state_retain(struct dc_plane_state *plane_state); 1146 void dc_plane_state_release(struct dc_plane_state *plane_state); 1147 1148 void dc_gamma_retain(struct dc_gamma *dc_gamma); 1149 void dc_gamma_release(struct dc_gamma **dc_gamma); 1150 struct dc_gamma *dc_create_gamma(void); 1151 1152 void dc_transfer_func_retain(struct dc_transfer_func *dc_tf); 1153 void dc_transfer_func_release(struct dc_transfer_func *dc_tf); 1154 struct dc_transfer_func *dc_create_transfer_func(void); 1155 1156 struct dc_3dlut *dc_create_3dlut_func(void); 1157 void dc_3dlut_func_release(struct dc_3dlut *lut); 1158 void dc_3dlut_func_retain(struct dc_3dlut *lut); 1159 1160 void dc_post_update_surfaces_to_stream( 1161 struct dc *dc); 1162 1163 #include "dc_stream.h" 1164 1165 /* 1166 * Structure to store surface/stream associations for validation 1167 */ 1168 struct dc_validation_set { 1169 struct dc_stream_state *stream; 1170 struct dc_plane_state *plane_states[MAX_SURFACES]; 1171 uint8_t plane_count; 1172 }; 1173 1174 bool dc_validate_boot_timing(const struct dc *dc, 1175 const struct dc_sink *sink, 1176 struct dc_crtc_timing *crtc_timing); 1177 1178 enum dc_status dc_validate_plane(struct dc *dc, const struct dc_plane_state *plane_state); 1179 1180 void get_clock_requirements_for_state(struct dc_state *state, struct AsicStateEx *info); 1181 1182 bool dc_set_generic_gpio_for_stereo(bool enable, 1183 struct gpio_service *gpio_service); 1184 1185 /* 1186 * fast_validate: we return after determining if we can support the new state, 1187 * but before we populate the programming info 1188 */ 1189 enum dc_status dc_validate_global_state( 1190 struct dc *dc, 1191 struct dc_state *new_ctx, 1192 bool fast_validate); 1193 1194 1195 void dc_resource_state_construct( 1196 const struct dc *dc, 1197 struct dc_state *dst_ctx); 1198 1199 bool dc_acquire_release_mpc_3dlut( 1200 struct dc *dc, bool acquire, 1201 struct dc_stream_state *stream, 1202 struct dc_3dlut **lut, 1203 struct dc_transfer_func **shaper); 1204 1205 void dc_resource_state_copy_construct( 1206 const struct dc_state *src_ctx, 1207 struct dc_state *dst_ctx); 1208 1209 void dc_resource_state_copy_construct_current( 1210 const struct dc *dc, 1211 struct dc_state *dst_ctx); 1212 1213 void dc_resource_state_destruct(struct dc_state *context); 1214 1215 bool dc_resource_is_dsc_encoding_supported(const struct dc *dc); 1216 1217 /* 1218 * TODO update to make it about validation sets 1219 * Set up streams and links associated to drive sinks 1220 * The streams parameter is an absolute set of all active streams. 1221 * 1222 * After this call: 1223 * Phy, Encoder, Timing Generator are programmed and enabled. 1224 * New streams are enabled with blank stream; no memory read. 1225 */ 1226 bool dc_commit_state(struct dc *dc, struct dc_state *context); 1227 1228 struct dc_state *dc_create_state(struct dc *dc); 1229 struct dc_state *dc_copy_state(struct dc_state *src_ctx); 1230 void dc_retain_state(struct dc_state *context); 1231 void dc_release_state(struct dc_state *context); 1232 1233 /******************************************************************************* 1234 * Link Interfaces 1235 ******************************************************************************/ 1236 1237 struct dpcd_caps { 1238 union dpcd_rev dpcd_rev; 1239 union max_lane_count max_ln_count; 1240 union max_down_spread max_down_spread; 1241 union dprx_feature dprx_feature; 1242 1243 /* valid only for eDP v1.4 or higher*/ 1244 uint8_t edp_supported_link_rates_count; 1245 enum dc_link_rate edp_supported_link_rates[8]; 1246 1247 /* dongle type (DP converter, CV smart dongle) */ 1248 enum display_dongle_type dongle_type; 1249 bool is_dongle_type_one; 1250 /* branch device or sink device */ 1251 bool is_branch_dev; 1252 /* Dongle's downstream count. */ 1253 union sink_count sink_count; 1254 bool is_mst_capable; 1255 /* If dongle_type == DISPLAY_DONGLE_DP_HDMI_CONVERTER, 1256 indicates 'Frame Sequential-to-lllFrame Pack' conversion capability.*/ 1257 struct dc_dongle_caps dongle_caps; 1258 1259 uint32_t sink_dev_id; 1260 int8_t sink_dev_id_str[6]; 1261 int8_t sink_hw_revision; 1262 int8_t sink_fw_revision[2]; 1263 1264 uint32_t branch_dev_id; 1265 int8_t branch_dev_name[6]; 1266 int8_t branch_hw_revision; 1267 int8_t branch_fw_revision[2]; 1268 1269 bool allow_invalid_MSA_timing_param; 1270 bool panel_mode_edp; 1271 bool dpcd_display_control_capable; 1272 bool ext_receiver_cap_field_present; 1273 bool set_power_state_capable_edp; 1274 bool dynamic_backlight_capable_edp; 1275 union dpcd_fec_capability fec_cap; 1276 struct dpcd_dsc_capabilities dsc_caps; 1277 struct dc_lttpr_caps lttpr_caps; 1278 struct dpcd_usb4_dp_tunneling_info usb4_dp_tun_info; 1279 1280 union dp_128b_132b_supported_link_rates dp_128b_132b_supported_link_rates; 1281 union dp_main_line_channel_coding_cap channel_coding_cap; 1282 union dp_sink_video_fallback_formats fallback_formats; 1283 union dp_fec_capability1 fec_cap1; 1284 union dp_cable_id cable_id; 1285 uint8_t edp_rev; 1286 union edp_alpm_caps alpm_caps; 1287 struct edp_psr_info psr_info; 1288 }; 1289 1290 union dpcd_sink_ext_caps { 1291 struct { 1292 /* 0 - Sink supports backlight adjust via PWM during SDR/HDR mode 1293 * 1 - Sink supports backlight adjust via AUX during SDR/HDR mode. 1294 */ 1295 uint8_t sdr_aux_backlight_control : 1; 1296 uint8_t hdr_aux_backlight_control : 1; 1297 uint8_t reserved_1 : 2; 1298 uint8_t oled : 1; 1299 uint8_t reserved : 3; 1300 } bits; 1301 uint8_t raw; 1302 }; 1303 1304 #if defined(CONFIG_DRM_AMD_DC_HDCP) 1305 union hdcp_rx_caps { 1306 struct { 1307 uint8_t version; 1308 uint8_t reserved; 1309 struct { 1310 uint8_t repeater : 1; 1311 uint8_t hdcp_capable : 1; 1312 uint8_t reserved : 6; 1313 } byte0; 1314 } fields; 1315 uint8_t raw[3]; 1316 }; 1317 1318 union hdcp_bcaps { 1319 struct { 1320 uint8_t HDCP_CAPABLE:1; 1321 uint8_t REPEATER:1; 1322 uint8_t RESERVED:6; 1323 } bits; 1324 uint8_t raw; 1325 }; 1326 1327 struct hdcp_caps { 1328 union hdcp_rx_caps rx_caps; 1329 union hdcp_bcaps bcaps; 1330 }; 1331 #endif 1332 1333 #include "dc_link.h" 1334 1335 uint32_t dc_get_opp_for_plane(struct dc *dc, struct dc_plane_state *plane); 1336 1337 /******************************************************************************* 1338 * Sink Interfaces - A sink corresponds to a display output device 1339 ******************************************************************************/ 1340 1341 struct dc_container_id { 1342 // 128bit GUID in binary form 1343 unsigned char guid[16]; 1344 // 8 byte port ID -> ELD.PortID 1345 unsigned int portId[2]; 1346 // 128bit GUID in binary formufacturer name -> ELD.ManufacturerName 1347 unsigned short manufacturerName; 1348 // 2 byte product code -> ELD.ProductCode 1349 unsigned short productCode; 1350 }; 1351 1352 1353 struct dc_sink_dsc_caps { 1354 // 'true' if these are virtual DPCD's DSC caps (immediately upstream of sink in MST topology), 1355 // 'false' if they are sink's DSC caps 1356 bool is_virtual_dpcd_dsc; 1357 #if defined(CONFIG_DRM_AMD_DC_DCN) 1358 // 'true' if MST topology supports DSC passthrough for sink 1359 // 'false' if MST topology does not support DSC passthrough 1360 bool is_dsc_passthrough_supported; 1361 #endif 1362 struct dsc_dec_dpcd_caps dsc_dec_caps; 1363 }; 1364 1365 struct dc_sink_fec_caps { 1366 bool is_rx_fec_supported; 1367 bool is_topology_fec_supported; 1368 }; 1369 1370 /* 1371 * The sink structure contains EDID and other display device properties 1372 */ 1373 struct dc_sink { 1374 enum signal_type sink_signal; 1375 struct dc_edid dc_edid; /* raw edid */ 1376 struct dc_edid_caps edid_caps; /* parse display caps */ 1377 struct dc_container_id *dc_container_id; 1378 uint32_t dongle_max_pix_clk; 1379 void *priv; 1380 struct stereo_3d_features features_3d[TIMING_3D_FORMAT_MAX]; 1381 bool converter_disable_audio; 1382 1383 struct dc_sink_dsc_caps dsc_caps; 1384 struct dc_sink_fec_caps fec_caps; 1385 1386 bool is_vsc_sdp_colorimetry_supported; 1387 1388 /* private to DC core */ 1389 struct dc_link *link; 1390 struct dc_context *ctx; 1391 1392 uint32_t sink_id; 1393 1394 /* private to dc_sink.c */ 1395 // refcount must be the last member in dc_sink, since we want the 1396 // sink structure to be logically cloneable up to (but not including) 1397 // refcount 1398 struct kref refcount; 1399 }; 1400 1401 void dc_sink_retain(struct dc_sink *sink); 1402 void dc_sink_release(struct dc_sink *sink); 1403 1404 struct dc_sink_init_data { 1405 enum signal_type sink_signal; 1406 struct dc_link *link; 1407 uint32_t dongle_max_pix_clk; 1408 bool converter_disable_audio; 1409 }; 1410 1411 bool dc_extended_blank_supported(struct dc *dc); 1412 1413 struct dc_sink *dc_sink_create(const struct dc_sink_init_data *init_params); 1414 1415 /* Newer interfaces */ 1416 struct dc_cursor { 1417 struct dc_plane_address address; 1418 struct dc_cursor_attributes attributes; 1419 }; 1420 1421 1422 /******************************************************************************* 1423 * Interrupt interfaces 1424 ******************************************************************************/ 1425 enum dc_irq_source dc_interrupt_to_irq_source( 1426 struct dc *dc, 1427 uint32_t src_id, 1428 uint32_t ext_id); 1429 bool dc_interrupt_set(struct dc *dc, enum dc_irq_source src, bool enable); 1430 void dc_interrupt_ack(struct dc *dc, enum dc_irq_source src); 1431 enum dc_irq_source dc_get_hpd_irq_source_at_index( 1432 struct dc *dc, uint32_t link_index); 1433 1434 void dc_notify_vsync_int_state(struct dc *dc, struct dc_stream_state *stream, bool enable); 1435 1436 /******************************************************************************* 1437 * Power Interfaces 1438 ******************************************************************************/ 1439 1440 void dc_set_power_state( 1441 struct dc *dc, 1442 enum dc_acpi_cm_power_state power_state); 1443 void dc_resume(struct dc *dc); 1444 1445 void dc_power_down_on_boot(struct dc *dc); 1446 1447 #if defined(CONFIG_DRM_AMD_DC_HDCP) 1448 /* 1449 * HDCP Interfaces 1450 */ 1451 enum hdcp_message_status dc_process_hdcp_msg( 1452 enum signal_type signal, 1453 struct dc_link *link, 1454 struct hdcp_protection_message *message_info); 1455 #endif 1456 bool dc_is_dmcu_initialized(struct dc *dc); 1457 1458 enum dc_status dc_set_clock(struct dc *dc, enum dc_clock_type clock_type, uint32_t clk_khz, uint32_t stepping); 1459 void dc_get_clock(struct dc *dc, enum dc_clock_type clock_type, struct dc_clock_config *clock_cfg); 1460 1461 bool dc_is_plane_eligible_for_idle_optimizations(struct dc *dc, struct dc_plane_state *plane, 1462 struct dc_cursor_attributes *cursor_attr); 1463 1464 void dc_allow_idle_optimizations(struct dc *dc, bool allow); 1465 1466 /* set min and max memory clock to lowest and highest DPM level, respectively */ 1467 void dc_unlock_memory_clock_frequency(struct dc *dc); 1468 1469 /* set min memory clock to the min required for current mode, max to maxDPM */ 1470 void dc_lock_memory_clock_frequency(struct dc *dc); 1471 1472 /* set soft max for memclk, to be used for AC/DC switching clock limitations */ 1473 void dc_enable_dcmode_clk_limit(struct dc *dc, bool enable); 1474 1475 /* cleanup on driver unload */ 1476 void dc_hardware_release(struct dc *dc); 1477 1478 /* disables fw based mclk switch */ 1479 void dc_mclk_switch_using_fw_based_vblank_stretch_shut_down(struct dc *dc); 1480 1481 bool dc_set_psr_allow_active(struct dc *dc, bool enable); 1482 void dc_z10_restore(const struct dc *dc); 1483 void dc_z10_save_init(struct dc *dc); 1484 1485 bool dc_is_dmub_outbox_supported(struct dc *dc); 1486 bool dc_enable_dmub_notifications(struct dc *dc); 1487 1488 void dc_enable_dmub_outbox(struct dc *dc); 1489 1490 bool dc_process_dmub_aux_transfer_async(struct dc *dc, 1491 uint32_t link_index, 1492 struct aux_payload *payload); 1493 1494 /* Get dc link index from dpia port index */ 1495 uint8_t get_link_index_from_dpia_port_index(const struct dc *dc, 1496 uint8_t dpia_port_index); 1497 1498 bool dc_process_dmub_set_config_async(struct dc *dc, 1499 uint32_t link_index, 1500 struct set_config_cmd_payload *payload, 1501 struct dmub_notification *notify); 1502 1503 enum dc_status dc_process_dmub_set_mst_slots(const struct dc *dc, 1504 uint32_t link_index, 1505 uint8_t mst_alloc_slots, 1506 uint8_t *mst_slots_in_use); 1507 1508 /******************************************************************************* 1509 * DSC Interfaces 1510 ******************************************************************************/ 1511 #include "dc_dsc.h" 1512 1513 /******************************************************************************* 1514 * Disable acc mode Interfaces 1515 ******************************************************************************/ 1516 void dc_disable_accelerated_mode(struct dc *dc); 1517 1518 #endif /* DC_INTERFACE_H_ */ 1519