1 /* 2 * Copyright 2012-14 Advanced Micro Devices, Inc. 3 * 4 * Permission is hereby granted, free of charge, to any person obtaining a 5 * copy of this software and associated documentation files (the "Software"), 6 * to deal in the Software without restriction, including without limitation 7 * the rights to use, copy, modify, merge, publish, distribute, sublicense, 8 * and/or sell copies of the Software, and to permit persons to whom the 9 * Software is furnished to do so, subject to the following conditions: 10 * 11 * The above copyright notice and this permission notice shall be included in 12 * all copies or substantial portions of the Software. 13 * 14 * THE SOFTWARE IS PROVIDED "AS IS", WITHOUT WARRANTY OF ANY KIND, EXPRESS OR 15 * IMPLIED, INCLUDING BUT NOT LIMITED TO THE WARRANTIES OF MERCHANTABILITY, 16 * FITNESS FOR A PARTICULAR PURPOSE AND NONINFRINGEMENT. IN NO EVENT SHALL 17 * THE COPYRIGHT HOLDER(S) OR AUTHOR(S) BE LIABLE FOR ANY CLAIM, DAMAGES OR 18 * OTHER LIABILITY, WHETHER IN AN ACTION OF CONTRACT, TORT OR OTHERWISE, 19 * ARISING FROM, OUT OF OR IN CONNECTION WITH THE SOFTWARE OR THE USE OR 20 * OTHER DEALINGS IN THE SOFTWARE. 21 * 22 * Authors: AMD 23 * 24 */ 25 26 #ifndef DC_INTERFACE_H_ 27 #define DC_INTERFACE_H_ 28 29 #include "dc_types.h" 30 #include "grph_object_defs.h" 31 #include "logger_types.h" 32 #if defined(CONFIG_DRM_AMD_DC_HDCP) 33 #include "hdcp_types.h" 34 #endif 35 #include "gpio_types.h" 36 #include "link_service_types.h" 37 #include "grph_object_ctrl_defs.h" 38 #include <inc/hw/opp.h> 39 40 #include "inc/hw_sequencer.h" 41 #include "inc/compressor.h" 42 #include "inc/hw/dmcu.h" 43 #include "dml/display_mode_lib.h" 44 45 /* forward declaration */ 46 struct aux_payload; 47 48 #define DC_VER "3.2.135.1" 49 50 #define MAX_SURFACES 3 51 #define MAX_PLANES 6 52 #define MAX_STREAMS 6 53 #define MAX_SINKS_PER_LINK 4 54 #define MIN_VIEWPORT_SIZE 12 55 #define MAX_NUM_EDP 2 56 57 /******************************************************************************* 58 * Display Core Interfaces 59 ******************************************************************************/ 60 struct dc_versions { 61 const char *dc_ver; 62 struct dmcu_version dmcu_version; 63 }; 64 65 enum dp_protocol_version { 66 DP_VERSION_1_4, 67 }; 68 69 enum dc_plane_type { 70 DC_PLANE_TYPE_INVALID, 71 DC_PLANE_TYPE_DCE_RGB, 72 DC_PLANE_TYPE_DCE_UNDERLAY, 73 DC_PLANE_TYPE_DCN_UNIVERSAL, 74 }; 75 76 struct dc_plane_cap { 77 enum dc_plane_type type; 78 uint32_t blends_with_above : 1; 79 uint32_t blends_with_below : 1; 80 uint32_t per_pixel_alpha : 1; 81 struct { 82 uint32_t argb8888 : 1; 83 uint32_t nv12 : 1; 84 uint32_t fp16 : 1; 85 uint32_t p010 : 1; 86 uint32_t ayuv : 1; 87 } pixel_format_support; 88 // max upscaling factor x1000 89 // upscaling factors are always >= 1 90 // for example, 1080p -> 8K is 4.0, or 4000 raw value 91 struct { 92 uint32_t argb8888; 93 uint32_t nv12; 94 uint32_t fp16; 95 } max_upscale_factor; 96 // max downscale factor x1000 97 // downscale factors are always <= 1 98 // for example, 8K -> 1080p is 0.25, or 250 raw value 99 struct { 100 uint32_t argb8888; 101 uint32_t nv12; 102 uint32_t fp16; 103 } max_downscale_factor; 104 // minimal width/height 105 uint32_t min_width; 106 uint32_t min_height; 107 }; 108 109 // Color management caps (DPP and MPC) 110 struct rom_curve_caps { 111 uint16_t srgb : 1; 112 uint16_t bt2020 : 1; 113 uint16_t gamma2_2 : 1; 114 uint16_t pq : 1; 115 uint16_t hlg : 1; 116 }; 117 118 struct dpp_color_caps { 119 uint16_t dcn_arch : 1; // all DCE generations treated the same 120 // input lut is different than most LUTs, just plain 256-entry lookup 121 uint16_t input_lut_shared : 1; // shared with DGAM 122 uint16_t icsc : 1; 123 uint16_t dgam_ram : 1; 124 uint16_t post_csc : 1; // before gamut remap 125 uint16_t gamma_corr : 1; 126 127 // hdr_mult and gamut remap always available in DPP (in that order) 128 // 3d lut implies shaper LUT, 129 // it may be shared with MPC - check MPC:shared_3d_lut flag 130 uint16_t hw_3d_lut : 1; 131 uint16_t ogam_ram : 1; // blnd gam 132 uint16_t ocsc : 1; 133 uint16_t dgam_rom_for_yuv : 1; 134 struct rom_curve_caps dgam_rom_caps; 135 struct rom_curve_caps ogam_rom_caps; 136 }; 137 138 struct mpc_color_caps { 139 uint16_t gamut_remap : 1; 140 uint16_t ogam_ram : 1; 141 uint16_t ocsc : 1; 142 uint16_t num_3dluts : 3; //3d lut always assumes a preceding shaper LUT 143 uint16_t shared_3d_lut:1; //can be in either DPP or MPC, but single instance 144 145 struct rom_curve_caps ogam_rom_caps; 146 }; 147 148 struct dc_color_caps { 149 struct dpp_color_caps dpp; 150 struct mpc_color_caps mpc; 151 }; 152 153 struct dc_caps { 154 uint32_t max_streams; 155 uint32_t max_links; 156 uint32_t max_audios; 157 uint32_t max_slave_planes; 158 uint32_t max_slave_yuv_planes; 159 uint32_t max_slave_rgb_planes; 160 uint32_t max_planes; 161 uint32_t max_downscale_ratio; 162 uint32_t i2c_speed_in_khz; 163 uint32_t i2c_speed_in_khz_hdcp; 164 uint32_t dmdata_alloc_size; 165 unsigned int max_cursor_size; 166 unsigned int max_video_width; 167 unsigned int min_horizontal_blanking_period; 168 int linear_pitch_alignment; 169 bool dcc_const_color; 170 bool dynamic_audio; 171 bool is_apu; 172 bool dual_link_dvi; 173 bool post_blend_color_processing; 174 bool force_dp_tps4_for_cp2520; 175 bool disable_dp_clk_share; 176 bool psp_setup_panel_mode; 177 bool extended_aux_timeout_support; 178 bool dmcub_support; 179 uint32_t num_of_internal_disp; 180 enum dp_protocol_version max_dp_protocol_version; 181 unsigned int mall_size_per_mem_channel; 182 unsigned int mall_size_total; 183 unsigned int cursor_cache_size; 184 struct dc_plane_cap planes[MAX_PLANES]; 185 struct dc_color_caps color; 186 }; 187 188 struct dc_bug_wa { 189 bool no_connect_phy_config; 190 bool dedcn20_305_wa; 191 bool skip_clock_update; 192 bool lt_early_cr_pattern; 193 }; 194 195 struct dc_dcc_surface_param { 196 struct dc_size surface_size; 197 enum surface_pixel_format format; 198 enum swizzle_mode_values swizzle_mode; 199 enum dc_scan_direction scan; 200 }; 201 202 struct dc_dcc_setting { 203 unsigned int max_compressed_blk_size; 204 unsigned int max_uncompressed_blk_size; 205 bool independent_64b_blks; 206 #if defined(CONFIG_DRM_AMD_DC_DCN) 207 //These bitfields to be used starting with DCN 3.0 208 struct { 209 uint32_t dcc_256_64_64 : 1;//available in ASICs before DCN 3.0 (the worst compression case) 210 uint32_t dcc_128_128_uncontrained : 1; //available in ASICs before DCN 3.0 211 uint32_t dcc_256_128_128 : 1; //available starting with DCN 3.0 212 uint32_t dcc_256_256_unconstrained : 1; //available in ASICs before DCN 3.0 (the best compression case) 213 } dcc_controls; 214 #endif 215 }; 216 217 struct dc_surface_dcc_cap { 218 union { 219 struct { 220 struct dc_dcc_setting rgb; 221 } grph; 222 223 struct { 224 struct dc_dcc_setting luma; 225 struct dc_dcc_setting chroma; 226 } video; 227 }; 228 229 bool capable; 230 bool const_color_support; 231 }; 232 233 struct dc_static_screen_params { 234 struct { 235 bool force_trigger; 236 bool cursor_update; 237 bool surface_update; 238 bool overlay_update; 239 } triggers; 240 unsigned int num_frames; 241 }; 242 243 244 /* Surface update type is used by dc_update_surfaces_and_stream 245 * The update type is determined at the very beginning of the function based 246 * on parameters passed in and decides how much programming (or updating) is 247 * going to be done during the call. 248 * 249 * UPDATE_TYPE_FAST is used for really fast updates that do not require much 250 * logical calculations or hardware register programming. This update MUST be 251 * ISR safe on windows. Currently fast update will only be used to flip surface 252 * address. 253 * 254 * UPDATE_TYPE_MED is used for slower updates which require significant hw 255 * re-programming however do not affect bandwidth consumption or clock 256 * requirements. At present, this is the level at which front end updates 257 * that do not require us to run bw_calcs happen. These are in/out transfer func 258 * updates, viewport offset changes, recout size changes and pixel depth changes. 259 * This update can be done at ISR, but we want to minimize how often this happens. 260 * 261 * UPDATE_TYPE_FULL is slow. Really slow. This requires us to recalculate our 262 * bandwidth and clocks, possibly rearrange some pipes and reprogram anything front 263 * end related. Any time viewport dimensions, recout dimensions, scaling ratios or 264 * gamma need to be adjusted or pipe needs to be turned on (or disconnected) we do 265 * a full update. This cannot be done at ISR level and should be a rare event. 266 * Unless someone is stress testing mpo enter/exit, playing with colour or adjusting 267 * underscan we don't expect to see this call at all. 268 */ 269 270 enum surface_update_type { 271 UPDATE_TYPE_FAST, /* super fast, safe to execute in isr */ 272 UPDATE_TYPE_MED, /* ISR safe, most of programming needed, no bw/clk change*/ 273 UPDATE_TYPE_FULL, /* may need to shuffle resources */ 274 }; 275 276 /* Forward declaration*/ 277 struct dc; 278 struct dc_plane_state; 279 struct dc_state; 280 281 282 struct dc_cap_funcs { 283 bool (*get_dcc_compression_cap)(const struct dc *dc, 284 const struct dc_dcc_surface_param *input, 285 struct dc_surface_dcc_cap *output); 286 }; 287 288 struct link_training_settings; 289 290 291 /* Structure to hold configuration flags set by dm at dc creation. */ 292 struct dc_config { 293 bool gpu_vm_support; 294 bool disable_disp_pll_sharing; 295 bool fbc_support; 296 bool disable_fractional_pwm; 297 bool allow_seamless_boot_optimization; 298 bool power_down_display_on_boot; 299 bool edp_not_connected; 300 bool force_enum_edp; 301 bool forced_clocks; 302 bool allow_lttpr_non_transparent_mode; 303 bool multi_mon_pp_mclk_switch; 304 bool disable_dmcu; 305 bool enable_4to1MPC; 306 #if defined(CONFIG_DRM_AMD_DC_DCN) 307 bool clamp_min_dcfclk; 308 #endif 309 uint64_t vblank_alignment_dto_params; 310 uint8_t vblank_alignment_max_frame_time_diff; 311 bool is_asymmetric_memory; 312 bool is_single_rank_dimm; 313 }; 314 315 enum visual_confirm { 316 VISUAL_CONFIRM_DISABLE = 0, 317 VISUAL_CONFIRM_SURFACE = 1, 318 VISUAL_CONFIRM_HDR = 2, 319 VISUAL_CONFIRM_MPCTREE = 4, 320 VISUAL_CONFIRM_PSR = 5, 321 }; 322 323 enum dcc_option { 324 DCC_ENABLE = 0, 325 DCC_DISABLE = 1, 326 DCC_HALF_REQ_DISALBE = 2, 327 }; 328 329 enum pipe_split_policy { 330 MPC_SPLIT_DYNAMIC = 0, 331 MPC_SPLIT_AVOID = 1, 332 MPC_SPLIT_AVOID_MULT_DISP = 2, 333 }; 334 335 enum wm_report_mode { 336 WM_REPORT_DEFAULT = 0, 337 WM_REPORT_OVERRIDE = 1, 338 }; 339 enum dtm_pstate{ 340 dtm_level_p0 = 0,/*highest voltage*/ 341 dtm_level_p1, 342 dtm_level_p2, 343 dtm_level_p3, 344 dtm_level_p4,/*when active_display_count = 0*/ 345 }; 346 347 enum dcn_pwr_state { 348 DCN_PWR_STATE_UNKNOWN = -1, 349 DCN_PWR_STATE_MISSION_MODE = 0, 350 DCN_PWR_STATE_LOW_POWER = 3, 351 }; 352 353 /* 354 * For any clocks that may differ per pipe 355 * only the max is stored in this structure 356 */ 357 struct dc_clocks { 358 int dispclk_khz; 359 int actual_dispclk_khz; 360 int dppclk_khz; 361 int actual_dppclk_khz; 362 int disp_dpp_voltage_level_khz; 363 int dcfclk_khz; 364 int socclk_khz; 365 int dcfclk_deep_sleep_khz; 366 int fclk_khz; 367 int phyclk_khz; 368 int dramclk_khz; 369 bool p_state_change_support; 370 enum dcn_pwr_state pwr_state; 371 /* 372 * Elements below are not compared for the purposes of 373 * optimization required 374 */ 375 bool prev_p_state_change_support; 376 enum dtm_pstate dtm_level; 377 int max_supported_dppclk_khz; 378 int max_supported_dispclk_khz; 379 int bw_dppclk_khz; /*a copy of dppclk_khz*/ 380 int bw_dispclk_khz; 381 }; 382 383 struct dc_bw_validation_profile { 384 bool enable; 385 386 unsigned long long total_ticks; 387 unsigned long long voltage_level_ticks; 388 unsigned long long watermark_ticks; 389 unsigned long long rq_dlg_ticks; 390 391 unsigned long long total_count; 392 unsigned long long skip_fast_count; 393 unsigned long long skip_pass_count; 394 unsigned long long skip_fail_count; 395 }; 396 397 #define BW_VAL_TRACE_SETUP() \ 398 unsigned long long end_tick = 0; \ 399 unsigned long long voltage_level_tick = 0; \ 400 unsigned long long watermark_tick = 0; \ 401 unsigned long long start_tick = dc->debug.bw_val_profile.enable ? \ 402 dm_get_timestamp(dc->ctx) : 0 403 404 #define BW_VAL_TRACE_COUNT() \ 405 if (dc->debug.bw_val_profile.enable) \ 406 dc->debug.bw_val_profile.total_count++ 407 408 #define BW_VAL_TRACE_SKIP(status) \ 409 if (dc->debug.bw_val_profile.enable) { \ 410 if (!voltage_level_tick) \ 411 voltage_level_tick = dm_get_timestamp(dc->ctx); \ 412 dc->debug.bw_val_profile.skip_ ## status ## _count++; \ 413 } 414 415 #define BW_VAL_TRACE_END_VOLTAGE_LEVEL() \ 416 if (dc->debug.bw_val_profile.enable) \ 417 voltage_level_tick = dm_get_timestamp(dc->ctx) 418 419 #define BW_VAL_TRACE_END_WATERMARKS() \ 420 if (dc->debug.bw_val_profile.enable) \ 421 watermark_tick = dm_get_timestamp(dc->ctx) 422 423 #define BW_VAL_TRACE_FINISH() \ 424 if (dc->debug.bw_val_profile.enable) { \ 425 end_tick = dm_get_timestamp(dc->ctx); \ 426 dc->debug.bw_val_profile.total_ticks += end_tick - start_tick; \ 427 dc->debug.bw_val_profile.voltage_level_ticks += voltage_level_tick - start_tick; \ 428 if (watermark_tick) { \ 429 dc->debug.bw_val_profile.watermark_ticks += watermark_tick - voltage_level_tick; \ 430 dc->debug.bw_val_profile.rq_dlg_ticks += end_tick - watermark_tick; \ 431 } \ 432 } 433 434 union mem_low_power_enable_options { 435 struct { 436 bool i2c: 1; 437 bool dmcu: 1; 438 bool dscl: 1; 439 bool cm: 1; 440 bool mpc: 1; 441 bool optc: 1; 442 } bits; 443 uint32_t u32All; 444 }; 445 446 struct dc_debug_options { 447 enum visual_confirm visual_confirm; 448 bool sanity_checks; 449 bool max_disp_clk; 450 bool surface_trace; 451 bool timing_trace; 452 bool clock_trace; 453 bool validation_trace; 454 bool bandwidth_calcs_trace; 455 int max_downscale_src_width; 456 457 /* stutter efficiency related */ 458 bool disable_stutter; 459 bool use_max_lb; 460 enum dcc_option disable_dcc; 461 enum pipe_split_policy pipe_split_policy; 462 bool force_single_disp_pipe_split; 463 bool voltage_align_fclk; 464 bool disable_min_fclk; 465 466 bool disable_dfs_bypass; 467 bool disable_dpp_power_gate; 468 bool disable_hubp_power_gate; 469 bool disable_dsc_power_gate; 470 int dsc_min_slice_height_override; 471 int dsc_bpp_increment_div; 472 bool native422_support; 473 bool disable_pplib_wm_range; 474 enum wm_report_mode pplib_wm_report_mode; 475 unsigned int min_disp_clk_khz; 476 unsigned int min_dpp_clk_khz; 477 int sr_exit_time_dpm0_ns; 478 int sr_enter_plus_exit_time_dpm0_ns; 479 int sr_exit_time_ns; 480 int sr_enter_plus_exit_time_ns; 481 int urgent_latency_ns; 482 uint32_t underflow_assert_delay_us; 483 int percent_of_ideal_drambw; 484 int dram_clock_change_latency_ns; 485 bool optimized_watermark; 486 int always_scale; 487 bool disable_pplib_clock_request; 488 bool disable_clock_gate; 489 bool disable_mem_low_power; 490 bool disable_dmcu; 491 bool disable_psr; 492 bool force_abm_enable; 493 bool disable_stereo_support; 494 bool vsr_support; 495 bool performance_trace; 496 bool az_endpoint_mute_only; 497 bool always_use_regamma; 498 bool recovery_enabled; 499 bool avoid_vbios_exec_table; 500 bool scl_reset_length10; 501 bool hdmi20_disable; 502 bool skip_detection_link_training; 503 uint32_t edid_read_retry_times; 504 bool remove_disconnect_edp; 505 unsigned int force_odm_combine; //bit vector based on otg inst 506 #if defined(CONFIG_DRM_AMD_DC_DCN) 507 unsigned int force_odm_combine_4to1; //bit vector based on otg inst 508 #endif 509 unsigned int force_fclk_khz; 510 bool enable_tri_buf; 511 bool dmub_offload_enabled; 512 bool dmcub_emulation; 513 #if defined(CONFIG_DRM_AMD_DC_DCN) 514 bool disable_idle_power_optimizations; 515 unsigned int mall_size_override; 516 unsigned int mall_additional_timer_percent; 517 bool mall_error_as_fatal; 518 #endif 519 bool dmub_command_table; /* for testing only */ 520 struct dc_bw_validation_profile bw_val_profile; 521 bool disable_fec; 522 bool disable_48mhz_pwrdwn; 523 /* This forces a hard min on the DCFCLK requested to SMU/PP 524 * watermarks are not affected. 525 */ 526 unsigned int force_min_dcfclk_mhz; 527 #if defined(CONFIG_DRM_AMD_DC_DCN) 528 int dwb_fi_phase; 529 #endif 530 bool disable_timing_sync; 531 bool cm_in_bypass; 532 int force_clock_mode;/*every mode change.*/ 533 534 bool disable_dram_clock_change_vactive_support; 535 bool validate_dml_output; 536 bool enable_dmcub_surface_flip; 537 bool usbc_combo_phy_reset_wa; 538 bool disable_dsc; 539 bool enable_dram_clock_change_one_display_vactive; 540 union mem_low_power_enable_options enable_mem_low_power; 541 bool force_vblank_alignment; 542 543 /* Enable dmub aux for legacy ddc */ 544 bool enable_dmub_aux_for_legacy_ddc; 545 bool optimize_edp_link_rate; /* eDP ILR */ 546 /* force enable edp FEC */ 547 bool force_enable_edp_fec; 548 /* FEC/PSR1 sequence enable delay in 100us */ 549 uint8_t fec_enable_delay_in100us; 550 }; 551 552 struct dc_debug_data { 553 uint32_t ltFailCount; 554 uint32_t i2cErrorCount; 555 uint32_t auxErrorCount; 556 }; 557 558 struct dc_phy_addr_space_config { 559 struct { 560 uint64_t start_addr; 561 uint64_t end_addr; 562 uint64_t fb_top; 563 uint64_t fb_offset; 564 uint64_t fb_base; 565 uint64_t agp_top; 566 uint64_t agp_bot; 567 uint64_t agp_base; 568 } system_aperture; 569 570 struct { 571 uint64_t page_table_start_addr; 572 uint64_t page_table_end_addr; 573 uint64_t page_table_base_addr; 574 } gart_config; 575 576 bool valid; 577 bool is_hvm_enabled; 578 uint64_t page_table_default_page_addr; 579 }; 580 581 struct dc_virtual_addr_space_config { 582 uint64_t page_table_base_addr; 583 uint64_t page_table_start_addr; 584 uint64_t page_table_end_addr; 585 uint32_t page_table_block_size_in_bytes; 586 uint8_t page_table_depth; // 1 = 1 level, 2 = 2 level, etc. 0 = invalid 587 }; 588 589 struct dc_bounding_box_overrides { 590 int sr_exit_time_ns; 591 int sr_enter_plus_exit_time_ns; 592 int urgent_latency_ns; 593 int percent_of_ideal_drambw; 594 int dram_clock_change_latency_ns; 595 int dummy_clock_change_latency_ns; 596 /* This forces a hard min on the DCFCLK we use 597 * for DML. Unlike the debug option for forcing 598 * DCFCLK, this override affects watermark calculations 599 */ 600 int min_dcfclk_mhz; 601 }; 602 603 struct resource_pool; 604 struct dce_hwseq; 605 struct gpu_info_soc_bounding_box_v1_0; 606 struct dc { 607 struct dc_versions versions; 608 struct dc_caps caps; 609 struct dc_cap_funcs cap_funcs; 610 struct dc_config config; 611 struct dc_debug_options debug; 612 struct dc_bounding_box_overrides bb_overrides; 613 struct dc_bug_wa work_arounds; 614 struct dc_context *ctx; 615 struct dc_phy_addr_space_config vm_pa_config; 616 617 uint8_t link_count; 618 struct dc_link *links[MAX_PIPES * 2]; 619 620 struct dc_state *current_state; 621 struct resource_pool *res_pool; 622 623 struct clk_mgr *clk_mgr; 624 625 /* Display Engine Clock levels */ 626 struct dm_pp_clock_levels sclk_lvls; 627 628 /* Inputs into BW and WM calculations. */ 629 struct bw_calcs_dceip *bw_dceip; 630 struct bw_calcs_vbios *bw_vbios; 631 #ifdef CONFIG_DRM_AMD_DC_DCN 632 struct dcn_soc_bounding_box *dcn_soc; 633 struct dcn_ip_params *dcn_ip; 634 struct display_mode_lib dml; 635 #endif 636 637 /* HW functions */ 638 struct hw_sequencer_funcs hwss; 639 struct dce_hwseq *hwseq; 640 641 /* Require to optimize clocks and bandwidth for added/removed planes */ 642 bool optimized_required; 643 bool wm_optimized_required; 644 #if defined(CONFIG_DRM_AMD_DC_DCN) 645 bool idle_optimizations_allowed; 646 #endif 647 648 /* Require to maintain clocks and bandwidth for UEFI enabled HW */ 649 650 /* FBC compressor */ 651 struct compressor *fbc_compressor; 652 653 struct dc_debug_data debug_data; 654 struct dpcd_vendor_signature vendor_signature; 655 656 const char *build_id; 657 struct vm_helper *vm_helper; 658 }; 659 660 enum frame_buffer_mode { 661 FRAME_BUFFER_MODE_LOCAL_ONLY = 0, 662 FRAME_BUFFER_MODE_ZFB_ONLY, 663 FRAME_BUFFER_MODE_MIXED_ZFB_AND_LOCAL, 664 } ; 665 666 struct dchub_init_data { 667 int64_t zfb_phys_addr_base; 668 int64_t zfb_mc_base_addr; 669 uint64_t zfb_size_in_byte; 670 enum frame_buffer_mode fb_mode; 671 bool dchub_initialzied; 672 bool dchub_info_valid; 673 }; 674 675 struct dc_init_data { 676 struct hw_asic_id asic_id; 677 void *driver; /* ctx */ 678 struct cgs_device *cgs_device; 679 struct dc_bounding_box_overrides bb_overrides; 680 681 int num_virtual_links; 682 /* 683 * If 'vbios_override' not NULL, it will be called instead 684 * of the real VBIOS. Intended use is Diagnostics on FPGA. 685 */ 686 struct dc_bios *vbios_override; 687 enum dce_environment dce_environment; 688 689 struct dmub_offload_funcs *dmub_if; 690 struct dc_reg_helper_state *dmub_offload; 691 692 struct dc_config flags; 693 uint64_t log_mask; 694 695 struct dpcd_vendor_signature vendor_signature; 696 #if defined(CONFIG_DRM_AMD_DC_DCN) 697 bool force_smu_not_present; 698 #endif 699 }; 700 701 struct dc_callback_init { 702 #ifdef CONFIG_DRM_AMD_DC_HDCP 703 struct cp_psp cp_psp; 704 #else 705 uint8_t reserved; 706 #endif 707 }; 708 709 struct dc *dc_create(const struct dc_init_data *init_params); 710 void dc_hardware_init(struct dc *dc); 711 712 int dc_get_vmid_use_vector(struct dc *dc); 713 void dc_setup_vm_context(struct dc *dc, struct dc_virtual_addr_space_config *va_config, int vmid); 714 /* Returns the number of vmids supported */ 715 int dc_setup_system_context(struct dc *dc, struct dc_phy_addr_space_config *pa_config); 716 void dc_init_callbacks(struct dc *dc, 717 const struct dc_callback_init *init_params); 718 void dc_deinit_callbacks(struct dc *dc); 719 void dc_destroy(struct dc **dc); 720 721 /******************************************************************************* 722 * Surface Interfaces 723 ******************************************************************************/ 724 725 enum { 726 TRANSFER_FUNC_POINTS = 1025 727 }; 728 729 struct dc_hdr_static_metadata { 730 /* display chromaticities and white point in units of 0.00001 */ 731 unsigned int chromaticity_green_x; 732 unsigned int chromaticity_green_y; 733 unsigned int chromaticity_blue_x; 734 unsigned int chromaticity_blue_y; 735 unsigned int chromaticity_red_x; 736 unsigned int chromaticity_red_y; 737 unsigned int chromaticity_white_point_x; 738 unsigned int chromaticity_white_point_y; 739 740 uint32_t min_luminance; 741 uint32_t max_luminance; 742 uint32_t maximum_content_light_level; 743 uint32_t maximum_frame_average_light_level; 744 }; 745 746 enum dc_transfer_func_type { 747 TF_TYPE_PREDEFINED, 748 TF_TYPE_DISTRIBUTED_POINTS, 749 TF_TYPE_BYPASS, 750 TF_TYPE_HWPWL 751 }; 752 753 struct dc_transfer_func_distributed_points { 754 struct fixed31_32 red[TRANSFER_FUNC_POINTS]; 755 struct fixed31_32 green[TRANSFER_FUNC_POINTS]; 756 struct fixed31_32 blue[TRANSFER_FUNC_POINTS]; 757 758 uint16_t end_exponent; 759 uint16_t x_point_at_y1_red; 760 uint16_t x_point_at_y1_green; 761 uint16_t x_point_at_y1_blue; 762 }; 763 764 enum dc_transfer_func_predefined { 765 TRANSFER_FUNCTION_SRGB, 766 TRANSFER_FUNCTION_BT709, 767 TRANSFER_FUNCTION_PQ, 768 TRANSFER_FUNCTION_LINEAR, 769 TRANSFER_FUNCTION_UNITY, 770 TRANSFER_FUNCTION_HLG, 771 TRANSFER_FUNCTION_HLG12, 772 TRANSFER_FUNCTION_GAMMA22, 773 TRANSFER_FUNCTION_GAMMA24, 774 TRANSFER_FUNCTION_GAMMA26 775 }; 776 777 778 struct dc_transfer_func { 779 struct kref refcount; 780 enum dc_transfer_func_type type; 781 enum dc_transfer_func_predefined tf; 782 /* FP16 1.0 reference level in nits, default is 80 nits, only for PQ*/ 783 uint32_t sdr_ref_white_level; 784 union { 785 struct pwl_params pwl; 786 struct dc_transfer_func_distributed_points tf_pts; 787 }; 788 }; 789 790 791 union dc_3dlut_state { 792 struct { 793 uint32_t initialized:1; /*if 3dlut is went through color module for initialization */ 794 uint32_t rmu_idx_valid:1; /*if mux settings are valid*/ 795 uint32_t rmu_mux_num:3; /*index of mux to use*/ 796 uint32_t mpc_rmu0_mux:4; /*select mpcc on mux, one of the following : mpcc0, mpcc1, mpcc2, mpcc3*/ 797 uint32_t mpc_rmu1_mux:4; 798 uint32_t mpc_rmu2_mux:4; 799 uint32_t reserved:15; 800 } bits; 801 uint32_t raw; 802 }; 803 804 805 struct dc_3dlut { 806 struct kref refcount; 807 struct tetrahedral_params lut_3d; 808 struct fixed31_32 hdr_multiplier; 809 union dc_3dlut_state state; 810 }; 811 /* 812 * This structure is filled in by dc_surface_get_status and contains 813 * the last requested address and the currently active address so the called 814 * can determine if there are any outstanding flips 815 */ 816 struct dc_plane_status { 817 struct dc_plane_address requested_address; 818 struct dc_plane_address current_address; 819 bool is_flip_pending; 820 bool is_right_eye; 821 }; 822 823 union surface_update_flags { 824 825 struct { 826 uint32_t addr_update:1; 827 /* Medium updates */ 828 uint32_t dcc_change:1; 829 uint32_t color_space_change:1; 830 uint32_t horizontal_mirror_change:1; 831 uint32_t per_pixel_alpha_change:1; 832 uint32_t global_alpha_change:1; 833 uint32_t hdr_mult:1; 834 uint32_t rotation_change:1; 835 uint32_t swizzle_change:1; 836 uint32_t scaling_change:1; 837 uint32_t position_change:1; 838 uint32_t in_transfer_func_change:1; 839 uint32_t input_csc_change:1; 840 uint32_t coeff_reduction_change:1; 841 uint32_t output_tf_change:1; 842 uint32_t pixel_format_change:1; 843 uint32_t plane_size_change:1; 844 uint32_t gamut_remap_change:1; 845 846 /* Full updates */ 847 uint32_t new_plane:1; 848 uint32_t bpp_change:1; 849 uint32_t gamma_change:1; 850 uint32_t bandwidth_change:1; 851 uint32_t clock_change:1; 852 uint32_t stereo_format_change:1; 853 uint32_t full_update:1; 854 } bits; 855 856 uint32_t raw; 857 }; 858 859 struct dc_plane_state { 860 struct dc_plane_address address; 861 struct dc_plane_flip_time time; 862 bool triplebuffer_flips; 863 struct scaling_taps scaling_quality; 864 struct rect src_rect; 865 struct rect dst_rect; 866 struct rect clip_rect; 867 868 struct plane_size plane_size; 869 union dc_tiling_info tiling_info; 870 871 struct dc_plane_dcc_param dcc; 872 873 struct dc_gamma *gamma_correction; 874 struct dc_transfer_func *in_transfer_func; 875 struct dc_bias_and_scale *bias_and_scale; 876 struct dc_csc_transform input_csc_color_matrix; 877 struct fixed31_32 coeff_reduction_factor; 878 struct fixed31_32 hdr_mult; 879 struct colorspace_transform gamut_remap_matrix; 880 881 // TODO: No longer used, remove 882 struct dc_hdr_static_metadata hdr_static_ctx; 883 884 enum dc_color_space color_space; 885 886 struct dc_3dlut *lut3d_func; 887 struct dc_transfer_func *in_shaper_func; 888 struct dc_transfer_func *blend_tf; 889 890 #if defined(CONFIG_DRM_AMD_DC_DCN) 891 struct dc_transfer_func *gamcor_tf; 892 #endif 893 enum surface_pixel_format format; 894 enum dc_rotation_angle rotation; 895 enum plane_stereo_format stereo_format; 896 897 bool is_tiling_rotated; 898 bool per_pixel_alpha; 899 bool global_alpha; 900 int global_alpha_value; 901 bool visible; 902 bool flip_immediate; 903 bool horizontal_mirror; 904 int layer_index; 905 906 union surface_update_flags update_flags; 907 bool flip_int_enabled; 908 bool skip_manual_trigger; 909 910 /* private to DC core */ 911 struct dc_plane_status status; 912 struct dc_context *ctx; 913 914 /* HACK: Workaround for forcing full reprogramming under some conditions */ 915 bool force_full_update; 916 917 /* private to dc_surface.c */ 918 enum dc_irq_source irq_source; 919 struct kref refcount; 920 }; 921 922 struct dc_plane_info { 923 struct plane_size plane_size; 924 union dc_tiling_info tiling_info; 925 struct dc_plane_dcc_param dcc; 926 enum surface_pixel_format format; 927 enum dc_rotation_angle rotation; 928 enum plane_stereo_format stereo_format; 929 enum dc_color_space color_space; 930 bool horizontal_mirror; 931 bool visible; 932 bool per_pixel_alpha; 933 bool global_alpha; 934 int global_alpha_value; 935 bool input_csc_enabled; 936 int layer_index; 937 }; 938 939 struct dc_scaling_info { 940 struct rect src_rect; 941 struct rect dst_rect; 942 struct rect clip_rect; 943 struct scaling_taps scaling_quality; 944 }; 945 946 struct dc_surface_update { 947 struct dc_plane_state *surface; 948 949 /* isr safe update parameters. null means no updates */ 950 const struct dc_flip_addrs *flip_addr; 951 const struct dc_plane_info *plane_info; 952 const struct dc_scaling_info *scaling_info; 953 struct fixed31_32 hdr_mult; 954 /* following updates require alloc/sleep/spin that is not isr safe, 955 * null means no updates 956 */ 957 const struct dc_gamma *gamma; 958 const struct dc_transfer_func *in_transfer_func; 959 960 const struct dc_csc_transform *input_csc_color_matrix; 961 const struct fixed31_32 *coeff_reduction_factor; 962 const struct dc_transfer_func *func_shaper; 963 const struct dc_3dlut *lut3d_func; 964 const struct dc_transfer_func *blend_tf; 965 const struct colorspace_transform *gamut_remap_matrix; 966 }; 967 968 /* 969 * Create a new surface with default parameters; 970 */ 971 struct dc_plane_state *dc_create_plane_state(struct dc *dc); 972 const struct dc_plane_status *dc_plane_get_status( 973 const struct dc_plane_state *plane_state); 974 975 void dc_plane_state_retain(struct dc_plane_state *plane_state); 976 void dc_plane_state_release(struct dc_plane_state *plane_state); 977 978 void dc_gamma_retain(struct dc_gamma *dc_gamma); 979 void dc_gamma_release(struct dc_gamma **dc_gamma); 980 struct dc_gamma *dc_create_gamma(void); 981 982 void dc_transfer_func_retain(struct dc_transfer_func *dc_tf); 983 void dc_transfer_func_release(struct dc_transfer_func *dc_tf); 984 struct dc_transfer_func *dc_create_transfer_func(void); 985 986 struct dc_3dlut *dc_create_3dlut_func(void); 987 void dc_3dlut_func_release(struct dc_3dlut *lut); 988 void dc_3dlut_func_retain(struct dc_3dlut *lut); 989 /* 990 * This structure holds a surface address. There could be multiple addresses 991 * in cases such as Stereo 3D, Planar YUV, etc. Other per-flip attributes such 992 * as frame durations and DCC format can also be set. 993 */ 994 struct dc_flip_addrs { 995 struct dc_plane_address address; 996 unsigned int flip_timestamp_in_us; 997 bool flip_immediate; 998 /* TODO: add flip duration for FreeSync */ 999 bool triplebuffer_flips; 1000 }; 1001 1002 void dc_post_update_surfaces_to_stream( 1003 struct dc *dc); 1004 1005 #include "dc_stream.h" 1006 1007 /* 1008 * Structure to store surface/stream associations for validation 1009 */ 1010 struct dc_validation_set { 1011 struct dc_stream_state *stream; 1012 struct dc_plane_state *plane_states[MAX_SURFACES]; 1013 uint8_t plane_count; 1014 }; 1015 1016 bool dc_validate_seamless_boot_timing(const struct dc *dc, 1017 const struct dc_sink *sink, 1018 struct dc_crtc_timing *crtc_timing); 1019 1020 enum dc_status dc_validate_plane(struct dc *dc, const struct dc_plane_state *plane_state); 1021 1022 void get_clock_requirements_for_state(struct dc_state *state, struct AsicStateEx *info); 1023 1024 bool dc_set_generic_gpio_for_stereo(bool enable, 1025 struct gpio_service *gpio_service); 1026 1027 /* 1028 * fast_validate: we return after determining if we can support the new state, 1029 * but before we populate the programming info 1030 */ 1031 enum dc_status dc_validate_global_state( 1032 struct dc *dc, 1033 struct dc_state *new_ctx, 1034 bool fast_validate); 1035 1036 1037 void dc_resource_state_construct( 1038 const struct dc *dc, 1039 struct dc_state *dst_ctx); 1040 1041 #if defined(CONFIG_DRM_AMD_DC_DCN) 1042 bool dc_acquire_release_mpc_3dlut( 1043 struct dc *dc, bool acquire, 1044 struct dc_stream_state *stream, 1045 struct dc_3dlut **lut, 1046 struct dc_transfer_func **shaper); 1047 #endif 1048 1049 void dc_resource_state_copy_construct( 1050 const struct dc_state *src_ctx, 1051 struct dc_state *dst_ctx); 1052 1053 void dc_resource_state_copy_construct_current( 1054 const struct dc *dc, 1055 struct dc_state *dst_ctx); 1056 1057 void dc_resource_state_destruct(struct dc_state *context); 1058 1059 bool dc_resource_is_dsc_encoding_supported(const struct dc *dc); 1060 1061 /* 1062 * TODO update to make it about validation sets 1063 * Set up streams and links associated to drive sinks 1064 * The streams parameter is an absolute set of all active streams. 1065 * 1066 * After this call: 1067 * Phy, Encoder, Timing Generator are programmed and enabled. 1068 * New streams are enabled with blank stream; no memory read. 1069 */ 1070 bool dc_commit_state(struct dc *dc, struct dc_state *context); 1071 1072 void dc_power_down_on_boot(struct dc *dc); 1073 1074 struct dc_state *dc_create_state(struct dc *dc); 1075 struct dc_state *dc_copy_state(struct dc_state *src_ctx); 1076 void dc_retain_state(struct dc_state *context); 1077 void dc_release_state(struct dc_state *context); 1078 1079 /******************************************************************************* 1080 * Link Interfaces 1081 ******************************************************************************/ 1082 1083 struct dpcd_caps { 1084 union dpcd_rev dpcd_rev; 1085 union max_lane_count max_ln_count; 1086 union max_down_spread max_down_spread; 1087 union dprx_feature dprx_feature; 1088 1089 /* valid only for eDP v1.4 or higher*/ 1090 uint8_t edp_supported_link_rates_count; 1091 enum dc_link_rate edp_supported_link_rates[8]; 1092 1093 /* dongle type (DP converter, CV smart dongle) */ 1094 enum display_dongle_type dongle_type; 1095 /* branch device or sink device */ 1096 bool is_branch_dev; 1097 /* Dongle's downstream count. */ 1098 union sink_count sink_count; 1099 /* If dongle_type == DISPLAY_DONGLE_DP_HDMI_CONVERTER, 1100 indicates 'Frame Sequential-to-lllFrame Pack' conversion capability.*/ 1101 struct dc_dongle_caps dongle_caps; 1102 1103 uint32_t sink_dev_id; 1104 int8_t sink_dev_id_str[6]; 1105 int8_t sink_hw_revision; 1106 int8_t sink_fw_revision[2]; 1107 1108 uint32_t branch_dev_id; 1109 int8_t branch_dev_name[6]; 1110 int8_t branch_hw_revision; 1111 int8_t branch_fw_revision[2]; 1112 1113 bool allow_invalid_MSA_timing_param; 1114 bool panel_mode_edp; 1115 bool dpcd_display_control_capable; 1116 bool ext_receiver_cap_field_present; 1117 bool dynamic_backlight_capable_edp; 1118 union dpcd_fec_capability fec_cap; 1119 struct dpcd_dsc_capabilities dsc_caps; 1120 struct dc_lttpr_caps lttpr_caps; 1121 struct psr_caps psr_caps; 1122 1123 }; 1124 1125 union dpcd_sink_ext_caps { 1126 struct { 1127 /* 0 - Sink supports backlight adjust via PWM during SDR/HDR mode 1128 * 1 - Sink supports backlight adjust via AUX during SDR/HDR mode. 1129 */ 1130 uint8_t sdr_aux_backlight_control : 1; 1131 uint8_t hdr_aux_backlight_control : 1; 1132 uint8_t reserved_1 : 2; 1133 uint8_t oled : 1; 1134 uint8_t reserved : 3; 1135 } bits; 1136 uint8_t raw; 1137 }; 1138 1139 #if defined(CONFIG_DRM_AMD_DC_HDCP) 1140 union hdcp_rx_caps { 1141 struct { 1142 uint8_t version; 1143 uint8_t reserved; 1144 struct { 1145 uint8_t repeater : 1; 1146 uint8_t hdcp_capable : 1; 1147 uint8_t reserved : 6; 1148 } byte0; 1149 } fields; 1150 uint8_t raw[3]; 1151 }; 1152 1153 union hdcp_bcaps { 1154 struct { 1155 uint8_t HDCP_CAPABLE:1; 1156 uint8_t REPEATER:1; 1157 uint8_t RESERVED:6; 1158 } bits; 1159 uint8_t raw; 1160 }; 1161 1162 struct hdcp_caps { 1163 union hdcp_rx_caps rx_caps; 1164 union hdcp_bcaps bcaps; 1165 }; 1166 #endif 1167 1168 #include "dc_link.h" 1169 1170 #if defined(CONFIG_DRM_AMD_DC_DCN) 1171 uint32_t dc_get_opp_for_plane(struct dc *dc, struct dc_plane_state *plane); 1172 1173 #endif 1174 /******************************************************************************* 1175 * Sink Interfaces - A sink corresponds to a display output device 1176 ******************************************************************************/ 1177 1178 struct dc_container_id { 1179 // 128bit GUID in binary form 1180 unsigned char guid[16]; 1181 // 8 byte port ID -> ELD.PortID 1182 unsigned int portId[2]; 1183 // 128bit GUID in binary formufacturer name -> ELD.ManufacturerName 1184 unsigned short manufacturerName; 1185 // 2 byte product code -> ELD.ProductCode 1186 unsigned short productCode; 1187 }; 1188 1189 1190 struct dc_sink_dsc_caps { 1191 // 'true' if these are virtual DPCD's DSC caps (immediately upstream of sink in MST topology), 1192 // 'false' if they are sink's DSC caps 1193 bool is_virtual_dpcd_dsc; 1194 struct dsc_dec_dpcd_caps dsc_dec_caps; 1195 }; 1196 1197 struct dc_sink_fec_caps { 1198 bool is_rx_fec_supported; 1199 bool is_topology_fec_supported; 1200 }; 1201 1202 /* 1203 * The sink structure contains EDID and other display device properties 1204 */ 1205 struct dc_sink { 1206 enum signal_type sink_signal; 1207 struct dc_edid dc_edid; /* raw edid */ 1208 struct dc_edid_caps edid_caps; /* parse display caps */ 1209 struct dc_container_id *dc_container_id; 1210 uint32_t dongle_max_pix_clk; 1211 void *priv; 1212 struct stereo_3d_features features_3d[TIMING_3D_FORMAT_MAX]; 1213 bool converter_disable_audio; 1214 1215 struct dc_sink_dsc_caps dsc_caps; 1216 struct dc_sink_fec_caps fec_caps; 1217 1218 bool is_vsc_sdp_colorimetry_supported; 1219 1220 /* private to DC core */ 1221 struct dc_link *link; 1222 struct dc_context *ctx; 1223 1224 uint32_t sink_id; 1225 1226 /* private to dc_sink.c */ 1227 // refcount must be the last member in dc_sink, since we want the 1228 // sink structure to be logically cloneable up to (but not including) 1229 // refcount 1230 struct kref refcount; 1231 }; 1232 1233 void dc_sink_retain(struct dc_sink *sink); 1234 void dc_sink_release(struct dc_sink *sink); 1235 1236 struct dc_sink_init_data { 1237 enum signal_type sink_signal; 1238 struct dc_link *link; 1239 uint32_t dongle_max_pix_clk; 1240 bool converter_disable_audio; 1241 }; 1242 1243 struct dc_sink *dc_sink_create(const struct dc_sink_init_data *init_params); 1244 1245 /* Newer interfaces */ 1246 struct dc_cursor { 1247 struct dc_plane_address address; 1248 struct dc_cursor_attributes attributes; 1249 }; 1250 1251 1252 /******************************************************************************* 1253 * Interrupt interfaces 1254 ******************************************************************************/ 1255 enum dc_irq_source dc_interrupt_to_irq_source( 1256 struct dc *dc, 1257 uint32_t src_id, 1258 uint32_t ext_id); 1259 bool dc_interrupt_set(struct dc *dc, enum dc_irq_source src, bool enable); 1260 void dc_interrupt_ack(struct dc *dc, enum dc_irq_source src); 1261 enum dc_irq_source dc_get_hpd_irq_source_at_index( 1262 struct dc *dc, uint32_t link_index); 1263 1264 /******************************************************************************* 1265 * Power Interfaces 1266 ******************************************************************************/ 1267 1268 void dc_set_power_state( 1269 struct dc *dc, 1270 enum dc_acpi_cm_power_state power_state); 1271 void dc_resume(struct dc *dc); 1272 1273 void dc_power_down_on_boot(struct dc *dc); 1274 1275 #if defined(CONFIG_DRM_AMD_DC_HDCP) 1276 /* 1277 * HDCP Interfaces 1278 */ 1279 enum hdcp_message_status dc_process_hdcp_msg( 1280 enum signal_type signal, 1281 struct dc_link *link, 1282 struct hdcp_protection_message *message_info); 1283 #endif 1284 bool dc_is_dmcu_initialized(struct dc *dc); 1285 1286 enum dc_status dc_set_clock(struct dc *dc, enum dc_clock_type clock_type, uint32_t clk_khz, uint32_t stepping); 1287 void dc_get_clock(struct dc *dc, enum dc_clock_type clock_type, struct dc_clock_config *clock_cfg); 1288 #if defined(CONFIG_DRM_AMD_DC_DCN) 1289 1290 bool dc_is_plane_eligible_for_idle_optimizations(struct dc *dc, struct dc_plane_state *plane, 1291 struct dc_cursor_attributes *cursor_attr); 1292 1293 void dc_allow_idle_optimizations(struct dc *dc, bool allow); 1294 1295 /* 1296 * blank all streams, and set min and max memory clock to 1297 * lowest and highest DPM level, respectively 1298 */ 1299 void dc_unlock_memory_clock_frequency(struct dc *dc); 1300 1301 /* 1302 * set min memory clock to the min required for current mode, 1303 * max to maxDPM, and unblank streams 1304 */ 1305 void dc_lock_memory_clock_frequency(struct dc *dc); 1306 1307 /* cleanup on driver unload */ 1308 void dc_hardware_release(struct dc *dc); 1309 1310 #endif 1311 1312 bool dc_set_psr_allow_active(struct dc *dc, bool enable); 1313 1314 bool dc_enable_dmub_notifications(struct dc *dc); 1315 1316 bool dc_process_dmub_aux_transfer_async(struct dc *dc, 1317 uint32_t link_index, 1318 struct aux_payload *payload); 1319 1320 /******************************************************************************* 1321 * DSC Interfaces 1322 ******************************************************************************/ 1323 #include "dc_dsc.h" 1324 1325 /******************************************************************************* 1326 * Disable acc mode Interfaces 1327 ******************************************************************************/ 1328 void dc_disable_accelerated_mode(struct dc *dc); 1329 1330 #endif /* DC_INTERFACE_H_ */ 1331