1 /* 2 * Copyright 2012-14 Advanced Micro Devices, Inc. 3 * 4 * Permission is hereby granted, free of charge, to any person obtaining a 5 * copy of this software and associated documentation files (the "Software"), 6 * to deal in the Software without restriction, including without limitation 7 * the rights to use, copy, modify, merge, publish, distribute, sublicense, 8 * and/or sell copies of the Software, and to permit persons to whom the 9 * Software is furnished to do so, subject to the following conditions: 10 * 11 * The above copyright notice and this permission notice shall be included in 12 * all copies or substantial portions of the Software. 13 * 14 * THE SOFTWARE IS PROVIDED "AS IS", WITHOUT WARRANTY OF ANY KIND, EXPRESS OR 15 * IMPLIED, INCLUDING BUT NOT LIMITED TO THE WARRANTIES OF MERCHANTABILITY, 16 * FITNESS FOR A PARTICULAR PURPOSE AND NONINFRINGEMENT. IN NO EVENT SHALL 17 * THE COPYRIGHT HOLDER(S) OR AUTHOR(S) BE LIABLE FOR ANY CLAIM, DAMAGES OR 18 * OTHER LIABILITY, WHETHER IN AN ACTION OF CONTRACT, TORT OR OTHERWISE, 19 * ARISING FROM, OUT OF OR IN CONNECTION WITH THE SOFTWARE OR THE USE OR 20 * OTHER DEALINGS IN THE SOFTWARE. 21 * 22 * Authors: AMD 23 * 24 */ 25 26 #ifndef DC_INTERFACE_H_ 27 #define DC_INTERFACE_H_ 28 29 #include "dc_types.h" 30 #include "grph_object_defs.h" 31 #include "logger_types.h" 32 #if defined(CONFIG_DRM_AMD_DC_HDCP) 33 #include "hdcp_types.h" 34 #endif 35 #include "gpio_types.h" 36 #include "link_service_types.h" 37 #include "grph_object_ctrl_defs.h" 38 #include <inc/hw/opp.h> 39 40 #include "inc/hw_sequencer.h" 41 #include "inc/compressor.h" 42 #include "inc/hw/dmcu.h" 43 #include "dml/display_mode_lib.h" 44 45 /* forward declaration */ 46 struct aux_payload; 47 48 #define DC_VER "3.2.155" 49 50 #define MAX_SURFACES 3 51 #define MAX_PLANES 6 52 #define MAX_STREAMS 6 53 #define MAX_SINKS_PER_LINK 4 54 #define MIN_VIEWPORT_SIZE 12 55 #define MAX_NUM_EDP 2 56 57 /******************************************************************************* 58 * Display Core Interfaces 59 ******************************************************************************/ 60 struct dc_versions { 61 const char *dc_ver; 62 struct dmcu_version dmcu_version; 63 }; 64 65 enum dp_protocol_version { 66 DP_VERSION_1_4, 67 }; 68 69 enum dc_plane_type { 70 DC_PLANE_TYPE_INVALID, 71 DC_PLANE_TYPE_DCE_RGB, 72 DC_PLANE_TYPE_DCE_UNDERLAY, 73 DC_PLANE_TYPE_DCN_UNIVERSAL, 74 }; 75 76 struct dc_plane_cap { 77 enum dc_plane_type type; 78 uint32_t blends_with_above : 1; 79 uint32_t blends_with_below : 1; 80 uint32_t per_pixel_alpha : 1; 81 struct { 82 uint32_t argb8888 : 1; 83 uint32_t nv12 : 1; 84 uint32_t fp16 : 1; 85 uint32_t p010 : 1; 86 uint32_t ayuv : 1; 87 } pixel_format_support; 88 // max upscaling factor x1000 89 // upscaling factors are always >= 1 90 // for example, 1080p -> 8K is 4.0, or 4000 raw value 91 struct { 92 uint32_t argb8888; 93 uint32_t nv12; 94 uint32_t fp16; 95 } max_upscale_factor; 96 // max downscale factor x1000 97 // downscale factors are always <= 1 98 // for example, 8K -> 1080p is 0.25, or 250 raw value 99 struct { 100 uint32_t argb8888; 101 uint32_t nv12; 102 uint32_t fp16; 103 } max_downscale_factor; 104 // minimal width/height 105 uint32_t min_width; 106 uint32_t min_height; 107 }; 108 109 // Color management caps (DPP and MPC) 110 struct rom_curve_caps { 111 uint16_t srgb : 1; 112 uint16_t bt2020 : 1; 113 uint16_t gamma2_2 : 1; 114 uint16_t pq : 1; 115 uint16_t hlg : 1; 116 }; 117 118 struct dpp_color_caps { 119 uint16_t dcn_arch : 1; // all DCE generations treated the same 120 // input lut is different than most LUTs, just plain 256-entry lookup 121 uint16_t input_lut_shared : 1; // shared with DGAM 122 uint16_t icsc : 1; 123 uint16_t dgam_ram : 1; 124 uint16_t post_csc : 1; // before gamut remap 125 uint16_t gamma_corr : 1; 126 127 // hdr_mult and gamut remap always available in DPP (in that order) 128 // 3d lut implies shaper LUT, 129 // it may be shared with MPC - check MPC:shared_3d_lut flag 130 uint16_t hw_3d_lut : 1; 131 uint16_t ogam_ram : 1; // blnd gam 132 uint16_t ocsc : 1; 133 uint16_t dgam_rom_for_yuv : 1; 134 struct rom_curve_caps dgam_rom_caps; 135 struct rom_curve_caps ogam_rom_caps; 136 }; 137 138 struct mpc_color_caps { 139 uint16_t gamut_remap : 1; 140 uint16_t ogam_ram : 1; 141 uint16_t ocsc : 1; 142 uint16_t num_3dluts : 3; //3d lut always assumes a preceding shaper LUT 143 uint16_t shared_3d_lut:1; //can be in either DPP or MPC, but single instance 144 145 struct rom_curve_caps ogam_rom_caps; 146 }; 147 148 struct dc_color_caps { 149 struct dpp_color_caps dpp; 150 struct mpc_color_caps mpc; 151 }; 152 153 struct dc_caps { 154 uint32_t max_streams; 155 uint32_t max_links; 156 uint32_t max_audios; 157 uint32_t max_slave_planes; 158 uint32_t max_slave_yuv_planes; 159 uint32_t max_slave_rgb_planes; 160 uint32_t max_planes; 161 uint32_t max_downscale_ratio; 162 uint32_t i2c_speed_in_khz; 163 uint32_t i2c_speed_in_khz_hdcp; 164 uint32_t dmdata_alloc_size; 165 unsigned int max_cursor_size; 166 unsigned int max_video_width; 167 unsigned int min_horizontal_blanking_period; 168 int linear_pitch_alignment; 169 bool dcc_const_color; 170 bool dynamic_audio; 171 bool is_apu; 172 bool dual_link_dvi; 173 bool post_blend_color_processing; 174 bool force_dp_tps4_for_cp2520; 175 bool disable_dp_clk_share; 176 bool psp_setup_panel_mode; 177 bool extended_aux_timeout_support; 178 bool dmcub_support; 179 uint32_t num_of_internal_disp; 180 enum dp_protocol_version max_dp_protocol_version; 181 unsigned int mall_size_per_mem_channel; 182 unsigned int mall_size_total; 183 unsigned int cursor_cache_size; 184 struct dc_plane_cap planes[MAX_PLANES]; 185 struct dc_color_caps color; 186 #if defined(CONFIG_DRM_AMD_DC_DCN) 187 bool dp_hpo; 188 #endif 189 bool vbios_lttpr_aware; 190 bool vbios_lttpr_enable; 191 }; 192 193 struct dc_bug_wa { 194 bool no_connect_phy_config; 195 bool dedcn20_305_wa; 196 bool skip_clock_update; 197 bool lt_early_cr_pattern; 198 }; 199 200 struct dc_dcc_surface_param { 201 struct dc_size surface_size; 202 enum surface_pixel_format format; 203 enum swizzle_mode_values swizzle_mode; 204 enum dc_scan_direction scan; 205 }; 206 207 struct dc_dcc_setting { 208 unsigned int max_compressed_blk_size; 209 unsigned int max_uncompressed_blk_size; 210 bool independent_64b_blks; 211 #if defined(CONFIG_DRM_AMD_DC_DCN) 212 //These bitfields to be used starting with DCN 3.0 213 struct { 214 uint32_t dcc_256_64_64 : 1;//available in ASICs before DCN 3.0 (the worst compression case) 215 uint32_t dcc_128_128_uncontrained : 1; //available in ASICs before DCN 3.0 216 uint32_t dcc_256_128_128 : 1; //available starting with DCN 3.0 217 uint32_t dcc_256_256_unconstrained : 1; //available in ASICs before DCN 3.0 (the best compression case) 218 } dcc_controls; 219 #endif 220 }; 221 222 struct dc_surface_dcc_cap { 223 union { 224 struct { 225 struct dc_dcc_setting rgb; 226 } grph; 227 228 struct { 229 struct dc_dcc_setting luma; 230 struct dc_dcc_setting chroma; 231 } video; 232 }; 233 234 bool capable; 235 bool const_color_support; 236 }; 237 238 struct dc_static_screen_params { 239 struct { 240 bool force_trigger; 241 bool cursor_update; 242 bool surface_update; 243 bool overlay_update; 244 } triggers; 245 unsigned int num_frames; 246 }; 247 248 249 /* Surface update type is used by dc_update_surfaces_and_stream 250 * The update type is determined at the very beginning of the function based 251 * on parameters passed in and decides how much programming (or updating) is 252 * going to be done during the call. 253 * 254 * UPDATE_TYPE_FAST is used for really fast updates that do not require much 255 * logical calculations or hardware register programming. This update MUST be 256 * ISR safe on windows. Currently fast update will only be used to flip surface 257 * address. 258 * 259 * UPDATE_TYPE_MED is used for slower updates which require significant hw 260 * re-programming however do not affect bandwidth consumption or clock 261 * requirements. At present, this is the level at which front end updates 262 * that do not require us to run bw_calcs happen. These are in/out transfer func 263 * updates, viewport offset changes, recout size changes and pixel depth changes. 264 * This update can be done at ISR, but we want to minimize how often this happens. 265 * 266 * UPDATE_TYPE_FULL is slow. Really slow. This requires us to recalculate our 267 * bandwidth and clocks, possibly rearrange some pipes and reprogram anything front 268 * end related. Any time viewport dimensions, recout dimensions, scaling ratios or 269 * gamma need to be adjusted or pipe needs to be turned on (or disconnected) we do 270 * a full update. This cannot be done at ISR level and should be a rare event. 271 * Unless someone is stress testing mpo enter/exit, playing with colour or adjusting 272 * underscan we don't expect to see this call at all. 273 */ 274 275 enum surface_update_type { 276 UPDATE_TYPE_FAST, /* super fast, safe to execute in isr */ 277 UPDATE_TYPE_MED, /* ISR safe, most of programming needed, no bw/clk change*/ 278 UPDATE_TYPE_FULL, /* may need to shuffle resources */ 279 }; 280 281 /* Forward declaration*/ 282 struct dc; 283 struct dc_plane_state; 284 struct dc_state; 285 286 287 struct dc_cap_funcs { 288 bool (*get_dcc_compression_cap)(const struct dc *dc, 289 const struct dc_dcc_surface_param *input, 290 struct dc_surface_dcc_cap *output); 291 }; 292 293 struct link_training_settings; 294 295 #if defined(CONFIG_DRM_AMD_DC_DCN) 296 union allow_lttpr_non_transparent_mode { 297 struct { 298 bool DP1_4A : 1; 299 bool DP2_0 : 1; 300 } bits; 301 unsigned char raw; 302 }; 303 #endif 304 /* Structure to hold configuration flags set by dm at dc creation. */ 305 struct dc_config { 306 bool gpu_vm_support; 307 bool disable_disp_pll_sharing; 308 bool fbc_support; 309 bool disable_fractional_pwm; 310 bool allow_seamless_boot_optimization; 311 bool power_down_display_on_boot; 312 bool edp_not_connected; 313 bool edp_no_power_sequencing; 314 bool force_enum_edp; 315 bool forced_clocks; 316 #if defined(CONFIG_DRM_AMD_DC_DCN) 317 union allow_lttpr_non_transparent_mode allow_lttpr_non_transparent_mode; 318 #else 319 bool allow_lttpr_non_transparent_mode; 320 #endif 321 bool multi_mon_pp_mclk_switch; 322 bool disable_dmcu; 323 bool enable_4to1MPC; 324 bool allow_edp_hotplug_detection; 325 #if defined(CONFIG_DRM_AMD_DC_DCN) 326 bool clamp_min_dcfclk; 327 #endif 328 uint64_t vblank_alignment_dto_params; 329 uint8_t vblank_alignment_max_frame_time_diff; 330 bool is_asymmetric_memory; 331 bool is_single_rank_dimm; 332 }; 333 334 enum visual_confirm { 335 VISUAL_CONFIRM_DISABLE = 0, 336 VISUAL_CONFIRM_SURFACE = 1, 337 VISUAL_CONFIRM_HDR = 2, 338 VISUAL_CONFIRM_MPCTREE = 4, 339 VISUAL_CONFIRM_PSR = 5, 340 VISUAL_CONFIRM_SWIZZLE = 9, 341 }; 342 343 enum dcc_option { 344 DCC_ENABLE = 0, 345 DCC_DISABLE = 1, 346 DCC_HALF_REQ_DISALBE = 2, 347 }; 348 349 enum pipe_split_policy { 350 MPC_SPLIT_DYNAMIC = 0, 351 MPC_SPLIT_AVOID = 1, 352 MPC_SPLIT_AVOID_MULT_DISP = 2, 353 }; 354 355 enum wm_report_mode { 356 WM_REPORT_DEFAULT = 0, 357 WM_REPORT_OVERRIDE = 1, 358 }; 359 enum dtm_pstate{ 360 dtm_level_p0 = 0,/*highest voltage*/ 361 dtm_level_p1, 362 dtm_level_p2, 363 dtm_level_p3, 364 dtm_level_p4,/*when active_display_count = 0*/ 365 }; 366 367 enum dcn_pwr_state { 368 DCN_PWR_STATE_UNKNOWN = -1, 369 DCN_PWR_STATE_MISSION_MODE = 0, 370 DCN_PWR_STATE_LOW_POWER = 3, 371 }; 372 373 #if defined(CONFIG_DRM_AMD_DC_DCN) 374 enum dcn_zstate_support_state { 375 DCN_ZSTATE_SUPPORT_UNKNOWN, 376 DCN_ZSTATE_SUPPORT_ALLOW, 377 DCN_ZSTATE_SUPPORT_DISALLOW, 378 }; 379 #endif 380 /* 381 * For any clocks that may differ per pipe 382 * only the max is stored in this structure 383 */ 384 struct dc_clocks { 385 int dispclk_khz; 386 int actual_dispclk_khz; 387 int dppclk_khz; 388 int actual_dppclk_khz; 389 int disp_dpp_voltage_level_khz; 390 int dcfclk_khz; 391 int socclk_khz; 392 int dcfclk_deep_sleep_khz; 393 int fclk_khz; 394 int phyclk_khz; 395 int dramclk_khz; 396 bool p_state_change_support; 397 #if defined(CONFIG_DRM_AMD_DC_DCN) 398 enum dcn_zstate_support_state zstate_support; 399 bool dtbclk_en; 400 #endif 401 enum dcn_pwr_state pwr_state; 402 /* 403 * Elements below are not compared for the purposes of 404 * optimization required 405 */ 406 bool prev_p_state_change_support; 407 enum dtm_pstate dtm_level; 408 int max_supported_dppclk_khz; 409 int max_supported_dispclk_khz; 410 int bw_dppclk_khz; /*a copy of dppclk_khz*/ 411 int bw_dispclk_khz; 412 }; 413 414 struct dc_bw_validation_profile { 415 bool enable; 416 417 unsigned long long total_ticks; 418 unsigned long long voltage_level_ticks; 419 unsigned long long watermark_ticks; 420 unsigned long long rq_dlg_ticks; 421 422 unsigned long long total_count; 423 unsigned long long skip_fast_count; 424 unsigned long long skip_pass_count; 425 unsigned long long skip_fail_count; 426 }; 427 428 #define BW_VAL_TRACE_SETUP() \ 429 unsigned long long end_tick = 0; \ 430 unsigned long long voltage_level_tick = 0; \ 431 unsigned long long watermark_tick = 0; \ 432 unsigned long long start_tick = dc->debug.bw_val_profile.enable ? \ 433 dm_get_timestamp(dc->ctx) : 0 434 435 #define BW_VAL_TRACE_COUNT() \ 436 if (dc->debug.bw_val_profile.enable) \ 437 dc->debug.bw_val_profile.total_count++ 438 439 #define BW_VAL_TRACE_SKIP(status) \ 440 if (dc->debug.bw_val_profile.enable) { \ 441 if (!voltage_level_tick) \ 442 voltage_level_tick = dm_get_timestamp(dc->ctx); \ 443 dc->debug.bw_val_profile.skip_ ## status ## _count++; \ 444 } 445 446 #define BW_VAL_TRACE_END_VOLTAGE_LEVEL() \ 447 if (dc->debug.bw_val_profile.enable) \ 448 voltage_level_tick = dm_get_timestamp(dc->ctx) 449 450 #define BW_VAL_TRACE_END_WATERMARKS() \ 451 if (dc->debug.bw_val_profile.enable) \ 452 watermark_tick = dm_get_timestamp(dc->ctx) 453 454 #define BW_VAL_TRACE_FINISH() \ 455 if (dc->debug.bw_val_profile.enable) { \ 456 end_tick = dm_get_timestamp(dc->ctx); \ 457 dc->debug.bw_val_profile.total_ticks += end_tick - start_tick; \ 458 dc->debug.bw_val_profile.voltage_level_ticks += voltage_level_tick - start_tick; \ 459 if (watermark_tick) { \ 460 dc->debug.bw_val_profile.watermark_ticks += watermark_tick - voltage_level_tick; \ 461 dc->debug.bw_val_profile.rq_dlg_ticks += end_tick - watermark_tick; \ 462 } \ 463 } 464 465 union mem_low_power_enable_options { 466 struct { 467 bool vga: 1; 468 bool i2c: 1; 469 bool dmcu: 1; 470 bool dscl: 1; 471 bool cm: 1; 472 bool mpc: 1; 473 bool optc: 1; 474 bool vpg: 1; 475 bool afmt: 1; 476 } bits; 477 uint32_t u32All; 478 }; 479 480 struct dc_debug_data { 481 uint32_t ltFailCount; 482 uint32_t i2cErrorCount; 483 uint32_t auxErrorCount; 484 }; 485 486 struct dc_phy_addr_space_config { 487 struct { 488 uint64_t start_addr; 489 uint64_t end_addr; 490 uint64_t fb_top; 491 uint64_t fb_offset; 492 uint64_t fb_base; 493 uint64_t agp_top; 494 uint64_t agp_bot; 495 uint64_t agp_base; 496 } system_aperture; 497 498 struct { 499 uint64_t page_table_start_addr; 500 uint64_t page_table_end_addr; 501 uint64_t page_table_base_addr; 502 bool base_addr_is_mc_addr; 503 } gart_config; 504 505 bool valid; 506 bool is_hvm_enabled; 507 uint64_t page_table_default_page_addr; 508 }; 509 510 struct dc_virtual_addr_space_config { 511 uint64_t page_table_base_addr; 512 uint64_t page_table_start_addr; 513 uint64_t page_table_end_addr; 514 uint32_t page_table_block_size_in_bytes; 515 uint8_t page_table_depth; // 1 = 1 level, 2 = 2 level, etc. 0 = invalid 516 }; 517 518 struct dc_bounding_box_overrides { 519 int sr_exit_time_ns; 520 int sr_enter_plus_exit_time_ns; 521 int urgent_latency_ns; 522 int percent_of_ideal_drambw; 523 int dram_clock_change_latency_ns; 524 int dummy_clock_change_latency_ns; 525 /* This forces a hard min on the DCFCLK we use 526 * for DML. Unlike the debug option for forcing 527 * DCFCLK, this override affects watermark calculations 528 */ 529 int min_dcfclk_mhz; 530 }; 531 532 struct dc_state; 533 struct resource_pool; 534 struct dce_hwseq; 535 536 struct dc_debug_options { 537 bool native422_support; 538 bool disable_dsc; 539 enum visual_confirm visual_confirm; 540 bool sanity_checks; 541 bool max_disp_clk; 542 bool surface_trace; 543 bool timing_trace; 544 bool clock_trace; 545 bool validation_trace; 546 bool bandwidth_calcs_trace; 547 int max_downscale_src_width; 548 549 /* stutter efficiency related */ 550 bool disable_stutter; 551 bool use_max_lb; 552 enum dcc_option disable_dcc; 553 enum pipe_split_policy pipe_split_policy; 554 bool force_single_disp_pipe_split; 555 bool voltage_align_fclk; 556 bool disable_min_fclk; 557 558 bool disable_dfs_bypass; 559 bool disable_dpp_power_gate; 560 bool disable_hubp_power_gate; 561 bool disable_dsc_power_gate; 562 int dsc_min_slice_height_override; 563 int dsc_bpp_increment_div; 564 bool disable_pplib_wm_range; 565 enum wm_report_mode pplib_wm_report_mode; 566 unsigned int min_disp_clk_khz; 567 unsigned int min_dpp_clk_khz; 568 unsigned int min_dram_clk_khz; 569 int sr_exit_time_dpm0_ns; 570 int sr_enter_plus_exit_time_dpm0_ns; 571 int sr_exit_time_ns; 572 int sr_enter_plus_exit_time_ns; 573 int urgent_latency_ns; 574 uint32_t underflow_assert_delay_us; 575 int percent_of_ideal_drambw; 576 int dram_clock_change_latency_ns; 577 bool optimized_watermark; 578 int always_scale; 579 bool disable_pplib_clock_request; 580 bool disable_clock_gate; 581 bool disable_mem_low_power; 582 #if defined(CONFIG_DRM_AMD_DC_DCN) 583 bool pstate_enabled; 584 #endif 585 bool disable_dmcu; 586 bool disable_psr; 587 bool force_abm_enable; 588 bool disable_stereo_support; 589 bool vsr_support; 590 bool performance_trace; 591 bool az_endpoint_mute_only; 592 bool always_use_regamma; 593 bool recovery_enabled; 594 bool avoid_vbios_exec_table; 595 bool scl_reset_length10; 596 bool hdmi20_disable; 597 bool skip_detection_link_training; 598 uint32_t edid_read_retry_times; 599 bool remove_disconnect_edp; 600 unsigned int force_odm_combine; //bit vector based on otg inst 601 #if defined(CONFIG_DRM_AMD_DC_DCN) 602 unsigned int force_odm_combine_4to1; //bit vector based on otg inst 603 bool disable_z9_mpc; 604 #endif 605 unsigned int force_fclk_khz; 606 bool enable_tri_buf; 607 bool dmub_offload_enabled; 608 bool dmcub_emulation; 609 #if defined(CONFIG_DRM_AMD_DC_DCN) 610 bool disable_idle_power_optimizations; 611 unsigned int mall_size_override; 612 unsigned int mall_additional_timer_percent; 613 bool mall_error_as_fatal; 614 #endif 615 bool dmub_command_table; /* for testing only */ 616 struct dc_bw_validation_profile bw_val_profile; 617 bool disable_fec; 618 bool disable_48mhz_pwrdwn; 619 /* This forces a hard min on the DCFCLK requested to SMU/PP 620 * watermarks are not affected. 621 */ 622 unsigned int force_min_dcfclk_mhz; 623 #if defined(CONFIG_DRM_AMD_DC_DCN) 624 int dwb_fi_phase; 625 #endif 626 bool disable_timing_sync; 627 bool cm_in_bypass; 628 int force_clock_mode;/*every mode change.*/ 629 630 bool disable_dram_clock_change_vactive_support; 631 bool validate_dml_output; 632 bool enable_dmcub_surface_flip; 633 bool usbc_combo_phy_reset_wa; 634 bool enable_dram_clock_change_one_display_vactive; 635 #if defined(CONFIG_DRM_AMD_DC_DCN) 636 /* TODO - remove once tested */ 637 bool legacy_dp2_lt; 638 #endif 639 union mem_low_power_enable_options enable_mem_low_power; 640 bool force_vblank_alignment; 641 642 /* Enable dmub aux for legacy ddc */ 643 bool enable_dmub_aux_for_legacy_ddc; 644 bool optimize_edp_link_rate; /* eDP ILR */ 645 /* FEC/PSR1 sequence enable delay in 100us */ 646 uint8_t fec_enable_delay_in100us; 647 bool enable_driver_sequence_debug; 648 #if defined(CONFIG_DRM_AMD_DC_DCN) 649 bool disable_z10; 650 bool enable_sw_cntl_psr; 651 #endif 652 }; 653 654 struct gpu_info_soc_bounding_box_v1_0; 655 struct dc { 656 struct dc_debug_options debug; 657 struct dc_versions versions; 658 struct dc_caps caps; 659 struct dc_cap_funcs cap_funcs; 660 struct dc_config config; 661 struct dc_bounding_box_overrides bb_overrides; 662 struct dc_bug_wa work_arounds; 663 struct dc_context *ctx; 664 struct dc_phy_addr_space_config vm_pa_config; 665 666 uint8_t link_count; 667 struct dc_link *links[MAX_PIPES * 2]; 668 669 struct dc_state *current_state; 670 struct resource_pool *res_pool; 671 672 struct clk_mgr *clk_mgr; 673 674 /* Display Engine Clock levels */ 675 struct dm_pp_clock_levels sclk_lvls; 676 677 /* Inputs into BW and WM calculations. */ 678 struct bw_calcs_dceip *bw_dceip; 679 struct bw_calcs_vbios *bw_vbios; 680 #ifdef CONFIG_DRM_AMD_DC_DCN 681 struct dcn_soc_bounding_box *dcn_soc; 682 struct dcn_ip_params *dcn_ip; 683 struct display_mode_lib dml; 684 #endif 685 686 /* HW functions */ 687 struct hw_sequencer_funcs hwss; 688 struct dce_hwseq *hwseq; 689 690 /* Require to optimize clocks and bandwidth for added/removed planes */ 691 bool optimized_required; 692 bool wm_optimized_required; 693 #if defined(CONFIG_DRM_AMD_DC_DCN) 694 bool idle_optimizations_allowed; 695 #endif 696 697 /* Require to maintain clocks and bandwidth for UEFI enabled HW */ 698 699 /* FBC compressor */ 700 struct compressor *fbc_compressor; 701 702 struct dc_debug_data debug_data; 703 struct dpcd_vendor_signature vendor_signature; 704 705 const char *build_id; 706 struct vm_helper *vm_helper; 707 }; 708 709 enum frame_buffer_mode { 710 FRAME_BUFFER_MODE_LOCAL_ONLY = 0, 711 FRAME_BUFFER_MODE_ZFB_ONLY, 712 FRAME_BUFFER_MODE_MIXED_ZFB_AND_LOCAL, 713 } ; 714 715 struct dchub_init_data { 716 int64_t zfb_phys_addr_base; 717 int64_t zfb_mc_base_addr; 718 uint64_t zfb_size_in_byte; 719 enum frame_buffer_mode fb_mode; 720 bool dchub_initialzied; 721 bool dchub_info_valid; 722 }; 723 724 struct dc_init_data { 725 struct hw_asic_id asic_id; 726 void *driver; /* ctx */ 727 struct cgs_device *cgs_device; 728 struct dc_bounding_box_overrides bb_overrides; 729 730 int num_virtual_links; 731 /* 732 * If 'vbios_override' not NULL, it will be called instead 733 * of the real VBIOS. Intended use is Diagnostics on FPGA. 734 */ 735 struct dc_bios *vbios_override; 736 enum dce_environment dce_environment; 737 738 struct dmub_offload_funcs *dmub_if; 739 struct dc_reg_helper_state *dmub_offload; 740 741 struct dc_config flags; 742 uint64_t log_mask; 743 744 struct dpcd_vendor_signature vendor_signature; 745 #if defined(CONFIG_DRM_AMD_DC_DCN) 746 bool force_smu_not_present; 747 #endif 748 }; 749 750 struct dc_callback_init { 751 #ifdef CONFIG_DRM_AMD_DC_HDCP 752 struct cp_psp cp_psp; 753 #else 754 uint8_t reserved; 755 #endif 756 }; 757 758 struct dc *dc_create(const struct dc_init_data *init_params); 759 void dc_hardware_init(struct dc *dc); 760 761 int dc_get_vmid_use_vector(struct dc *dc); 762 void dc_setup_vm_context(struct dc *dc, struct dc_virtual_addr_space_config *va_config, int vmid); 763 /* Returns the number of vmids supported */ 764 int dc_setup_system_context(struct dc *dc, struct dc_phy_addr_space_config *pa_config); 765 void dc_init_callbacks(struct dc *dc, 766 const struct dc_callback_init *init_params); 767 void dc_deinit_callbacks(struct dc *dc); 768 void dc_destroy(struct dc **dc); 769 770 /******************************************************************************* 771 * Surface Interfaces 772 ******************************************************************************/ 773 774 enum { 775 TRANSFER_FUNC_POINTS = 1025 776 }; 777 778 struct dc_hdr_static_metadata { 779 /* display chromaticities and white point in units of 0.00001 */ 780 unsigned int chromaticity_green_x; 781 unsigned int chromaticity_green_y; 782 unsigned int chromaticity_blue_x; 783 unsigned int chromaticity_blue_y; 784 unsigned int chromaticity_red_x; 785 unsigned int chromaticity_red_y; 786 unsigned int chromaticity_white_point_x; 787 unsigned int chromaticity_white_point_y; 788 789 uint32_t min_luminance; 790 uint32_t max_luminance; 791 uint32_t maximum_content_light_level; 792 uint32_t maximum_frame_average_light_level; 793 }; 794 795 enum dc_transfer_func_type { 796 TF_TYPE_PREDEFINED, 797 TF_TYPE_DISTRIBUTED_POINTS, 798 TF_TYPE_BYPASS, 799 TF_TYPE_HWPWL 800 }; 801 802 struct dc_transfer_func_distributed_points { 803 struct fixed31_32 red[TRANSFER_FUNC_POINTS]; 804 struct fixed31_32 green[TRANSFER_FUNC_POINTS]; 805 struct fixed31_32 blue[TRANSFER_FUNC_POINTS]; 806 807 uint16_t end_exponent; 808 uint16_t x_point_at_y1_red; 809 uint16_t x_point_at_y1_green; 810 uint16_t x_point_at_y1_blue; 811 }; 812 813 enum dc_transfer_func_predefined { 814 TRANSFER_FUNCTION_SRGB, 815 TRANSFER_FUNCTION_BT709, 816 TRANSFER_FUNCTION_PQ, 817 TRANSFER_FUNCTION_LINEAR, 818 TRANSFER_FUNCTION_UNITY, 819 TRANSFER_FUNCTION_HLG, 820 TRANSFER_FUNCTION_HLG12, 821 TRANSFER_FUNCTION_GAMMA22, 822 TRANSFER_FUNCTION_GAMMA24, 823 TRANSFER_FUNCTION_GAMMA26 824 }; 825 826 827 struct dc_transfer_func { 828 struct kref refcount; 829 enum dc_transfer_func_type type; 830 enum dc_transfer_func_predefined tf; 831 /* FP16 1.0 reference level in nits, default is 80 nits, only for PQ*/ 832 uint32_t sdr_ref_white_level; 833 union { 834 struct pwl_params pwl; 835 struct dc_transfer_func_distributed_points tf_pts; 836 }; 837 }; 838 839 840 union dc_3dlut_state { 841 struct { 842 uint32_t initialized:1; /*if 3dlut is went through color module for initialization */ 843 uint32_t rmu_idx_valid:1; /*if mux settings are valid*/ 844 uint32_t rmu_mux_num:3; /*index of mux to use*/ 845 uint32_t mpc_rmu0_mux:4; /*select mpcc on mux, one of the following : mpcc0, mpcc1, mpcc2, mpcc3*/ 846 uint32_t mpc_rmu1_mux:4; 847 uint32_t mpc_rmu2_mux:4; 848 uint32_t reserved:15; 849 } bits; 850 uint32_t raw; 851 }; 852 853 854 struct dc_3dlut { 855 struct kref refcount; 856 struct tetrahedral_params lut_3d; 857 struct fixed31_32 hdr_multiplier; 858 union dc_3dlut_state state; 859 }; 860 /* 861 * This structure is filled in by dc_surface_get_status and contains 862 * the last requested address and the currently active address so the called 863 * can determine if there are any outstanding flips 864 */ 865 struct dc_plane_status { 866 struct dc_plane_address requested_address; 867 struct dc_plane_address current_address; 868 bool is_flip_pending; 869 bool is_right_eye; 870 }; 871 872 union surface_update_flags { 873 874 struct { 875 uint32_t addr_update:1; 876 /* Medium updates */ 877 uint32_t dcc_change:1; 878 uint32_t color_space_change:1; 879 uint32_t horizontal_mirror_change:1; 880 uint32_t per_pixel_alpha_change:1; 881 uint32_t global_alpha_change:1; 882 uint32_t hdr_mult:1; 883 uint32_t rotation_change:1; 884 uint32_t swizzle_change:1; 885 uint32_t scaling_change:1; 886 uint32_t position_change:1; 887 uint32_t in_transfer_func_change:1; 888 uint32_t input_csc_change:1; 889 uint32_t coeff_reduction_change:1; 890 uint32_t output_tf_change:1; 891 uint32_t pixel_format_change:1; 892 uint32_t plane_size_change:1; 893 uint32_t gamut_remap_change:1; 894 895 /* Full updates */ 896 uint32_t new_plane:1; 897 uint32_t bpp_change:1; 898 uint32_t gamma_change:1; 899 uint32_t bandwidth_change:1; 900 uint32_t clock_change:1; 901 uint32_t stereo_format_change:1; 902 uint32_t full_update:1; 903 } bits; 904 905 uint32_t raw; 906 }; 907 908 struct dc_plane_state { 909 struct dc_plane_address address; 910 struct dc_plane_flip_time time; 911 bool triplebuffer_flips; 912 struct scaling_taps scaling_quality; 913 struct rect src_rect; 914 struct rect dst_rect; 915 struct rect clip_rect; 916 917 struct plane_size plane_size; 918 union dc_tiling_info tiling_info; 919 920 struct dc_plane_dcc_param dcc; 921 922 struct dc_gamma *gamma_correction; 923 struct dc_transfer_func *in_transfer_func; 924 struct dc_bias_and_scale *bias_and_scale; 925 struct dc_csc_transform input_csc_color_matrix; 926 struct fixed31_32 coeff_reduction_factor; 927 struct fixed31_32 hdr_mult; 928 struct colorspace_transform gamut_remap_matrix; 929 930 // TODO: No longer used, remove 931 struct dc_hdr_static_metadata hdr_static_ctx; 932 933 enum dc_color_space color_space; 934 935 struct dc_3dlut *lut3d_func; 936 struct dc_transfer_func *in_shaper_func; 937 struct dc_transfer_func *blend_tf; 938 939 #if defined(CONFIG_DRM_AMD_DC_DCN) 940 struct dc_transfer_func *gamcor_tf; 941 #endif 942 enum surface_pixel_format format; 943 enum dc_rotation_angle rotation; 944 enum plane_stereo_format stereo_format; 945 946 bool is_tiling_rotated; 947 bool per_pixel_alpha; 948 bool global_alpha; 949 int global_alpha_value; 950 bool visible; 951 bool flip_immediate; 952 bool horizontal_mirror; 953 int layer_index; 954 955 union surface_update_flags update_flags; 956 bool flip_int_enabled; 957 bool skip_manual_trigger; 958 959 /* private to DC core */ 960 struct dc_plane_status status; 961 struct dc_context *ctx; 962 963 /* HACK: Workaround for forcing full reprogramming under some conditions */ 964 bool force_full_update; 965 966 /* private to dc_surface.c */ 967 enum dc_irq_source irq_source; 968 struct kref refcount; 969 }; 970 971 struct dc_plane_info { 972 struct plane_size plane_size; 973 union dc_tiling_info tiling_info; 974 struct dc_plane_dcc_param dcc; 975 enum surface_pixel_format format; 976 enum dc_rotation_angle rotation; 977 enum plane_stereo_format stereo_format; 978 enum dc_color_space color_space; 979 bool horizontal_mirror; 980 bool visible; 981 bool per_pixel_alpha; 982 bool global_alpha; 983 int global_alpha_value; 984 bool input_csc_enabled; 985 int layer_index; 986 }; 987 988 struct dc_scaling_info { 989 struct rect src_rect; 990 struct rect dst_rect; 991 struct rect clip_rect; 992 struct scaling_taps scaling_quality; 993 }; 994 995 struct dc_surface_update { 996 struct dc_plane_state *surface; 997 998 /* isr safe update parameters. null means no updates */ 999 const struct dc_flip_addrs *flip_addr; 1000 const struct dc_plane_info *plane_info; 1001 const struct dc_scaling_info *scaling_info; 1002 struct fixed31_32 hdr_mult; 1003 /* following updates require alloc/sleep/spin that is not isr safe, 1004 * null means no updates 1005 */ 1006 const struct dc_gamma *gamma; 1007 const struct dc_transfer_func *in_transfer_func; 1008 1009 const struct dc_csc_transform *input_csc_color_matrix; 1010 const struct fixed31_32 *coeff_reduction_factor; 1011 const struct dc_transfer_func *func_shaper; 1012 const struct dc_3dlut *lut3d_func; 1013 const struct dc_transfer_func *blend_tf; 1014 const struct colorspace_transform *gamut_remap_matrix; 1015 }; 1016 1017 /* 1018 * Create a new surface with default parameters; 1019 */ 1020 struct dc_plane_state *dc_create_plane_state(struct dc *dc); 1021 const struct dc_plane_status *dc_plane_get_status( 1022 const struct dc_plane_state *plane_state); 1023 1024 void dc_plane_state_retain(struct dc_plane_state *plane_state); 1025 void dc_plane_state_release(struct dc_plane_state *plane_state); 1026 1027 void dc_gamma_retain(struct dc_gamma *dc_gamma); 1028 void dc_gamma_release(struct dc_gamma **dc_gamma); 1029 struct dc_gamma *dc_create_gamma(void); 1030 1031 void dc_transfer_func_retain(struct dc_transfer_func *dc_tf); 1032 void dc_transfer_func_release(struct dc_transfer_func *dc_tf); 1033 struct dc_transfer_func *dc_create_transfer_func(void); 1034 1035 struct dc_3dlut *dc_create_3dlut_func(void); 1036 void dc_3dlut_func_release(struct dc_3dlut *lut); 1037 void dc_3dlut_func_retain(struct dc_3dlut *lut); 1038 /* 1039 * This structure holds a surface address. There could be multiple addresses 1040 * in cases such as Stereo 3D, Planar YUV, etc. Other per-flip attributes such 1041 * as frame durations and DCC format can also be set. 1042 */ 1043 struct dc_flip_addrs { 1044 struct dc_plane_address address; 1045 unsigned int flip_timestamp_in_us; 1046 bool flip_immediate; 1047 /* TODO: add flip duration for FreeSync */ 1048 bool triplebuffer_flips; 1049 }; 1050 1051 void dc_post_update_surfaces_to_stream( 1052 struct dc *dc); 1053 1054 #include "dc_stream.h" 1055 1056 /* 1057 * Structure to store surface/stream associations for validation 1058 */ 1059 struct dc_validation_set { 1060 struct dc_stream_state *stream; 1061 struct dc_plane_state *plane_states[MAX_SURFACES]; 1062 uint8_t plane_count; 1063 }; 1064 1065 bool dc_validate_seamless_boot_timing(const struct dc *dc, 1066 const struct dc_sink *sink, 1067 struct dc_crtc_timing *crtc_timing); 1068 1069 enum dc_status dc_validate_plane(struct dc *dc, const struct dc_plane_state *plane_state); 1070 1071 void get_clock_requirements_for_state(struct dc_state *state, struct AsicStateEx *info); 1072 1073 bool dc_set_generic_gpio_for_stereo(bool enable, 1074 struct gpio_service *gpio_service); 1075 1076 /* 1077 * fast_validate: we return after determining if we can support the new state, 1078 * but before we populate the programming info 1079 */ 1080 enum dc_status dc_validate_global_state( 1081 struct dc *dc, 1082 struct dc_state *new_ctx, 1083 bool fast_validate); 1084 1085 1086 void dc_resource_state_construct( 1087 const struct dc *dc, 1088 struct dc_state *dst_ctx); 1089 1090 #if defined(CONFIG_DRM_AMD_DC_DCN) 1091 bool dc_acquire_release_mpc_3dlut( 1092 struct dc *dc, bool acquire, 1093 struct dc_stream_state *stream, 1094 struct dc_3dlut **lut, 1095 struct dc_transfer_func **shaper); 1096 #endif 1097 1098 void dc_resource_state_copy_construct( 1099 const struct dc_state *src_ctx, 1100 struct dc_state *dst_ctx); 1101 1102 void dc_resource_state_copy_construct_current( 1103 const struct dc *dc, 1104 struct dc_state *dst_ctx); 1105 1106 void dc_resource_state_destruct(struct dc_state *context); 1107 1108 bool dc_resource_is_dsc_encoding_supported(const struct dc *dc); 1109 1110 /* 1111 * TODO update to make it about validation sets 1112 * Set up streams and links associated to drive sinks 1113 * The streams parameter is an absolute set of all active streams. 1114 * 1115 * After this call: 1116 * Phy, Encoder, Timing Generator are programmed and enabled. 1117 * New streams are enabled with blank stream; no memory read. 1118 */ 1119 bool dc_commit_state(struct dc *dc, struct dc_state *context); 1120 1121 struct dc_state *dc_create_state(struct dc *dc); 1122 struct dc_state *dc_copy_state(struct dc_state *src_ctx); 1123 void dc_retain_state(struct dc_state *context); 1124 void dc_release_state(struct dc_state *context); 1125 1126 /******************************************************************************* 1127 * Link Interfaces 1128 ******************************************************************************/ 1129 1130 struct dpcd_caps { 1131 union dpcd_rev dpcd_rev; 1132 union max_lane_count max_ln_count; 1133 union max_down_spread max_down_spread; 1134 union dprx_feature dprx_feature; 1135 1136 /* valid only for eDP v1.4 or higher*/ 1137 uint8_t edp_supported_link_rates_count; 1138 enum dc_link_rate edp_supported_link_rates[8]; 1139 1140 /* dongle type (DP converter, CV smart dongle) */ 1141 enum display_dongle_type dongle_type; 1142 /* branch device or sink device */ 1143 bool is_branch_dev; 1144 /* Dongle's downstream count. */ 1145 union sink_count sink_count; 1146 /* If dongle_type == DISPLAY_DONGLE_DP_HDMI_CONVERTER, 1147 indicates 'Frame Sequential-to-lllFrame Pack' conversion capability.*/ 1148 struct dc_dongle_caps dongle_caps; 1149 1150 uint32_t sink_dev_id; 1151 int8_t sink_dev_id_str[6]; 1152 int8_t sink_hw_revision; 1153 int8_t sink_fw_revision[2]; 1154 1155 uint32_t branch_dev_id; 1156 int8_t branch_dev_name[6]; 1157 int8_t branch_hw_revision; 1158 int8_t branch_fw_revision[2]; 1159 1160 bool allow_invalid_MSA_timing_param; 1161 bool panel_mode_edp; 1162 bool dpcd_display_control_capable; 1163 bool ext_receiver_cap_field_present; 1164 bool dynamic_backlight_capable_edp; 1165 union dpcd_fec_capability fec_cap; 1166 struct dpcd_dsc_capabilities dsc_caps; 1167 struct dc_lttpr_caps lttpr_caps; 1168 struct psr_caps psr_caps; 1169 1170 #if defined(CONFIG_DRM_AMD_DC_DCN) 1171 union dp_128b_132b_supported_link_rates dp_128b_132b_supported_link_rates; 1172 union dp_main_line_channel_coding_cap channel_coding_cap; 1173 union dp_sink_video_fallback_formats fallback_formats; 1174 union dp_fec_capability1 fec_cap1; 1175 #endif 1176 }; 1177 1178 union dpcd_sink_ext_caps { 1179 struct { 1180 /* 0 - Sink supports backlight adjust via PWM during SDR/HDR mode 1181 * 1 - Sink supports backlight adjust via AUX during SDR/HDR mode. 1182 */ 1183 uint8_t sdr_aux_backlight_control : 1; 1184 uint8_t hdr_aux_backlight_control : 1; 1185 uint8_t reserved_1 : 2; 1186 uint8_t oled : 1; 1187 uint8_t reserved : 3; 1188 } bits; 1189 uint8_t raw; 1190 }; 1191 1192 #if defined(CONFIG_DRM_AMD_DC_HDCP) 1193 union hdcp_rx_caps { 1194 struct { 1195 uint8_t version; 1196 uint8_t reserved; 1197 struct { 1198 uint8_t repeater : 1; 1199 uint8_t hdcp_capable : 1; 1200 uint8_t reserved : 6; 1201 } byte0; 1202 } fields; 1203 uint8_t raw[3]; 1204 }; 1205 1206 union hdcp_bcaps { 1207 struct { 1208 uint8_t HDCP_CAPABLE:1; 1209 uint8_t REPEATER:1; 1210 uint8_t RESERVED:6; 1211 } bits; 1212 uint8_t raw; 1213 }; 1214 1215 struct hdcp_caps { 1216 union hdcp_rx_caps rx_caps; 1217 union hdcp_bcaps bcaps; 1218 }; 1219 #endif 1220 1221 #include "dc_link.h" 1222 1223 #if defined(CONFIG_DRM_AMD_DC_DCN) 1224 uint32_t dc_get_opp_for_plane(struct dc *dc, struct dc_plane_state *plane); 1225 1226 #endif 1227 /******************************************************************************* 1228 * Sink Interfaces - A sink corresponds to a display output device 1229 ******************************************************************************/ 1230 1231 struct dc_container_id { 1232 // 128bit GUID in binary form 1233 unsigned char guid[16]; 1234 // 8 byte port ID -> ELD.PortID 1235 unsigned int portId[2]; 1236 // 128bit GUID in binary formufacturer name -> ELD.ManufacturerName 1237 unsigned short manufacturerName; 1238 // 2 byte product code -> ELD.ProductCode 1239 unsigned short productCode; 1240 }; 1241 1242 1243 struct dc_sink_dsc_caps { 1244 // 'true' if these are virtual DPCD's DSC caps (immediately upstream of sink in MST topology), 1245 // 'false' if they are sink's DSC caps 1246 bool is_virtual_dpcd_dsc; 1247 struct dsc_dec_dpcd_caps dsc_dec_caps; 1248 }; 1249 1250 struct dc_sink_fec_caps { 1251 bool is_rx_fec_supported; 1252 bool is_topology_fec_supported; 1253 }; 1254 1255 /* 1256 * The sink structure contains EDID and other display device properties 1257 */ 1258 struct dc_sink { 1259 enum signal_type sink_signal; 1260 struct dc_edid dc_edid; /* raw edid */ 1261 struct dc_edid_caps edid_caps; /* parse display caps */ 1262 struct dc_container_id *dc_container_id; 1263 uint32_t dongle_max_pix_clk; 1264 void *priv; 1265 struct stereo_3d_features features_3d[TIMING_3D_FORMAT_MAX]; 1266 bool converter_disable_audio; 1267 1268 struct dc_sink_dsc_caps dsc_caps; 1269 struct dc_sink_fec_caps fec_caps; 1270 1271 bool is_vsc_sdp_colorimetry_supported; 1272 1273 /* private to DC core */ 1274 struct dc_link *link; 1275 struct dc_context *ctx; 1276 1277 uint32_t sink_id; 1278 1279 /* private to dc_sink.c */ 1280 // refcount must be the last member in dc_sink, since we want the 1281 // sink structure to be logically cloneable up to (but not including) 1282 // refcount 1283 struct kref refcount; 1284 }; 1285 1286 void dc_sink_retain(struct dc_sink *sink); 1287 void dc_sink_release(struct dc_sink *sink); 1288 1289 struct dc_sink_init_data { 1290 enum signal_type sink_signal; 1291 struct dc_link *link; 1292 uint32_t dongle_max_pix_clk; 1293 bool converter_disable_audio; 1294 }; 1295 1296 struct dc_sink *dc_sink_create(const struct dc_sink_init_data *init_params); 1297 1298 /* Newer interfaces */ 1299 struct dc_cursor { 1300 struct dc_plane_address address; 1301 struct dc_cursor_attributes attributes; 1302 }; 1303 1304 1305 /******************************************************************************* 1306 * Interrupt interfaces 1307 ******************************************************************************/ 1308 enum dc_irq_source dc_interrupt_to_irq_source( 1309 struct dc *dc, 1310 uint32_t src_id, 1311 uint32_t ext_id); 1312 bool dc_interrupt_set(struct dc *dc, enum dc_irq_source src, bool enable); 1313 void dc_interrupt_ack(struct dc *dc, enum dc_irq_source src); 1314 enum dc_irq_source dc_get_hpd_irq_source_at_index( 1315 struct dc *dc, uint32_t link_index); 1316 1317 void dc_notify_vsync_int_state(struct dc *dc, struct dc_stream_state *stream, bool enable); 1318 1319 /******************************************************************************* 1320 * Power Interfaces 1321 ******************************************************************************/ 1322 1323 void dc_set_power_state( 1324 struct dc *dc, 1325 enum dc_acpi_cm_power_state power_state); 1326 void dc_resume(struct dc *dc); 1327 1328 void dc_power_down_on_boot(struct dc *dc); 1329 1330 #if defined(CONFIG_DRM_AMD_DC_HDCP) 1331 /* 1332 * HDCP Interfaces 1333 */ 1334 enum hdcp_message_status dc_process_hdcp_msg( 1335 enum signal_type signal, 1336 struct dc_link *link, 1337 struct hdcp_protection_message *message_info); 1338 #endif 1339 bool dc_is_dmcu_initialized(struct dc *dc); 1340 1341 enum dc_status dc_set_clock(struct dc *dc, enum dc_clock_type clock_type, uint32_t clk_khz, uint32_t stepping); 1342 void dc_get_clock(struct dc *dc, enum dc_clock_type clock_type, struct dc_clock_config *clock_cfg); 1343 #if defined(CONFIG_DRM_AMD_DC_DCN) 1344 1345 bool dc_is_plane_eligible_for_idle_optimizations(struct dc *dc, struct dc_plane_state *plane, 1346 struct dc_cursor_attributes *cursor_attr); 1347 1348 void dc_allow_idle_optimizations(struct dc *dc, bool allow); 1349 1350 /* 1351 * blank all streams, and set min and max memory clock to 1352 * lowest and highest DPM level, respectively 1353 */ 1354 void dc_unlock_memory_clock_frequency(struct dc *dc); 1355 1356 /* 1357 * set min memory clock to the min required for current mode, 1358 * max to maxDPM, and unblank streams 1359 */ 1360 void dc_lock_memory_clock_frequency(struct dc *dc); 1361 1362 /* cleanup on driver unload */ 1363 void dc_hardware_release(struct dc *dc); 1364 1365 #endif 1366 1367 bool dc_set_psr_allow_active(struct dc *dc, bool enable); 1368 #if defined(CONFIG_DRM_AMD_DC_DCN) 1369 void dc_z10_restore(const struct dc *dc); 1370 void dc_z10_save_init(struct dc *dc); 1371 #endif 1372 1373 bool dc_enable_dmub_notifications(struct dc *dc); 1374 1375 bool dc_process_dmub_aux_transfer_async(struct dc *dc, 1376 uint32_t link_index, 1377 struct aux_payload *payload); 1378 1379 /******************************************************************************* 1380 * DSC Interfaces 1381 ******************************************************************************/ 1382 #include "dc_dsc.h" 1383 1384 /******************************************************************************* 1385 * Disable acc mode Interfaces 1386 ******************************************************************************/ 1387 void dc_disable_accelerated_mode(struct dc *dc); 1388 1389 #endif /* DC_INTERFACE_H_ */ 1390