1 /* 2 * Copyright 2012-14 Advanced Micro Devices, Inc. 3 * 4 * Permission is hereby granted, free of charge, to any person obtaining a 5 * copy of this software and associated documentation files (the "Software"), 6 * to deal in the Software without restriction, including without limitation 7 * the rights to use, copy, modify, merge, publish, distribute, sublicense, 8 * and/or sell copies of the Software, and to permit persons to whom the 9 * Software is furnished to do so, subject to the following conditions: 10 * 11 * The above copyright notice and this permission notice shall be included in 12 * all copies or substantial portions of the Software. 13 * 14 * THE SOFTWARE IS PROVIDED "AS IS", WITHOUT WARRANTY OF ANY KIND, EXPRESS OR 15 * IMPLIED, INCLUDING BUT NOT LIMITED TO THE WARRANTIES OF MERCHANTABILITY, 16 * FITNESS FOR A PARTICULAR PURPOSE AND NONINFRINGEMENT. IN NO EVENT SHALL 17 * THE COPYRIGHT HOLDER(S) OR AUTHOR(S) BE LIABLE FOR ANY CLAIM, DAMAGES OR 18 * OTHER LIABILITY, WHETHER IN AN ACTION OF CONTRACT, TORT OR OTHERWISE, 19 * ARISING FROM, OUT OF OR IN CONNECTION WITH THE SOFTWARE OR THE USE OR 20 * OTHER DEALINGS IN THE SOFTWARE. 21 * 22 * Authors: AMD 23 * 24 */ 25 26 #ifndef DC_INTERFACE_H_ 27 #define DC_INTERFACE_H_ 28 29 #include "dc_types.h" 30 #include "grph_object_defs.h" 31 #include "logger_types.h" 32 #include "gpio_types.h" 33 #include "link_service_types.h" 34 #include "grph_object_ctrl_defs.h" 35 #include <inc/hw/opp.h> 36 37 #include "inc/hw_sequencer.h" 38 #include "inc/compressor.h" 39 #include "dml/display_mode_lib.h" 40 41 #define DC_VER "3.1.68" 42 43 #define MAX_SURFACES 3 44 #define MAX_STREAMS 6 45 #define MAX_SINKS_PER_LINK 4 46 47 /******************************************************************************* 48 * Display Core Interfaces 49 ******************************************************************************/ 50 struct dmcu_version { 51 unsigned int date; 52 unsigned int month; 53 unsigned int year; 54 unsigned int interface_version; 55 }; 56 57 struct dc_versions { 58 const char *dc_ver; 59 struct dmcu_version dmcu_version; 60 }; 61 62 struct dc_caps { 63 uint32_t max_streams; 64 uint32_t max_links; 65 uint32_t max_audios; 66 uint32_t max_slave_planes; 67 uint32_t max_planes; 68 uint32_t max_downscale_ratio; 69 uint32_t i2c_speed_in_khz; 70 uint32_t dmdata_alloc_size; 71 unsigned int max_cursor_size; 72 unsigned int max_video_width; 73 int linear_pitch_alignment; 74 bool dcc_const_color; 75 bool dynamic_audio; 76 bool is_apu; 77 bool dual_link_dvi; 78 bool post_blend_color_processing; 79 bool force_dp_tps4_for_cp2520; 80 bool disable_dp_clk_share; 81 bool psp_setup_panel_mode; 82 }; 83 84 struct dc_dcc_surface_param { 85 struct dc_size surface_size; 86 enum surface_pixel_format format; 87 enum swizzle_mode_values swizzle_mode; 88 enum dc_scan_direction scan; 89 }; 90 91 struct dc_dcc_setting { 92 unsigned int max_compressed_blk_size; 93 unsigned int max_uncompressed_blk_size; 94 bool independent_64b_blks; 95 }; 96 97 struct dc_surface_dcc_cap { 98 union { 99 struct { 100 struct dc_dcc_setting rgb; 101 } grph; 102 103 struct { 104 struct dc_dcc_setting luma; 105 struct dc_dcc_setting chroma; 106 } video; 107 }; 108 109 bool capable; 110 bool const_color_support; 111 }; 112 113 struct dc_static_screen_events { 114 bool force_trigger; 115 bool cursor_update; 116 bool surface_update; 117 bool overlay_update; 118 }; 119 120 121 /* Surface update type is used by dc_update_surfaces_and_stream 122 * The update type is determined at the very beginning of the function based 123 * on parameters passed in and decides how much programming (or updating) is 124 * going to be done during the call. 125 * 126 * UPDATE_TYPE_FAST is used for really fast updates that do not require much 127 * logical calculations or hardware register programming. This update MUST be 128 * ISR safe on windows. Currently fast update will only be used to flip surface 129 * address. 130 * 131 * UPDATE_TYPE_MED is used for slower updates which require significant hw 132 * re-programming however do not affect bandwidth consumption or clock 133 * requirements. At present, this is the level at which front end updates 134 * that do not require us to run bw_calcs happen. These are in/out transfer func 135 * updates, viewport offset changes, recout size changes and pixel depth changes. 136 * This update can be done at ISR, but we want to minimize how often this happens. 137 * 138 * UPDATE_TYPE_FULL is slow. Really slow. This requires us to recalculate our 139 * bandwidth and clocks, possibly rearrange some pipes and reprogram anything front 140 * end related. Any time viewport dimensions, recout dimensions, scaling ratios or 141 * gamma need to be adjusted or pipe needs to be turned on (or disconnected) we do 142 * a full update. This cannot be done at ISR level and should be a rare event. 143 * Unless someone is stress testing mpo enter/exit, playing with colour or adjusting 144 * underscan we don't expect to see this call at all. 145 */ 146 147 enum surface_update_type { 148 UPDATE_TYPE_FAST, /* super fast, safe to execute in isr */ 149 UPDATE_TYPE_MED, /* ISR safe, most of programming needed, no bw/clk change*/ 150 UPDATE_TYPE_FULL, /* may need to shuffle resources */ 151 }; 152 153 /* Forward declaration*/ 154 struct dc; 155 struct dc_plane_state; 156 struct dc_state; 157 158 159 struct dc_cap_funcs { 160 bool (*get_dcc_compression_cap)(const struct dc *dc, 161 const struct dc_dcc_surface_param *input, 162 struct dc_surface_dcc_cap *output); 163 }; 164 165 struct link_training_settings; 166 167 168 /* Structure to hold configuration flags set by dm at dc creation. */ 169 struct dc_config { 170 bool gpu_vm_support; 171 bool disable_disp_pll_sharing; 172 bool fbc_support; 173 }; 174 175 enum visual_confirm { 176 VISUAL_CONFIRM_DISABLE = 0, 177 VISUAL_CONFIRM_SURFACE = 1, 178 VISUAL_CONFIRM_HDR = 2, 179 }; 180 181 enum dcc_option { 182 DCC_ENABLE = 0, 183 DCC_DISABLE = 1, 184 DCC_HALF_REQ_DISALBE = 2, 185 }; 186 187 enum pipe_split_policy { 188 MPC_SPLIT_DYNAMIC = 0, 189 MPC_SPLIT_AVOID = 1, 190 MPC_SPLIT_AVOID_MULT_DISP = 2, 191 }; 192 193 enum wm_report_mode { 194 WM_REPORT_DEFAULT = 0, 195 WM_REPORT_OVERRIDE = 1, 196 }; 197 198 /* 199 * For any clocks that may differ per pipe 200 * only the max is stored in this structure 201 */ 202 struct dc_clocks { 203 int dispclk_khz; 204 int max_supported_dppclk_khz; 205 int dppclk_khz; 206 int dcfclk_khz; 207 int socclk_khz; 208 int dcfclk_deep_sleep_khz; 209 int fclk_khz; 210 int phyclk_khz; 211 int dramclk_khz; 212 }; 213 214 struct dc_debug_options { 215 enum visual_confirm visual_confirm; 216 bool sanity_checks; 217 bool max_disp_clk; 218 bool surface_trace; 219 bool timing_trace; 220 bool clock_trace; 221 bool validation_trace; 222 bool bandwidth_calcs_trace; 223 int max_downscale_src_width; 224 225 /* stutter efficiency related */ 226 bool disable_stutter; 227 bool use_max_lb; 228 enum dcc_option disable_dcc; 229 enum pipe_split_policy pipe_split_policy; 230 bool force_single_disp_pipe_split; 231 bool voltage_align_fclk; 232 233 bool disable_dfs_bypass; 234 bool disable_dpp_power_gate; 235 bool disable_hubp_power_gate; 236 bool disable_pplib_wm_range; 237 enum wm_report_mode pplib_wm_report_mode; 238 unsigned int min_disp_clk_khz; 239 int sr_exit_time_dpm0_ns; 240 int sr_enter_plus_exit_time_dpm0_ns; 241 int sr_exit_time_ns; 242 int sr_enter_plus_exit_time_ns; 243 int urgent_latency_ns; 244 int percent_of_ideal_drambw; 245 int dram_clock_change_latency_ns; 246 bool optimized_watermark; 247 int always_scale; 248 bool disable_pplib_clock_request; 249 bool disable_clock_gate; 250 bool disable_dmcu; 251 bool disable_psr; 252 bool force_abm_enable; 253 bool disable_hbup_pg; 254 bool disable_dpp_pg; 255 bool disable_stereo_support; 256 bool vsr_support; 257 bool performance_trace; 258 bool az_endpoint_mute_only; 259 bool always_use_regamma; 260 bool p010_mpo_support; 261 bool recovery_enabled; 262 bool avoid_vbios_exec_table; 263 bool scl_reset_length10; 264 bool hdmi20_disable; 265 bool skip_detection_link_training; 266 }; 267 268 struct dc_debug_data { 269 uint32_t ltFailCount; 270 uint32_t i2cErrorCount; 271 uint32_t auxErrorCount; 272 }; 273 274 275 struct dc_state; 276 struct resource_pool; 277 struct dce_hwseq; 278 struct dc { 279 struct dc_versions versions; 280 struct dc_caps caps; 281 struct dc_cap_funcs cap_funcs; 282 struct dc_config config; 283 struct dc_debug_options debug; 284 struct dc_context *ctx; 285 286 uint8_t link_count; 287 struct dc_link *links[MAX_PIPES * 2]; 288 289 struct dc_state *current_state; 290 struct resource_pool *res_pool; 291 292 /* Display Engine Clock levels */ 293 struct dm_pp_clock_levels sclk_lvls; 294 295 /* Inputs into BW and WM calculations. */ 296 struct bw_calcs_dceip *bw_dceip; 297 struct bw_calcs_vbios *bw_vbios; 298 #ifdef CONFIG_DRM_AMD_DC_DCN1_0 299 struct dcn_soc_bounding_box *dcn_soc; 300 struct dcn_ip_params *dcn_ip; 301 struct display_mode_lib dml; 302 #endif 303 304 /* HW functions */ 305 struct hw_sequencer_funcs hwss; 306 struct dce_hwseq *hwseq; 307 308 /* temp store of dm_pp_display_configuration 309 * to compare to see if display config changed 310 */ 311 struct dm_pp_display_configuration prev_display_config; 312 313 bool optimized_required; 314 315 /* FBC compressor */ 316 struct compressor *fbc_compressor; 317 318 struct dc_debug_data debug_data; 319 320 const char *build_id; 321 }; 322 323 enum frame_buffer_mode { 324 FRAME_BUFFER_MODE_LOCAL_ONLY = 0, 325 FRAME_BUFFER_MODE_ZFB_ONLY, 326 FRAME_BUFFER_MODE_MIXED_ZFB_AND_LOCAL, 327 } ; 328 329 struct dchub_init_data { 330 int64_t zfb_phys_addr_base; 331 int64_t zfb_mc_base_addr; 332 uint64_t zfb_size_in_byte; 333 enum frame_buffer_mode fb_mode; 334 bool dchub_initialzied; 335 bool dchub_info_valid; 336 }; 337 338 struct dc_init_data { 339 struct hw_asic_id asic_id; 340 void *driver; /* ctx */ 341 struct cgs_device *cgs_device; 342 343 int num_virtual_links; 344 /* 345 * If 'vbios_override' not NULL, it will be called instead 346 * of the real VBIOS. Intended use is Diagnostics on FPGA. 347 */ 348 struct dc_bios *vbios_override; 349 enum dce_environment dce_environment; 350 351 struct dc_config flags; 352 uint32_t log_mask; 353 }; 354 355 struct dc *dc_create(const struct dc_init_data *init_params); 356 357 void dc_destroy(struct dc **dc); 358 359 /******************************************************************************* 360 * Surface Interfaces 361 ******************************************************************************/ 362 363 enum { 364 TRANSFER_FUNC_POINTS = 1025 365 }; 366 367 struct dc_hdr_static_metadata { 368 /* display chromaticities and white point in units of 0.00001 */ 369 unsigned int chromaticity_green_x; 370 unsigned int chromaticity_green_y; 371 unsigned int chromaticity_blue_x; 372 unsigned int chromaticity_blue_y; 373 unsigned int chromaticity_red_x; 374 unsigned int chromaticity_red_y; 375 unsigned int chromaticity_white_point_x; 376 unsigned int chromaticity_white_point_y; 377 378 uint32_t min_luminance; 379 uint32_t max_luminance; 380 uint32_t maximum_content_light_level; 381 uint32_t maximum_frame_average_light_level; 382 }; 383 384 enum dc_transfer_func_type { 385 TF_TYPE_PREDEFINED, 386 TF_TYPE_DISTRIBUTED_POINTS, 387 TF_TYPE_BYPASS, 388 TF_TYPE_HWPWL 389 }; 390 391 struct dc_transfer_func_distributed_points { 392 struct fixed31_32 red[TRANSFER_FUNC_POINTS]; 393 struct fixed31_32 green[TRANSFER_FUNC_POINTS]; 394 struct fixed31_32 blue[TRANSFER_FUNC_POINTS]; 395 396 uint16_t end_exponent; 397 uint16_t x_point_at_y1_red; 398 uint16_t x_point_at_y1_green; 399 uint16_t x_point_at_y1_blue; 400 }; 401 402 enum dc_transfer_func_predefined { 403 TRANSFER_FUNCTION_SRGB, 404 TRANSFER_FUNCTION_BT709, 405 TRANSFER_FUNCTION_PQ, 406 TRANSFER_FUNCTION_LINEAR, 407 TRANSFER_FUNCTION_UNITY, 408 TRANSFER_FUNCTION_HLG, 409 TRANSFER_FUNCTION_HLG12, 410 TRANSFER_FUNCTION_GAMMA22 411 }; 412 413 struct dc_transfer_func { 414 struct kref refcount; 415 enum dc_transfer_func_type type; 416 enum dc_transfer_func_predefined tf; 417 /* FP16 1.0 reference level in nits, default is 80 nits, only for PQ*/ 418 uint32_t sdr_ref_white_level; 419 struct dc_context *ctx; 420 union { 421 struct pwl_params pwl; 422 struct dc_transfer_func_distributed_points tf_pts; 423 }; 424 }; 425 426 /* 427 * This structure is filled in by dc_surface_get_status and contains 428 * the last requested address and the currently active address so the called 429 * can determine if there are any outstanding flips 430 */ 431 struct dc_plane_status { 432 struct dc_plane_address requested_address; 433 struct dc_plane_address current_address; 434 bool is_flip_pending; 435 bool is_right_eye; 436 }; 437 438 union surface_update_flags { 439 440 struct { 441 /* Medium updates */ 442 uint32_t dcc_change:1; 443 uint32_t color_space_change:1; 444 uint32_t horizontal_mirror_change:1; 445 uint32_t per_pixel_alpha_change:1; 446 uint32_t global_alpha_change:1; 447 uint32_t rotation_change:1; 448 uint32_t swizzle_change:1; 449 uint32_t scaling_change:1; 450 uint32_t position_change:1; 451 uint32_t in_transfer_func_change:1; 452 uint32_t input_csc_change:1; 453 uint32_t coeff_reduction_change:1; 454 uint32_t output_tf_change:1; 455 uint32_t pixel_format_change:1; 456 457 /* Full updates */ 458 uint32_t new_plane:1; 459 uint32_t bpp_change:1; 460 uint32_t gamma_change:1; 461 uint32_t bandwidth_change:1; 462 uint32_t clock_change:1; 463 uint32_t stereo_format_change:1; 464 uint32_t full_update:1; 465 } bits; 466 467 uint32_t raw; 468 }; 469 470 struct dc_plane_state { 471 struct dc_plane_address address; 472 struct dc_plane_flip_time time; 473 struct scaling_taps scaling_quality; 474 struct rect src_rect; 475 struct rect dst_rect; 476 struct rect clip_rect; 477 478 union plane_size plane_size; 479 union dc_tiling_info tiling_info; 480 481 struct dc_plane_dcc_param dcc; 482 483 struct dc_gamma *gamma_correction; 484 struct dc_transfer_func *in_transfer_func; 485 struct dc_bias_and_scale *bias_and_scale; 486 struct dc_csc_transform input_csc_color_matrix; 487 struct fixed31_32 coeff_reduction_factor; 488 uint32_t sdr_white_level; 489 490 // TODO: No longer used, remove 491 struct dc_hdr_static_metadata hdr_static_ctx; 492 493 enum dc_color_space color_space; 494 495 enum surface_pixel_format format; 496 enum dc_rotation_angle rotation; 497 enum plane_stereo_format stereo_format; 498 499 bool is_tiling_rotated; 500 bool per_pixel_alpha; 501 bool global_alpha; 502 int global_alpha_value; 503 bool visible; 504 bool flip_immediate; 505 bool horizontal_mirror; 506 507 union surface_update_flags update_flags; 508 /* private to DC core */ 509 struct dc_plane_status status; 510 struct dc_context *ctx; 511 512 /* private to dc_surface.c */ 513 enum dc_irq_source irq_source; 514 struct kref refcount; 515 }; 516 517 struct dc_plane_info { 518 union plane_size plane_size; 519 union dc_tiling_info tiling_info; 520 struct dc_plane_dcc_param dcc; 521 enum surface_pixel_format format; 522 enum dc_rotation_angle rotation; 523 enum plane_stereo_format stereo_format; 524 enum dc_color_space color_space; 525 unsigned int sdr_white_level; 526 bool horizontal_mirror; 527 bool visible; 528 bool per_pixel_alpha; 529 bool global_alpha; 530 int global_alpha_value; 531 bool input_csc_enabled; 532 }; 533 534 struct dc_scaling_info { 535 struct rect src_rect; 536 struct rect dst_rect; 537 struct rect clip_rect; 538 struct scaling_taps scaling_quality; 539 }; 540 541 struct dc_surface_update { 542 struct dc_plane_state *surface; 543 544 /* isr safe update parameters. null means no updates */ 545 const struct dc_flip_addrs *flip_addr; 546 const struct dc_plane_info *plane_info; 547 const struct dc_scaling_info *scaling_info; 548 549 /* following updates require alloc/sleep/spin that is not isr safe, 550 * null means no updates 551 */ 552 const struct dc_gamma *gamma; 553 const struct dc_transfer_func *in_transfer_func; 554 555 const struct dc_csc_transform *input_csc_color_matrix; 556 const struct fixed31_32 *coeff_reduction_factor; 557 }; 558 559 /* 560 * Create a new surface with default parameters; 561 */ 562 struct dc_plane_state *dc_create_plane_state(struct dc *dc); 563 const struct dc_plane_status *dc_plane_get_status( 564 const struct dc_plane_state *plane_state); 565 566 void dc_plane_state_retain(struct dc_plane_state *plane_state); 567 void dc_plane_state_release(struct dc_plane_state *plane_state); 568 569 void dc_gamma_retain(struct dc_gamma *dc_gamma); 570 void dc_gamma_release(struct dc_gamma **dc_gamma); 571 struct dc_gamma *dc_create_gamma(void); 572 573 void dc_transfer_func_retain(struct dc_transfer_func *dc_tf); 574 void dc_transfer_func_release(struct dc_transfer_func *dc_tf); 575 struct dc_transfer_func *dc_create_transfer_func(void); 576 577 /* 578 * This structure holds a surface address. There could be multiple addresses 579 * in cases such as Stereo 3D, Planar YUV, etc. Other per-flip attributes such 580 * as frame durations and DCC format can also be set. 581 */ 582 struct dc_flip_addrs { 583 struct dc_plane_address address; 584 unsigned int flip_timestamp_in_us; 585 bool flip_immediate; 586 /* TODO: add flip duration for FreeSync */ 587 }; 588 589 bool dc_post_update_surfaces_to_stream( 590 struct dc *dc); 591 592 #include "dc_stream.h" 593 594 /* 595 * Structure to store surface/stream associations for validation 596 */ 597 struct dc_validation_set { 598 struct dc_stream_state *stream; 599 struct dc_plane_state *plane_states[MAX_SURFACES]; 600 uint8_t plane_count; 601 }; 602 603 enum dc_status dc_validate_plane(struct dc *dc, const struct dc_plane_state *plane_state); 604 605 void get_clock_requirements_for_state(struct dc_state *state, struct AsicStateEx *info); 606 607 enum dc_status dc_validate_global_state( 608 struct dc *dc, 609 struct dc_state *new_ctx); 610 611 612 void dc_resource_state_construct( 613 const struct dc *dc, 614 struct dc_state *dst_ctx); 615 616 void dc_resource_state_copy_construct( 617 const struct dc_state *src_ctx, 618 struct dc_state *dst_ctx); 619 620 void dc_resource_state_copy_construct_current( 621 const struct dc *dc, 622 struct dc_state *dst_ctx); 623 624 void dc_resource_state_destruct(struct dc_state *context); 625 626 /* 627 * TODO update to make it about validation sets 628 * Set up streams and links associated to drive sinks 629 * The streams parameter is an absolute set of all active streams. 630 * 631 * After this call: 632 * Phy, Encoder, Timing Generator are programmed and enabled. 633 * New streams are enabled with blank stream; no memory read. 634 */ 635 bool dc_commit_state(struct dc *dc, struct dc_state *context); 636 637 638 struct dc_state *dc_create_state(void); 639 void dc_retain_state(struct dc_state *context); 640 void dc_release_state(struct dc_state *context); 641 642 /******************************************************************************* 643 * Link Interfaces 644 ******************************************************************************/ 645 646 struct dpcd_caps { 647 union dpcd_rev dpcd_rev; 648 union max_lane_count max_ln_count; 649 union max_down_spread max_down_spread; 650 651 /* dongle type (DP converter, CV smart dongle) */ 652 enum display_dongle_type dongle_type; 653 /* Dongle's downstream count. */ 654 union sink_count sink_count; 655 /* If dongle_type == DISPLAY_DONGLE_DP_HDMI_CONVERTER, 656 indicates 'Frame Sequential-to-lllFrame Pack' conversion capability.*/ 657 struct dc_dongle_caps dongle_caps; 658 659 uint32_t sink_dev_id; 660 int8_t sink_dev_id_str[6]; 661 int8_t sink_hw_revision; 662 int8_t sink_fw_revision[2]; 663 664 uint32_t branch_dev_id; 665 int8_t branch_dev_name[6]; 666 int8_t branch_hw_revision; 667 int8_t branch_fw_revision[2]; 668 669 bool allow_invalid_MSA_timing_param; 670 bool panel_mode_edp; 671 bool dpcd_display_control_capable; 672 }; 673 674 #include "dc_link.h" 675 676 /******************************************************************************* 677 * Sink Interfaces - A sink corresponds to a display output device 678 ******************************************************************************/ 679 680 struct dc_container_id { 681 // 128bit GUID in binary form 682 unsigned char guid[16]; 683 // 8 byte port ID -> ELD.PortID 684 unsigned int portId[2]; 685 // 128bit GUID in binary formufacturer name -> ELD.ManufacturerName 686 unsigned short manufacturerName; 687 // 2 byte product code -> ELD.ProductCode 688 unsigned short productCode; 689 }; 690 691 692 693 /* 694 * The sink structure contains EDID and other display device properties 695 */ 696 struct dc_sink { 697 enum signal_type sink_signal; 698 struct dc_edid dc_edid; /* raw edid */ 699 struct dc_edid_caps edid_caps; /* parse display caps */ 700 struct dc_container_id *dc_container_id; 701 uint32_t dongle_max_pix_clk; 702 void *priv; 703 struct stereo_3d_features features_3d[TIMING_3D_FORMAT_MAX]; 704 bool converter_disable_audio; 705 706 /* private to DC core */ 707 struct dc_link *link; 708 struct dc_context *ctx; 709 710 uint32_t sink_id; 711 712 /* private to dc_sink.c */ 713 // refcount must be the last member in dc_sink, since we want the 714 // sink structure to be logically cloneable up to (but not including) 715 // refcount 716 struct kref refcount; 717 }; 718 719 void dc_sink_retain(struct dc_sink *sink); 720 void dc_sink_release(struct dc_sink *sink); 721 722 struct dc_sink_init_data { 723 enum signal_type sink_signal; 724 struct dc_link *link; 725 uint32_t dongle_max_pix_clk; 726 bool converter_disable_audio; 727 }; 728 729 struct dc_sink *dc_sink_create(const struct dc_sink_init_data *init_params); 730 731 /* Newer interfaces */ 732 struct dc_cursor { 733 struct dc_plane_address address; 734 struct dc_cursor_attributes attributes; 735 }; 736 737 738 /******************************************************************************* 739 * Interrupt interfaces 740 ******************************************************************************/ 741 enum dc_irq_source dc_interrupt_to_irq_source( 742 struct dc *dc, 743 uint32_t src_id, 744 uint32_t ext_id); 745 bool dc_interrupt_set(struct dc *dc, enum dc_irq_source src, bool enable); 746 void dc_interrupt_ack(struct dc *dc, enum dc_irq_source src); 747 enum dc_irq_source dc_get_hpd_irq_source_at_index( 748 struct dc *dc, uint32_t link_index); 749 750 /******************************************************************************* 751 * Power Interfaces 752 ******************************************************************************/ 753 754 void dc_set_power_state( 755 struct dc *dc, 756 enum dc_acpi_cm_power_state power_state); 757 void dc_resume(struct dc *dc); 758 759 #endif /* DC_INTERFACE_H_ */ 760