1 /* 2 * Copyright 2012-15 Advanced Micro Devices, Inc. 3 * 4 * Permission is hereby granted, free of charge, to any person obtaining a 5 * copy of this software and associated documentation files (the "Software"), 6 * to deal in the Software without restriction, including without limitation 7 * the rights to use, copy, modify, merge, publish, distribute, sublicense, 8 * and/or sell copies of the Software, and to permit persons to whom the 9 * Software is furnished to do so, subject to the following conditions: 10 * 11 * The above copyright notice and this permission notice shall be included in 12 * all copies or substantial portions of the Software. 13 * 14 * THE SOFTWARE IS PROVIDED "AS IS", WITHOUT WARRANTY OF ANY KIND, EXPRESS OR 15 * IMPLIED, INCLUDING BUT NOT LIMITED TO THE WARRANTIES OF MERCHANTABILITY, 16 * FITNESS FOR A PARTICULAR PURPOSE AND NONINFRINGEMENT. IN NO EVENT SHALL 17 * THE COPYRIGHT HOLDER(S) OR AUTHOR(S) BE LIABLE FOR ANY CLAIM, DAMAGES OR 18 * OTHER LIABILITY, WHETHER IN AN ACTION OF CONTRACT, TORT OR OTHERWISE, 19 * ARISING FROM, OUT OF OR IN CONNECTION WITH THE SOFTWARE OR THE USE OR 20 * OTHER DEALINGS IN THE SOFTWARE. 21 * 22 * Authors: AMD 23 * 24 */ 25 26 #include <linux/delay.h> 27 #include <linux/slab.h> 28 29 #include "dm_services.h" 30 #include "basics/dc_common.h" 31 #include "dc.h" 32 #include "core_types.h" 33 #include "resource.h" 34 #include "ipp.h" 35 #include "timing_generator.h" 36 37 #define DC_LOGGER dc->ctx->logger 38 39 /******************************************************************************* 40 * Private functions 41 ******************************************************************************/ 42 void update_stream_signal(struct dc_stream_state *stream, struct dc_sink *sink) 43 { 44 if (sink->sink_signal == SIGNAL_TYPE_NONE) 45 stream->signal = stream->link->connector_signal; 46 else 47 stream->signal = sink->sink_signal; 48 49 if (dc_is_dvi_signal(stream->signal)) { 50 if (stream->ctx->dc->caps.dual_link_dvi && 51 (stream->timing.pix_clk_100hz / 10) > TMDS_MAX_PIXEL_CLOCK && 52 sink->sink_signal != SIGNAL_TYPE_DVI_SINGLE_LINK) 53 stream->signal = SIGNAL_TYPE_DVI_DUAL_LINK; 54 else 55 stream->signal = SIGNAL_TYPE_DVI_SINGLE_LINK; 56 } 57 } 58 59 static bool dc_stream_construct(struct dc_stream_state *stream, 60 struct dc_sink *dc_sink_data) 61 { 62 uint32_t i = 0; 63 64 stream->sink = dc_sink_data; 65 dc_sink_retain(dc_sink_data); 66 67 stream->ctx = dc_sink_data->ctx; 68 stream->link = dc_sink_data->link; 69 stream->sink_patches = dc_sink_data->edid_caps.panel_patch; 70 stream->converter_disable_audio = dc_sink_data->converter_disable_audio; 71 stream->qs_bit = dc_sink_data->edid_caps.qs_bit; 72 stream->qy_bit = dc_sink_data->edid_caps.qy_bit; 73 74 /* Copy audio modes */ 75 /* TODO - Remove this translation */ 76 for (i = 0; i < (dc_sink_data->edid_caps.audio_mode_count); i++) 77 { 78 stream->audio_info.modes[i].channel_count = dc_sink_data->edid_caps.audio_modes[i].channel_count; 79 stream->audio_info.modes[i].format_code = dc_sink_data->edid_caps.audio_modes[i].format_code; 80 stream->audio_info.modes[i].sample_rates.all = dc_sink_data->edid_caps.audio_modes[i].sample_rate; 81 stream->audio_info.modes[i].sample_size = dc_sink_data->edid_caps.audio_modes[i].sample_size; 82 } 83 stream->audio_info.mode_count = dc_sink_data->edid_caps.audio_mode_count; 84 stream->audio_info.audio_latency = dc_sink_data->edid_caps.audio_latency; 85 stream->audio_info.video_latency = dc_sink_data->edid_caps.video_latency; 86 memmove( 87 stream->audio_info.display_name, 88 dc_sink_data->edid_caps.display_name, 89 AUDIO_INFO_DISPLAY_NAME_SIZE_IN_CHARS); 90 stream->audio_info.manufacture_id = dc_sink_data->edid_caps.manufacturer_id; 91 stream->audio_info.product_id = dc_sink_data->edid_caps.product_id; 92 stream->audio_info.flags.all = dc_sink_data->edid_caps.speaker_flags; 93 94 if (dc_sink_data->dc_container_id != NULL) { 95 struct dc_container_id *dc_container_id = dc_sink_data->dc_container_id; 96 97 stream->audio_info.port_id[0] = dc_container_id->portId[0]; 98 stream->audio_info.port_id[1] = dc_container_id->portId[1]; 99 } else { 100 /* TODO - WindowDM has implemented, 101 other DMs need Unhardcode port_id */ 102 stream->audio_info.port_id[0] = 0x5558859e; 103 stream->audio_info.port_id[1] = 0xd989449; 104 } 105 106 /* EDID CAP translation for HDMI 2.0 */ 107 stream->timing.flags.LTE_340MCSC_SCRAMBLE = dc_sink_data->edid_caps.lte_340mcsc_scramble; 108 109 memset(&stream->timing.dsc_cfg, 0, sizeof(stream->timing.dsc_cfg)); 110 stream->timing.dsc_cfg.num_slices_h = 0; 111 stream->timing.dsc_cfg.num_slices_v = 0; 112 stream->timing.dsc_cfg.bits_per_pixel = 128; 113 stream->timing.dsc_cfg.block_pred_enable = 1; 114 stream->timing.dsc_cfg.linebuf_depth = 9; 115 stream->timing.dsc_cfg.version_minor = 2; 116 stream->timing.dsc_cfg.ycbcr422_simple = 0; 117 118 update_stream_signal(stream, dc_sink_data); 119 120 stream->out_transfer_func = dc_create_transfer_func(); 121 if (stream->out_transfer_func == NULL) { 122 dc_sink_release(dc_sink_data); 123 return false; 124 } 125 stream->out_transfer_func->type = TF_TYPE_BYPASS; 126 127 stream->stream_id = stream->ctx->dc_stream_id_count; 128 stream->ctx->dc_stream_id_count++; 129 130 return true; 131 } 132 133 static void dc_stream_destruct(struct dc_stream_state *stream) 134 { 135 dc_sink_release(stream->sink); 136 if (stream->out_transfer_func != NULL) { 137 dc_transfer_func_release(stream->out_transfer_func); 138 stream->out_transfer_func = NULL; 139 } 140 } 141 142 void dc_stream_retain(struct dc_stream_state *stream) 143 { 144 kref_get(&stream->refcount); 145 } 146 147 static void dc_stream_free(struct kref *kref) 148 { 149 struct dc_stream_state *stream = container_of(kref, struct dc_stream_state, refcount); 150 151 dc_stream_destruct(stream); 152 kfree(stream); 153 } 154 155 void dc_stream_release(struct dc_stream_state *stream) 156 { 157 if (stream != NULL) { 158 kref_put(&stream->refcount, dc_stream_free); 159 } 160 } 161 162 struct dc_stream_state *dc_create_stream_for_sink( 163 struct dc_sink *sink) 164 { 165 struct dc_stream_state *stream; 166 167 if (sink == NULL) 168 return NULL; 169 170 stream = kzalloc(sizeof(struct dc_stream_state), GFP_KERNEL); 171 if (stream == NULL) 172 goto alloc_fail; 173 174 if (dc_stream_construct(stream, sink) == false) 175 goto construct_fail; 176 177 kref_init(&stream->refcount); 178 179 return stream; 180 181 construct_fail: 182 kfree(stream); 183 184 alloc_fail: 185 return NULL; 186 } 187 188 struct dc_stream_state *dc_copy_stream(const struct dc_stream_state *stream) 189 { 190 struct dc_stream_state *new_stream; 191 192 new_stream = kmemdup(stream, sizeof(struct dc_stream_state), GFP_KERNEL); 193 if (!new_stream) 194 return NULL; 195 196 if (new_stream->sink) 197 dc_sink_retain(new_stream->sink); 198 199 if (new_stream->out_transfer_func) 200 dc_transfer_func_retain(new_stream->out_transfer_func); 201 202 new_stream->stream_id = new_stream->ctx->dc_stream_id_count; 203 new_stream->ctx->dc_stream_id_count++; 204 205 kref_init(&new_stream->refcount); 206 207 return new_stream; 208 } 209 210 /** 211 * dc_stream_get_status_from_state - Get stream status from given dc state 212 * @state: DC state to find the stream status in 213 * @stream: The stream to get the stream status for 214 * 215 * The given stream is expected to exist in the given dc state. Otherwise, NULL 216 * will be returned. 217 */ 218 struct dc_stream_status *dc_stream_get_status_from_state( 219 struct dc_state *state, 220 struct dc_stream_state *stream) 221 { 222 uint8_t i; 223 224 if (state == NULL) 225 return NULL; 226 227 for (i = 0; i < state->stream_count; i++) { 228 if (stream == state->streams[i]) 229 return &state->stream_status[i]; 230 } 231 232 return NULL; 233 } 234 235 /** 236 * dc_stream_get_status() - Get current stream status of the given stream state 237 * @stream: The stream to get the stream status for. 238 * 239 * The given stream is expected to exist in dc->current_state. Otherwise, NULL 240 * will be returned. 241 */ 242 struct dc_stream_status *dc_stream_get_status( 243 struct dc_stream_state *stream) 244 { 245 struct dc *dc = stream->ctx->dc; 246 return dc_stream_get_status_from_state(dc->current_state, stream); 247 } 248 249 #ifndef TRIM_FSFT 250 /* 251 * dc_optimize_timing_for_fsft() - dc to optimize timing 252 */ 253 bool dc_optimize_timing_for_fsft( 254 struct dc_stream_state *pStream, 255 unsigned int max_input_rate_in_khz) 256 { 257 struct dc *dc; 258 259 dc = pStream->ctx->dc; 260 261 return (dc->hwss.optimize_timing_for_fsft && 262 dc->hwss.optimize_timing_for_fsft(dc, &pStream->timing, max_input_rate_in_khz)); 263 } 264 #endif 265 266 /* 267 * dc_stream_set_cursor_attributes() - Update cursor attributes and set cursor surface address 268 */ 269 bool dc_stream_set_cursor_attributes( 270 struct dc_stream_state *stream, 271 const struct dc_cursor_attributes *attributes) 272 { 273 int i; 274 struct dc *dc; 275 struct resource_context *res_ctx; 276 struct pipe_ctx *pipe_to_program = NULL; 277 #if defined(CONFIG_DRM_AMD_DC_DCN) 278 bool reset_idle_optimizations = false; 279 #endif 280 281 if (NULL == stream) { 282 dm_error("DC: dc_stream is NULL!\n"); 283 return false; 284 } 285 if (NULL == attributes) { 286 dm_error("DC: attributes is NULL!\n"); 287 return false; 288 } 289 290 if (attributes->address.quad_part == 0) { 291 dm_output_to_console("DC: Cursor address is 0!\n"); 292 return false; 293 } 294 295 dc = stream->ctx->dc; 296 res_ctx = &dc->current_state->res_ctx; 297 stream->cursor_attributes = *attributes; 298 299 #if defined(CONFIG_DRM_AMD_DC_DCN) 300 dc_z10_restore(dc); 301 /* disable idle optimizations while updating cursor */ 302 if (dc->idle_optimizations_allowed) { 303 dc_allow_idle_optimizations(dc, false); 304 reset_idle_optimizations = true; 305 } 306 307 #endif 308 309 for (i = 0; i < MAX_PIPES; i++) { 310 struct pipe_ctx *pipe_ctx = &res_ctx->pipe_ctx[i]; 311 312 if (pipe_ctx->stream != stream) 313 continue; 314 315 if (!pipe_to_program) { 316 pipe_to_program = pipe_ctx; 317 dc->hwss.cursor_lock(dc, pipe_to_program, true); 318 } 319 320 dc->hwss.set_cursor_attribute(pipe_ctx); 321 if (dc->hwss.set_cursor_sdr_white_level) 322 dc->hwss.set_cursor_sdr_white_level(pipe_ctx); 323 } 324 325 if (pipe_to_program) 326 dc->hwss.cursor_lock(dc, pipe_to_program, false); 327 328 #if defined(CONFIG_DRM_AMD_DC_DCN) 329 /* re-enable idle optimizations if necessary */ 330 if (reset_idle_optimizations) 331 dc_allow_idle_optimizations(dc, true); 332 333 #endif 334 return true; 335 } 336 337 bool dc_stream_set_cursor_position( 338 struct dc_stream_state *stream, 339 const struct dc_cursor_position *position) 340 { 341 int i; 342 struct dc *dc; 343 struct resource_context *res_ctx; 344 struct pipe_ctx *pipe_to_program = NULL; 345 #if defined(CONFIG_DRM_AMD_DC_DCN) 346 bool reset_idle_optimizations = false; 347 #endif 348 349 if (NULL == stream) { 350 dm_error("DC: dc_stream is NULL!\n"); 351 return false; 352 } 353 354 if (NULL == position) { 355 dm_error("DC: cursor position is NULL!\n"); 356 return false; 357 } 358 359 dc = stream->ctx->dc; 360 res_ctx = &dc->current_state->res_ctx; 361 #if defined(CONFIG_DRM_AMD_DC_DCN) 362 dc_z10_restore(dc); 363 364 /* disable idle optimizations if enabling cursor */ 365 if (dc->idle_optimizations_allowed && !stream->cursor_position.enable && position->enable) { 366 dc_allow_idle_optimizations(dc, false); 367 reset_idle_optimizations = true; 368 } 369 370 #endif 371 stream->cursor_position = *position; 372 373 for (i = 0; i < MAX_PIPES; i++) { 374 struct pipe_ctx *pipe_ctx = &res_ctx->pipe_ctx[i]; 375 376 if (pipe_ctx->stream != stream || 377 (!pipe_ctx->plane_res.mi && !pipe_ctx->plane_res.hubp) || 378 !pipe_ctx->plane_state || 379 (!pipe_ctx->plane_res.xfm && !pipe_ctx->plane_res.dpp) || 380 (!pipe_ctx->plane_res.ipp && !pipe_ctx->plane_res.dpp)) 381 continue; 382 383 if (!pipe_to_program) { 384 pipe_to_program = pipe_ctx; 385 dc->hwss.cursor_lock(dc, pipe_to_program, true); 386 } 387 388 dc->hwss.set_cursor_position(pipe_ctx); 389 } 390 391 if (pipe_to_program) 392 dc->hwss.cursor_lock(dc, pipe_to_program, false); 393 394 #if defined(CONFIG_DRM_AMD_DC_DCN) 395 /* re-enable idle optimizations if necessary */ 396 if (reset_idle_optimizations) 397 dc_allow_idle_optimizations(dc, true); 398 399 #endif 400 return true; 401 } 402 403 bool dc_stream_add_writeback(struct dc *dc, 404 struct dc_stream_state *stream, 405 struct dc_writeback_info *wb_info) 406 { 407 bool isDrc = false; 408 int i = 0; 409 struct dwbc *dwb; 410 411 if (stream == NULL) { 412 dm_error("DC: dc_stream is NULL!\n"); 413 return false; 414 } 415 416 if (wb_info == NULL) { 417 dm_error("DC: dc_writeback_info is NULL!\n"); 418 return false; 419 } 420 421 if (wb_info->dwb_pipe_inst >= MAX_DWB_PIPES) { 422 dm_error("DC: writeback pipe is invalid!\n"); 423 return false; 424 } 425 426 wb_info->dwb_params.out_transfer_func = stream->out_transfer_func; 427 428 dwb = dc->res_pool->dwbc[wb_info->dwb_pipe_inst]; 429 dwb->dwb_is_drc = false; 430 431 /* recalculate and apply DML parameters */ 432 433 for (i = 0; i < stream->num_wb_info; i++) { 434 /*dynamic update*/ 435 if (stream->writeback_info[i].wb_enabled && 436 stream->writeback_info[i].dwb_pipe_inst == wb_info->dwb_pipe_inst) { 437 stream->writeback_info[i] = *wb_info; 438 isDrc = true; 439 } 440 } 441 442 if (!isDrc) { 443 stream->writeback_info[stream->num_wb_info++] = *wb_info; 444 } 445 446 if (dc->hwss.enable_writeback) { 447 struct dc_stream_status *stream_status = dc_stream_get_status(stream); 448 struct dwbc *dwb = dc->res_pool->dwbc[wb_info->dwb_pipe_inst]; 449 dwb->otg_inst = stream_status->primary_otg_inst; 450 } 451 if (IS_DIAG_DC(dc->ctx->dce_environment)) { 452 if (!dc->hwss.update_bandwidth(dc, dc->current_state)) { 453 dm_error("DC: update_bandwidth failed!\n"); 454 return false; 455 } 456 457 /* enable writeback */ 458 if (dc->hwss.enable_writeback) { 459 struct dwbc *dwb = dc->res_pool->dwbc[wb_info->dwb_pipe_inst]; 460 461 if (dwb->funcs->is_enabled(dwb)) { 462 /* writeback pipe already enabled, only need to update */ 463 dc->hwss.update_writeback(dc, wb_info, dc->current_state); 464 } else { 465 /* Enable writeback pipe from scratch*/ 466 dc->hwss.enable_writeback(dc, wb_info, dc->current_state); 467 } 468 } 469 } 470 return true; 471 } 472 473 bool dc_stream_remove_writeback(struct dc *dc, 474 struct dc_stream_state *stream, 475 uint32_t dwb_pipe_inst) 476 { 477 int i = 0, j = 0; 478 if (stream == NULL) { 479 dm_error("DC: dc_stream is NULL!\n"); 480 return false; 481 } 482 483 if (dwb_pipe_inst >= MAX_DWB_PIPES) { 484 dm_error("DC: writeback pipe is invalid!\n"); 485 return false; 486 } 487 488 // stream->writeback_info[dwb_pipe_inst].wb_enabled = false; 489 for (i = 0; i < stream->num_wb_info; i++) { 490 /*dynamic update*/ 491 if (stream->writeback_info[i].wb_enabled && 492 stream->writeback_info[i].dwb_pipe_inst == dwb_pipe_inst) { 493 stream->writeback_info[i].wb_enabled = false; 494 } 495 } 496 497 /* remove writeback info for disabled writeback pipes from stream */ 498 for (i = 0, j = 0; i < stream->num_wb_info; i++) { 499 if (stream->writeback_info[i].wb_enabled) { 500 if (i != j) 501 /* trim the array */ 502 stream->writeback_info[j] = stream->writeback_info[i]; 503 j++; 504 } 505 } 506 stream->num_wb_info = j; 507 508 if (IS_DIAG_DC(dc->ctx->dce_environment)) { 509 /* recalculate and apply DML parameters */ 510 if (!dc->hwss.update_bandwidth(dc, dc->current_state)) { 511 dm_error("DC: update_bandwidth failed!\n"); 512 return false; 513 } 514 515 /* disable writeback */ 516 if (dc->hwss.disable_writeback) 517 dc->hwss.disable_writeback(dc, dwb_pipe_inst); 518 } 519 return true; 520 } 521 522 bool dc_stream_warmup_writeback(struct dc *dc, 523 int num_dwb, 524 struct dc_writeback_info *wb_info) 525 { 526 if (dc->hwss.mmhubbub_warmup) 527 return dc->hwss.mmhubbub_warmup(dc, num_dwb, wb_info); 528 else 529 return false; 530 } 531 uint32_t dc_stream_get_vblank_counter(const struct dc_stream_state *stream) 532 { 533 uint8_t i; 534 struct dc *dc = stream->ctx->dc; 535 struct resource_context *res_ctx = 536 &dc->current_state->res_ctx; 537 538 for (i = 0; i < MAX_PIPES; i++) { 539 struct timing_generator *tg = res_ctx->pipe_ctx[i].stream_res.tg; 540 541 if (res_ctx->pipe_ctx[i].stream != stream) 542 continue; 543 544 return tg->funcs->get_frame_count(tg); 545 } 546 547 return 0; 548 } 549 550 bool dc_stream_send_dp_sdp(const struct dc_stream_state *stream, 551 const uint8_t *custom_sdp_message, 552 unsigned int sdp_message_size) 553 { 554 int i; 555 struct dc *dc; 556 struct resource_context *res_ctx; 557 558 if (stream == NULL) { 559 dm_error("DC: dc_stream is NULL!\n"); 560 return false; 561 } 562 563 dc = stream->ctx->dc; 564 res_ctx = &dc->current_state->res_ctx; 565 566 for (i = 0; i < MAX_PIPES; i++) { 567 struct pipe_ctx *pipe_ctx = &res_ctx->pipe_ctx[i]; 568 569 if (pipe_ctx->stream != stream) 570 continue; 571 572 if (dc->hwss.send_immediate_sdp_message != NULL) 573 dc->hwss.send_immediate_sdp_message(pipe_ctx, 574 custom_sdp_message, 575 sdp_message_size); 576 else 577 DC_LOG_WARNING("%s:send_immediate_sdp_message not implemented on this ASIC\n", 578 __func__); 579 580 } 581 582 return true; 583 } 584 585 bool dc_stream_get_scanoutpos(const struct dc_stream_state *stream, 586 uint32_t *v_blank_start, 587 uint32_t *v_blank_end, 588 uint32_t *h_position, 589 uint32_t *v_position) 590 { 591 uint8_t i; 592 bool ret = false; 593 struct dc *dc = stream->ctx->dc; 594 struct resource_context *res_ctx = 595 &dc->current_state->res_ctx; 596 597 for (i = 0; i < MAX_PIPES; i++) { 598 struct timing_generator *tg = res_ctx->pipe_ctx[i].stream_res.tg; 599 600 if (res_ctx->pipe_ctx[i].stream != stream) 601 continue; 602 603 tg->funcs->get_scanoutpos(tg, 604 v_blank_start, 605 v_blank_end, 606 h_position, 607 v_position); 608 609 ret = true; 610 break; 611 } 612 613 return ret; 614 } 615 616 bool dc_stream_dmdata_status_done(struct dc *dc, struct dc_stream_state *stream) 617 { 618 struct pipe_ctx *pipe = NULL; 619 int i; 620 621 if (!dc->hwss.dmdata_status_done) 622 return false; 623 624 for (i = 0; i < MAX_PIPES; i++) { 625 pipe = &dc->current_state->res_ctx.pipe_ctx[i]; 626 if (pipe->stream == stream) 627 break; 628 } 629 /* Stream not found, by default we'll assume HUBP fetched dm data */ 630 if (i == MAX_PIPES) 631 return true; 632 633 return dc->hwss.dmdata_status_done(pipe); 634 } 635 636 bool dc_stream_set_dynamic_metadata(struct dc *dc, 637 struct dc_stream_state *stream, 638 struct dc_dmdata_attributes *attr) 639 { 640 struct pipe_ctx *pipe_ctx = NULL; 641 struct hubp *hubp; 642 int i; 643 644 /* Dynamic metadata is only supported on HDMI or DP */ 645 if (!dc_is_hdmi_signal(stream->signal) && !dc_is_dp_signal(stream->signal)) 646 return false; 647 648 /* Check hardware support */ 649 if (!dc->hwss.program_dmdata_engine) 650 return false; 651 652 for (i = 0; i < MAX_PIPES; i++) { 653 pipe_ctx = &dc->current_state->res_ctx.pipe_ctx[i]; 654 if (pipe_ctx->stream == stream) 655 break; 656 } 657 658 if (i == MAX_PIPES) 659 return false; 660 661 hubp = pipe_ctx->plane_res.hubp; 662 if (hubp == NULL) 663 return false; 664 665 pipe_ctx->stream->dmdata_address = attr->address; 666 667 dc->hwss.program_dmdata_engine(pipe_ctx); 668 669 if (hubp->funcs->dmdata_set_attributes != NULL && 670 pipe_ctx->stream->dmdata_address.quad_part != 0) { 671 hubp->funcs->dmdata_set_attributes(hubp, attr); 672 } 673 674 return true; 675 } 676 677 enum dc_status dc_stream_add_dsc_to_resource(struct dc *dc, 678 struct dc_state *state, 679 struct dc_stream_state *stream) 680 { 681 if (dc->res_pool->funcs->add_dsc_to_stream_resource) { 682 return dc->res_pool->funcs->add_dsc_to_stream_resource(dc, state, stream); 683 } else { 684 return DC_NO_DSC_RESOURCE; 685 } 686 } 687 688 void dc_stream_log(const struct dc *dc, const struct dc_stream_state *stream) 689 { 690 DC_LOG_DC( 691 "core_stream 0x%p: src: %d, %d, %d, %d; dst: %d, %d, %d, %d, colorSpace:%d\n", 692 stream, 693 stream->src.x, 694 stream->src.y, 695 stream->src.width, 696 stream->src.height, 697 stream->dst.x, 698 stream->dst.y, 699 stream->dst.width, 700 stream->dst.height, 701 stream->output_color_space); 702 DC_LOG_DC( 703 "\tpix_clk_khz: %d, h_total: %d, v_total: %d, pixelencoder:%d, displaycolorDepth:%d\n", 704 stream->timing.pix_clk_100hz / 10, 705 stream->timing.h_total, 706 stream->timing.v_total, 707 stream->timing.pixel_encoding, 708 stream->timing.display_color_depth); 709 DC_LOG_DC( 710 "\tlink: %d\n", 711 stream->link->link_index); 712 } 713 714