1 /* 2 * Copyright 2012-15 Advanced Micro Devices, Inc. 3 * 4 * Permission is hereby granted, free of charge, to any person obtaining a 5 * copy of this software and associated documentation files (the "Software"), 6 * to deal in the Software without restriction, including without limitation 7 * the rights to use, copy, modify, merge, publish, distribute, sublicense, 8 * and/or sell copies of the Software, and to permit persons to whom the 9 * Software is furnished to do so, subject to the following conditions: 10 * 11 * The above copyright notice and this permission notice shall be included in 12 * all copies or substantial portions of the Software. 13 * 14 * THE SOFTWARE IS PROVIDED "AS IS", WITHOUT WARRANTY OF ANY KIND, EXPRESS OR 15 * IMPLIED, INCLUDING BUT NOT LIMITED TO THE WARRANTIES OF MERCHANTABILITY, 16 * FITNESS FOR A PARTICULAR PURPOSE AND NONINFRINGEMENT. IN NO EVENT SHALL 17 * THE COPYRIGHT HOLDER(S) OR AUTHOR(S) BE LIABLE FOR ANY CLAIM, DAMAGES OR 18 * OTHER LIABILITY, WHETHER IN AN ACTION OF CONTRACT, TORT OR OTHERWISE, 19 * ARISING FROM, OUT OF OR IN CONNECTION WITH THE SOFTWARE OR THE USE OR 20 * OTHER DEALINGS IN THE SOFTWARE. 21 * 22 * Authors: AMD 23 * 24 */ 25 26 #include "dm_services.h" 27 #include "basics/dc_common.h" 28 #include "dc.h" 29 #include "core_types.h" 30 #include "resource.h" 31 #include "ipp.h" 32 #include "timing_generator.h" 33 #include "dc_dmub_srv.h" 34 35 #define DC_LOGGER dc->ctx->logger 36 37 /******************************************************************************* 38 * Private functions 39 ******************************************************************************/ 40 void update_stream_signal(struct dc_stream_state *stream, struct dc_sink *sink) 41 { 42 if (sink->sink_signal == SIGNAL_TYPE_NONE) 43 stream->signal = stream->link->connector_signal; 44 else 45 stream->signal = sink->sink_signal; 46 47 if (dc_is_dvi_signal(stream->signal)) { 48 if (stream->ctx->dc->caps.dual_link_dvi && 49 (stream->timing.pix_clk_100hz / 10) > TMDS_MAX_PIXEL_CLOCK && 50 sink->sink_signal != SIGNAL_TYPE_DVI_SINGLE_LINK) 51 stream->signal = SIGNAL_TYPE_DVI_DUAL_LINK; 52 else 53 stream->signal = SIGNAL_TYPE_DVI_SINGLE_LINK; 54 } 55 } 56 57 static bool dc_stream_construct(struct dc_stream_state *stream, 58 struct dc_sink *dc_sink_data) 59 { 60 uint32_t i = 0; 61 62 stream->sink = dc_sink_data; 63 dc_sink_retain(dc_sink_data); 64 65 stream->ctx = dc_sink_data->ctx; 66 stream->link = dc_sink_data->link; 67 stream->sink_patches = dc_sink_data->edid_caps.panel_patch; 68 stream->converter_disable_audio = dc_sink_data->converter_disable_audio; 69 stream->qs_bit = dc_sink_data->edid_caps.qs_bit; 70 stream->qy_bit = dc_sink_data->edid_caps.qy_bit; 71 72 /* Copy audio modes */ 73 /* TODO - Remove this translation */ 74 for (i = 0; i < (dc_sink_data->edid_caps.audio_mode_count); i++) 75 { 76 stream->audio_info.modes[i].channel_count = dc_sink_data->edid_caps.audio_modes[i].channel_count; 77 stream->audio_info.modes[i].format_code = dc_sink_data->edid_caps.audio_modes[i].format_code; 78 stream->audio_info.modes[i].sample_rates.all = dc_sink_data->edid_caps.audio_modes[i].sample_rate; 79 stream->audio_info.modes[i].sample_size = dc_sink_data->edid_caps.audio_modes[i].sample_size; 80 } 81 stream->audio_info.mode_count = dc_sink_data->edid_caps.audio_mode_count; 82 stream->audio_info.audio_latency = dc_sink_data->edid_caps.audio_latency; 83 stream->audio_info.video_latency = dc_sink_data->edid_caps.video_latency; 84 memmove( 85 stream->audio_info.display_name, 86 dc_sink_data->edid_caps.display_name, 87 AUDIO_INFO_DISPLAY_NAME_SIZE_IN_CHARS); 88 stream->audio_info.manufacture_id = dc_sink_data->edid_caps.manufacturer_id; 89 stream->audio_info.product_id = dc_sink_data->edid_caps.product_id; 90 stream->audio_info.flags.all = dc_sink_data->edid_caps.speaker_flags; 91 92 if (dc_sink_data->dc_container_id != NULL) { 93 struct dc_container_id *dc_container_id = dc_sink_data->dc_container_id; 94 95 stream->audio_info.port_id[0] = dc_container_id->portId[0]; 96 stream->audio_info.port_id[1] = dc_container_id->portId[1]; 97 } else { 98 /* TODO - WindowDM has implemented, 99 other DMs need Unhardcode port_id */ 100 stream->audio_info.port_id[0] = 0x5558859e; 101 stream->audio_info.port_id[1] = 0xd989449; 102 } 103 104 /* EDID CAP translation for HDMI 2.0 */ 105 stream->timing.flags.LTE_340MCSC_SCRAMBLE = dc_sink_data->edid_caps.lte_340mcsc_scramble; 106 107 memset(&stream->timing.dsc_cfg, 0, sizeof(stream->timing.dsc_cfg)); 108 stream->timing.dsc_cfg.num_slices_h = 0; 109 stream->timing.dsc_cfg.num_slices_v = 0; 110 stream->timing.dsc_cfg.bits_per_pixel = 128; 111 stream->timing.dsc_cfg.block_pred_enable = 1; 112 stream->timing.dsc_cfg.linebuf_depth = 9; 113 stream->timing.dsc_cfg.version_minor = 2; 114 stream->timing.dsc_cfg.ycbcr422_simple = 0; 115 116 update_stream_signal(stream, dc_sink_data); 117 118 stream->out_transfer_func = dc_create_transfer_func(); 119 if (stream->out_transfer_func == NULL) { 120 dc_sink_release(dc_sink_data); 121 return false; 122 } 123 stream->out_transfer_func->type = TF_TYPE_BYPASS; 124 125 stream->stream_id = stream->ctx->dc_stream_id_count; 126 stream->ctx->dc_stream_id_count++; 127 128 return true; 129 } 130 131 static void dc_stream_destruct(struct dc_stream_state *stream) 132 { 133 dc_sink_release(stream->sink); 134 if (stream->out_transfer_func != NULL) { 135 dc_transfer_func_release(stream->out_transfer_func); 136 stream->out_transfer_func = NULL; 137 } 138 } 139 140 void dc_stream_retain(struct dc_stream_state *stream) 141 { 142 kref_get(&stream->refcount); 143 } 144 145 static void dc_stream_free(struct kref *kref) 146 { 147 struct dc_stream_state *stream = container_of(kref, struct dc_stream_state, refcount); 148 149 dc_stream_destruct(stream); 150 kfree(stream); 151 } 152 153 void dc_stream_release(struct dc_stream_state *stream) 154 { 155 if (stream != NULL) { 156 kref_put(&stream->refcount, dc_stream_free); 157 } 158 } 159 160 struct dc_stream_state *dc_create_stream_for_sink( 161 struct dc_sink *sink) 162 { 163 struct dc_stream_state *stream; 164 165 if (sink == NULL) 166 return NULL; 167 168 stream = kzalloc(sizeof(struct dc_stream_state), GFP_KERNEL); 169 if (stream == NULL) 170 goto alloc_fail; 171 172 if (dc_stream_construct(stream, sink) == false) 173 goto construct_fail; 174 175 kref_init(&stream->refcount); 176 177 return stream; 178 179 construct_fail: 180 kfree(stream); 181 182 alloc_fail: 183 return NULL; 184 } 185 186 struct dc_stream_state *dc_copy_stream(const struct dc_stream_state *stream) 187 { 188 struct dc_stream_state *new_stream; 189 190 new_stream = kmemdup(stream, sizeof(struct dc_stream_state), GFP_KERNEL); 191 if (!new_stream) 192 return NULL; 193 194 if (new_stream->sink) 195 dc_sink_retain(new_stream->sink); 196 197 if (new_stream->out_transfer_func) 198 dc_transfer_func_retain(new_stream->out_transfer_func); 199 200 new_stream->stream_id = new_stream->ctx->dc_stream_id_count; 201 new_stream->ctx->dc_stream_id_count++; 202 203 /* If using dynamic encoder assignment, wait till stream committed to assign encoder. */ 204 if (new_stream->ctx->dc->res_pool->funcs->link_encs_assign) 205 new_stream->link_enc = NULL; 206 207 kref_init(&new_stream->refcount); 208 209 return new_stream; 210 } 211 212 /** 213 * dc_stream_get_status_from_state - Get stream status from given dc state 214 * @state: DC state to find the stream status in 215 * @stream: The stream to get the stream status for 216 * 217 * The given stream is expected to exist in the given dc state. Otherwise, NULL 218 * will be returned. 219 */ 220 struct dc_stream_status *dc_stream_get_status_from_state( 221 struct dc_state *state, 222 struct dc_stream_state *stream) 223 { 224 uint8_t i; 225 226 if (state == NULL) 227 return NULL; 228 229 for (i = 0; i < state->stream_count; i++) { 230 if (stream == state->streams[i]) 231 return &state->stream_status[i]; 232 } 233 234 return NULL; 235 } 236 237 /** 238 * dc_stream_get_status() - Get current stream status of the given stream state 239 * @stream: The stream to get the stream status for. 240 * 241 * The given stream is expected to exist in dc->current_state. Otherwise, NULL 242 * will be returned. 243 */ 244 struct dc_stream_status *dc_stream_get_status( 245 struct dc_stream_state *stream) 246 { 247 struct dc *dc = stream->ctx->dc; 248 return dc_stream_get_status_from_state(dc->current_state, stream); 249 } 250 251 static void program_cursor_attributes( 252 struct dc *dc, 253 struct dc_stream_state *stream, 254 const struct dc_cursor_attributes *attributes) 255 { 256 int i; 257 struct resource_context *res_ctx; 258 struct pipe_ctx *pipe_to_program = NULL; 259 260 if (!stream) 261 return; 262 263 res_ctx = &dc->current_state->res_ctx; 264 265 for (i = 0; i < MAX_PIPES; i++) { 266 struct pipe_ctx *pipe_ctx = &res_ctx->pipe_ctx[i]; 267 268 if (pipe_ctx->stream != stream) 269 continue; 270 271 if (!pipe_to_program) { 272 pipe_to_program = pipe_ctx; 273 dc->hwss.cursor_lock(dc, pipe_to_program, true); 274 if (pipe_to_program->next_odm_pipe) 275 dc->hwss.cursor_lock(dc, pipe_to_program->next_odm_pipe, true); 276 } 277 278 dc->hwss.set_cursor_attribute(pipe_ctx); 279 280 dc_send_update_cursor_info_to_dmu(pipe_ctx, i); 281 if (dc->hwss.set_cursor_sdr_white_level) 282 dc->hwss.set_cursor_sdr_white_level(pipe_ctx); 283 } 284 285 if (pipe_to_program) { 286 dc->hwss.cursor_lock(dc, pipe_to_program, false); 287 if (pipe_to_program->next_odm_pipe) 288 dc->hwss.cursor_lock(dc, pipe_to_program->next_odm_pipe, false); 289 } 290 } 291 292 #ifndef TRIM_FSFT 293 /* 294 * dc_optimize_timing_for_fsft() - dc to optimize timing 295 */ 296 bool dc_optimize_timing_for_fsft( 297 struct dc_stream_state *pStream, 298 unsigned int max_input_rate_in_khz) 299 { 300 struct dc *dc; 301 302 dc = pStream->ctx->dc; 303 304 return (dc->hwss.optimize_timing_for_fsft && 305 dc->hwss.optimize_timing_for_fsft(dc, &pStream->timing, max_input_rate_in_khz)); 306 } 307 #endif 308 309 /* 310 * dc_stream_set_cursor_attributes() - Update cursor attributes and set cursor surface address 311 */ 312 bool dc_stream_set_cursor_attributes( 313 struct dc_stream_state *stream, 314 const struct dc_cursor_attributes *attributes) 315 { 316 struct dc *dc; 317 bool reset_idle_optimizations = false; 318 319 if (NULL == stream) { 320 dm_error("DC: dc_stream is NULL!\n"); 321 return false; 322 } 323 if (NULL == attributes) { 324 dm_error("DC: attributes is NULL!\n"); 325 return false; 326 } 327 328 if (attributes->address.quad_part == 0) { 329 dm_output_to_console("DC: Cursor address is 0!\n"); 330 return false; 331 } 332 333 dc = stream->ctx->dc; 334 335 /* SubVP is not compatible with HW cursor larger than 64 x 64 x 4. 336 * Therefore, if cursor is greater than 64 x 64 x 4, fallback to SW cursor in the following case: 337 * 1. For single display cases, if resolution is >= 5K and refresh rate < 120hz 338 * 2. For multi display cases, if resolution is >= 4K and refresh rate < 120hz 339 * 340 * [< 120hz is a requirement for SubVP configs] 341 */ 342 if (dc->debug.allow_sw_cursor_fallback && attributes->height * attributes->width * 4 > 16384) { 343 if (dc->current_state->stream_count == 1 && stream->timing.v_addressable >= 2880 && 344 ((stream->timing.pix_clk_100hz * 100) / stream->timing.v_total / stream->timing.h_total) < 120) 345 return false; 346 else if (dc->current_state->stream_count > 1 && stream->timing.v_addressable >= 2160 && 347 ((stream->timing.pix_clk_100hz * 100) / stream->timing.v_total / stream->timing.h_total) < 120) 348 return false; 349 } 350 351 stream->cursor_attributes = *attributes; 352 353 dc_z10_restore(dc); 354 /* disable idle optimizations while updating cursor */ 355 if (dc->idle_optimizations_allowed) { 356 dc_allow_idle_optimizations(dc, false); 357 reset_idle_optimizations = true; 358 } 359 360 program_cursor_attributes(dc, stream, attributes); 361 362 /* re-enable idle optimizations if necessary */ 363 if (reset_idle_optimizations) 364 dc_allow_idle_optimizations(dc, true); 365 366 return true; 367 } 368 369 static void program_cursor_position( 370 struct dc *dc, 371 struct dc_stream_state *stream, 372 const struct dc_cursor_position *position) 373 { 374 int i; 375 struct resource_context *res_ctx; 376 struct pipe_ctx *pipe_to_program = NULL; 377 378 if (!stream) 379 return; 380 381 res_ctx = &dc->current_state->res_ctx; 382 383 for (i = 0; i < MAX_PIPES; i++) { 384 struct pipe_ctx *pipe_ctx = &res_ctx->pipe_ctx[i]; 385 386 if (pipe_ctx->stream != stream || 387 (!pipe_ctx->plane_res.mi && !pipe_ctx->plane_res.hubp) || 388 !pipe_ctx->plane_state || 389 (!pipe_ctx->plane_res.xfm && !pipe_ctx->plane_res.dpp) || 390 (!pipe_ctx->plane_res.ipp && !pipe_ctx->plane_res.dpp)) 391 continue; 392 393 if (!pipe_to_program) { 394 pipe_to_program = pipe_ctx; 395 dc->hwss.cursor_lock(dc, pipe_to_program, true); 396 } 397 398 dc->hwss.set_cursor_position(pipe_ctx); 399 400 dc_send_update_cursor_info_to_dmu(pipe_ctx, i); 401 } 402 403 if (pipe_to_program) 404 dc->hwss.cursor_lock(dc, pipe_to_program, false); 405 } 406 407 bool dc_stream_set_cursor_position( 408 struct dc_stream_state *stream, 409 const struct dc_cursor_position *position) 410 { 411 struct dc *dc; 412 bool reset_idle_optimizations = false; 413 414 if (NULL == stream) { 415 dm_error("DC: dc_stream is NULL!\n"); 416 return false; 417 } 418 419 if (NULL == position) { 420 dm_error("DC: cursor position is NULL!\n"); 421 return false; 422 } 423 424 dc = stream->ctx->dc; 425 dc_z10_restore(dc); 426 427 /* disable idle optimizations if enabling cursor */ 428 if (dc->idle_optimizations_allowed && (!stream->cursor_position.enable || dc->debug.exit_idle_opt_for_cursor_updates) 429 && position->enable) { 430 dc_allow_idle_optimizations(dc, false); 431 reset_idle_optimizations = true; 432 } 433 434 stream->cursor_position = *position; 435 436 program_cursor_position(dc, stream, position); 437 /* re-enable idle optimizations if necessary */ 438 if (reset_idle_optimizations) 439 dc_allow_idle_optimizations(dc, true); 440 441 return true; 442 } 443 444 bool dc_stream_add_writeback(struct dc *dc, 445 struct dc_stream_state *stream, 446 struct dc_writeback_info *wb_info) 447 { 448 bool isDrc = false; 449 int i = 0; 450 struct dwbc *dwb; 451 452 if (stream == NULL) { 453 dm_error("DC: dc_stream is NULL!\n"); 454 return false; 455 } 456 457 if (wb_info == NULL) { 458 dm_error("DC: dc_writeback_info is NULL!\n"); 459 return false; 460 } 461 462 if (wb_info->dwb_pipe_inst >= MAX_DWB_PIPES) { 463 dm_error("DC: writeback pipe is invalid!\n"); 464 return false; 465 } 466 467 wb_info->dwb_params.out_transfer_func = stream->out_transfer_func; 468 469 dwb = dc->res_pool->dwbc[wb_info->dwb_pipe_inst]; 470 dwb->dwb_is_drc = false; 471 472 /* recalculate and apply DML parameters */ 473 474 for (i = 0; i < stream->num_wb_info; i++) { 475 /*dynamic update*/ 476 if (stream->writeback_info[i].wb_enabled && 477 stream->writeback_info[i].dwb_pipe_inst == wb_info->dwb_pipe_inst) { 478 stream->writeback_info[i] = *wb_info; 479 isDrc = true; 480 } 481 } 482 483 if (!isDrc) { 484 ASSERT(stream->num_wb_info + 1 <= MAX_DWB_PIPES); 485 stream->writeback_info[stream->num_wb_info++] = *wb_info; 486 } 487 488 if (dc->hwss.enable_writeback) { 489 struct dc_stream_status *stream_status = dc_stream_get_status(stream); 490 struct dwbc *dwb = dc->res_pool->dwbc[wb_info->dwb_pipe_inst]; 491 dwb->otg_inst = stream_status->primary_otg_inst; 492 } 493 if (IS_DIAG_DC(dc->ctx->dce_environment)) { 494 if (!dc->hwss.update_bandwidth(dc, dc->current_state)) { 495 dm_error("DC: update_bandwidth failed!\n"); 496 return false; 497 } 498 499 /* enable writeback */ 500 if (dc->hwss.enable_writeback) { 501 struct dwbc *dwb = dc->res_pool->dwbc[wb_info->dwb_pipe_inst]; 502 503 if (dwb->funcs->is_enabled(dwb)) { 504 /* writeback pipe already enabled, only need to update */ 505 dc->hwss.update_writeback(dc, wb_info, dc->current_state); 506 } else { 507 /* Enable writeback pipe from scratch*/ 508 dc->hwss.enable_writeback(dc, wb_info, dc->current_state); 509 } 510 } 511 } 512 return true; 513 } 514 515 bool dc_stream_remove_writeback(struct dc *dc, 516 struct dc_stream_state *stream, 517 uint32_t dwb_pipe_inst) 518 { 519 int i = 0, j = 0; 520 if (stream == NULL) { 521 dm_error("DC: dc_stream is NULL!\n"); 522 return false; 523 } 524 525 if (dwb_pipe_inst >= MAX_DWB_PIPES) { 526 dm_error("DC: writeback pipe is invalid!\n"); 527 return false; 528 } 529 530 if (stream->num_wb_info > MAX_DWB_PIPES) { 531 dm_error("DC: num_wb_info is invalid!\n"); 532 return false; 533 } 534 535 // stream->writeback_info[dwb_pipe_inst].wb_enabled = false; 536 for (i = 0; i < stream->num_wb_info; i++) { 537 /*dynamic update*/ 538 if (stream->writeback_info[i].wb_enabled && 539 stream->writeback_info[i].dwb_pipe_inst == dwb_pipe_inst) { 540 stream->writeback_info[i].wb_enabled = false; 541 } 542 } 543 544 /* remove writeback info for disabled writeback pipes from stream */ 545 for (i = 0, j = 0; i < stream->num_wb_info; i++) { 546 if (stream->writeback_info[i].wb_enabled) { 547 if (j < i) 548 /* trim the array */ 549 memcpy(&stream->writeback_info[j], &stream->writeback_info[i], 550 sizeof(struct dc_writeback_info)); 551 j++; 552 } 553 } 554 stream->num_wb_info = j; 555 556 if (IS_DIAG_DC(dc->ctx->dce_environment)) { 557 /* recalculate and apply DML parameters */ 558 if (!dc->hwss.update_bandwidth(dc, dc->current_state)) { 559 dm_error("DC: update_bandwidth failed!\n"); 560 return false; 561 } 562 563 /* disable writeback */ 564 if (dc->hwss.disable_writeback) 565 dc->hwss.disable_writeback(dc, dwb_pipe_inst); 566 } 567 return true; 568 } 569 570 bool dc_stream_warmup_writeback(struct dc *dc, 571 int num_dwb, 572 struct dc_writeback_info *wb_info) 573 { 574 if (dc->hwss.mmhubbub_warmup) 575 return dc->hwss.mmhubbub_warmup(dc, num_dwb, wb_info); 576 else 577 return false; 578 } 579 uint32_t dc_stream_get_vblank_counter(const struct dc_stream_state *stream) 580 { 581 uint8_t i; 582 struct dc *dc = stream->ctx->dc; 583 struct resource_context *res_ctx = 584 &dc->current_state->res_ctx; 585 586 for (i = 0; i < MAX_PIPES; i++) { 587 struct timing_generator *tg = res_ctx->pipe_ctx[i].stream_res.tg; 588 589 if (res_ctx->pipe_ctx[i].stream != stream) 590 continue; 591 592 return tg->funcs->get_frame_count(tg); 593 } 594 595 return 0; 596 } 597 598 bool dc_stream_send_dp_sdp(const struct dc_stream_state *stream, 599 const uint8_t *custom_sdp_message, 600 unsigned int sdp_message_size) 601 { 602 int i; 603 struct dc *dc; 604 struct resource_context *res_ctx; 605 606 if (stream == NULL) { 607 dm_error("DC: dc_stream is NULL!\n"); 608 return false; 609 } 610 611 dc = stream->ctx->dc; 612 res_ctx = &dc->current_state->res_ctx; 613 614 for (i = 0; i < MAX_PIPES; i++) { 615 struct pipe_ctx *pipe_ctx = &res_ctx->pipe_ctx[i]; 616 617 if (pipe_ctx->stream != stream) 618 continue; 619 620 if (dc->hwss.send_immediate_sdp_message != NULL) 621 dc->hwss.send_immediate_sdp_message(pipe_ctx, 622 custom_sdp_message, 623 sdp_message_size); 624 else 625 DC_LOG_WARNING("%s:send_immediate_sdp_message not implemented on this ASIC\n", 626 __func__); 627 628 } 629 630 return true; 631 } 632 633 bool dc_stream_get_scanoutpos(const struct dc_stream_state *stream, 634 uint32_t *v_blank_start, 635 uint32_t *v_blank_end, 636 uint32_t *h_position, 637 uint32_t *v_position) 638 { 639 uint8_t i; 640 bool ret = false; 641 struct dc *dc = stream->ctx->dc; 642 struct resource_context *res_ctx = 643 &dc->current_state->res_ctx; 644 645 for (i = 0; i < MAX_PIPES; i++) { 646 struct timing_generator *tg = res_ctx->pipe_ctx[i].stream_res.tg; 647 648 if (res_ctx->pipe_ctx[i].stream != stream) 649 continue; 650 651 tg->funcs->get_scanoutpos(tg, 652 v_blank_start, 653 v_blank_end, 654 h_position, 655 v_position); 656 657 ret = true; 658 break; 659 } 660 661 return ret; 662 } 663 664 bool dc_stream_dmdata_status_done(struct dc *dc, struct dc_stream_state *stream) 665 { 666 struct pipe_ctx *pipe = NULL; 667 int i; 668 669 if (!dc->hwss.dmdata_status_done) 670 return false; 671 672 for (i = 0; i < MAX_PIPES; i++) { 673 pipe = &dc->current_state->res_ctx.pipe_ctx[i]; 674 if (pipe->stream == stream) 675 break; 676 } 677 /* Stream not found, by default we'll assume HUBP fetched dm data */ 678 if (i == MAX_PIPES) 679 return true; 680 681 return dc->hwss.dmdata_status_done(pipe); 682 } 683 684 bool dc_stream_set_dynamic_metadata(struct dc *dc, 685 struct dc_stream_state *stream, 686 struct dc_dmdata_attributes *attr) 687 { 688 struct pipe_ctx *pipe_ctx = NULL; 689 struct hubp *hubp; 690 int i; 691 692 /* Dynamic metadata is only supported on HDMI or DP */ 693 if (!dc_is_hdmi_signal(stream->signal) && !dc_is_dp_signal(stream->signal)) 694 return false; 695 696 /* Check hardware support */ 697 if (!dc->hwss.program_dmdata_engine) 698 return false; 699 700 for (i = 0; i < MAX_PIPES; i++) { 701 pipe_ctx = &dc->current_state->res_ctx.pipe_ctx[i]; 702 if (pipe_ctx->stream == stream) 703 break; 704 } 705 706 if (i == MAX_PIPES) 707 return false; 708 709 hubp = pipe_ctx->plane_res.hubp; 710 if (hubp == NULL) 711 return false; 712 713 pipe_ctx->stream->dmdata_address = attr->address; 714 715 dc->hwss.program_dmdata_engine(pipe_ctx); 716 717 if (hubp->funcs->dmdata_set_attributes != NULL && 718 pipe_ctx->stream->dmdata_address.quad_part != 0) { 719 hubp->funcs->dmdata_set_attributes(hubp, attr); 720 } 721 722 return true; 723 } 724 725 enum dc_status dc_stream_add_dsc_to_resource(struct dc *dc, 726 struct dc_state *state, 727 struct dc_stream_state *stream) 728 { 729 if (dc->res_pool->funcs->add_dsc_to_stream_resource) { 730 return dc->res_pool->funcs->add_dsc_to_stream_resource(dc, state, stream); 731 } else { 732 return DC_NO_DSC_RESOURCE; 733 } 734 } 735 736 struct pipe_ctx *dc_stream_get_pipe_ctx(struct dc_stream_state *stream) 737 { 738 int i = 0; 739 740 for (i = 0; i < MAX_PIPES; i++) { 741 struct pipe_ctx *pipe = &stream->ctx->dc->current_state->res_ctx.pipe_ctx[i]; 742 743 if (pipe->stream == stream) 744 return pipe; 745 } 746 747 return NULL; 748 } 749 750 void dc_stream_log(const struct dc *dc, const struct dc_stream_state *stream) 751 { 752 DC_LOG_DC( 753 "core_stream 0x%p: src: %d, %d, %d, %d; dst: %d, %d, %d, %d, colorSpace:%d\n", 754 stream, 755 stream->src.x, 756 stream->src.y, 757 stream->src.width, 758 stream->src.height, 759 stream->dst.x, 760 stream->dst.y, 761 stream->dst.width, 762 stream->dst.height, 763 stream->output_color_space); 764 DC_LOG_DC( 765 "\tpix_clk_khz: %d, h_total: %d, v_total: %d, pixelencoder:%d, displaycolorDepth:%d\n", 766 stream->timing.pix_clk_100hz / 10, 767 stream->timing.h_total, 768 stream->timing.v_total, 769 stream->timing.pixel_encoding, 770 stream->timing.display_color_depth); 771 DC_LOG_DC( 772 "\tlink: %d\n", 773 stream->link->link_index); 774 775 DC_LOG_DC( 776 "\tdsc: %d, mst_pbn: %d\n", 777 stream->timing.flags.DSC, 778 stream->timing.dsc_cfg.mst_pbn); 779 780 if (stream->sink) { 781 if (stream->sink->sink_signal != SIGNAL_TYPE_VIRTUAL && 782 stream->sink->sink_signal != SIGNAL_TYPE_NONE) { 783 784 DC_LOG_DC( 785 "\tdispname: %s signal: %x\n", 786 stream->sink->edid_caps.display_name, 787 stream->signal); 788 } 789 } 790 } 791 792