1 /* 2 * Copyright 2012-15 Advanced Micro Devices, Inc. 3 * 4 * Permission is hereby granted, free of charge, to any person obtaining a 5 * copy of this software and associated documentation files (the "Software"), 6 * to deal in the Software without restriction, including without limitation 7 * the rights to use, copy, modify, merge, publish, distribute, sublicense, 8 * and/or sell copies of the Software, and to permit persons to whom the 9 * Software is furnished to do so, subject to the following conditions: 10 * 11 * The above copyright notice and this permission notice shall be included in 12 * all copies or substantial portions of the Software. 13 * 14 * THE SOFTWARE IS PROVIDED "AS IS", WITHOUT WARRANTY OF ANY KIND, EXPRESS OR 15 * IMPLIED, INCLUDING BUT NOT LIMITED TO THE WARRANTIES OF MERCHANTABILITY, 16 * FITNESS FOR A PARTICULAR PURPOSE AND NONINFRINGEMENT. IN NO EVENT SHALL 17 * THE COPYRIGHT HOLDER(S) OR AUTHOR(S) BE LIABLE FOR ANY CLAIM, DAMAGES OR 18 * OTHER LIABILITY, WHETHER IN AN ACTION OF CONTRACT, TORT OR OTHERWISE, 19 * ARISING FROM, OUT OF OR IN CONNECTION WITH THE SOFTWARE OR THE USE OR 20 * OTHER DEALINGS IN THE SOFTWARE. 21 * 22 * Authors: AMD 23 * 24 */ 25 26 #include <linux/delay.h> 27 #include <linux/slab.h> 28 29 #include "dm_services.h" 30 #include "basics/dc_common.h" 31 #include "dc.h" 32 #include "core_types.h" 33 #include "resource.h" 34 #include "ipp.h" 35 #include "timing_generator.h" 36 37 #define DC_LOGGER dc->ctx->logger 38 39 /******************************************************************************* 40 * Private functions 41 ******************************************************************************/ 42 void update_stream_signal(struct dc_stream_state *stream, struct dc_sink *sink) 43 { 44 if (sink->sink_signal == SIGNAL_TYPE_NONE) 45 stream->signal = stream->link->connector_signal; 46 else 47 stream->signal = sink->sink_signal; 48 49 if (dc_is_dvi_signal(stream->signal)) { 50 if (stream->ctx->dc->caps.dual_link_dvi && 51 (stream->timing.pix_clk_100hz / 10) > TMDS_MAX_PIXEL_CLOCK && 52 sink->sink_signal != SIGNAL_TYPE_DVI_SINGLE_LINK) 53 stream->signal = SIGNAL_TYPE_DVI_DUAL_LINK; 54 else 55 stream->signal = SIGNAL_TYPE_DVI_SINGLE_LINK; 56 } 57 } 58 59 static bool dc_stream_construct(struct dc_stream_state *stream, 60 struct dc_sink *dc_sink_data) 61 { 62 uint32_t i = 0; 63 64 stream->sink = dc_sink_data; 65 dc_sink_retain(dc_sink_data); 66 67 stream->ctx = dc_sink_data->ctx; 68 stream->link = dc_sink_data->link; 69 stream->sink_patches = dc_sink_data->edid_caps.panel_patch; 70 stream->converter_disable_audio = dc_sink_data->converter_disable_audio; 71 stream->qs_bit = dc_sink_data->edid_caps.qs_bit; 72 stream->qy_bit = dc_sink_data->edid_caps.qy_bit; 73 74 /* Copy audio modes */ 75 /* TODO - Remove this translation */ 76 for (i = 0; i < (dc_sink_data->edid_caps.audio_mode_count); i++) 77 { 78 stream->audio_info.modes[i].channel_count = dc_sink_data->edid_caps.audio_modes[i].channel_count; 79 stream->audio_info.modes[i].format_code = dc_sink_data->edid_caps.audio_modes[i].format_code; 80 stream->audio_info.modes[i].sample_rates.all = dc_sink_data->edid_caps.audio_modes[i].sample_rate; 81 stream->audio_info.modes[i].sample_size = dc_sink_data->edid_caps.audio_modes[i].sample_size; 82 } 83 stream->audio_info.mode_count = dc_sink_data->edid_caps.audio_mode_count; 84 stream->audio_info.audio_latency = dc_sink_data->edid_caps.audio_latency; 85 stream->audio_info.video_latency = dc_sink_data->edid_caps.video_latency; 86 memmove( 87 stream->audio_info.display_name, 88 dc_sink_data->edid_caps.display_name, 89 AUDIO_INFO_DISPLAY_NAME_SIZE_IN_CHARS); 90 stream->audio_info.manufacture_id = dc_sink_data->edid_caps.manufacturer_id; 91 stream->audio_info.product_id = dc_sink_data->edid_caps.product_id; 92 stream->audio_info.flags.all = dc_sink_data->edid_caps.speaker_flags; 93 94 if (dc_sink_data->dc_container_id != NULL) { 95 struct dc_container_id *dc_container_id = dc_sink_data->dc_container_id; 96 97 stream->audio_info.port_id[0] = dc_container_id->portId[0]; 98 stream->audio_info.port_id[1] = dc_container_id->portId[1]; 99 } else { 100 /* TODO - WindowDM has implemented, 101 other DMs need Unhardcode port_id */ 102 stream->audio_info.port_id[0] = 0x5558859e; 103 stream->audio_info.port_id[1] = 0xd989449; 104 } 105 106 /* EDID CAP translation for HDMI 2.0 */ 107 stream->timing.flags.LTE_340MCSC_SCRAMBLE = dc_sink_data->edid_caps.lte_340mcsc_scramble; 108 109 memset(&stream->timing.dsc_cfg, 0, sizeof(stream->timing.dsc_cfg)); 110 stream->timing.dsc_cfg.num_slices_h = 0; 111 stream->timing.dsc_cfg.num_slices_v = 0; 112 stream->timing.dsc_cfg.bits_per_pixel = 128; 113 stream->timing.dsc_cfg.block_pred_enable = 1; 114 stream->timing.dsc_cfg.linebuf_depth = 9; 115 stream->timing.dsc_cfg.version_minor = 2; 116 stream->timing.dsc_cfg.ycbcr422_simple = 0; 117 118 update_stream_signal(stream, dc_sink_data); 119 120 stream->out_transfer_func = dc_create_transfer_func(); 121 if (stream->out_transfer_func == NULL) { 122 dc_sink_release(dc_sink_data); 123 return false; 124 } 125 stream->out_transfer_func->type = TF_TYPE_BYPASS; 126 127 stream->stream_id = stream->ctx->dc_stream_id_count; 128 stream->ctx->dc_stream_id_count++; 129 130 return true; 131 } 132 133 static void dc_stream_destruct(struct dc_stream_state *stream) 134 { 135 dc_sink_release(stream->sink); 136 if (stream->out_transfer_func != NULL) { 137 dc_transfer_func_release(stream->out_transfer_func); 138 stream->out_transfer_func = NULL; 139 } 140 } 141 142 void dc_stream_retain(struct dc_stream_state *stream) 143 { 144 kref_get(&stream->refcount); 145 } 146 147 static void dc_stream_free(struct kref *kref) 148 { 149 struct dc_stream_state *stream = container_of(kref, struct dc_stream_state, refcount); 150 151 dc_stream_destruct(stream); 152 kfree(stream); 153 } 154 155 void dc_stream_release(struct dc_stream_state *stream) 156 { 157 if (stream != NULL) { 158 kref_put(&stream->refcount, dc_stream_free); 159 } 160 } 161 162 struct dc_stream_state *dc_create_stream_for_sink( 163 struct dc_sink *sink) 164 { 165 struct dc_stream_state *stream; 166 167 if (sink == NULL) 168 return NULL; 169 170 stream = kzalloc(sizeof(struct dc_stream_state), GFP_KERNEL); 171 if (stream == NULL) 172 goto alloc_fail; 173 174 if (dc_stream_construct(stream, sink) == false) 175 goto construct_fail; 176 177 kref_init(&stream->refcount); 178 179 return stream; 180 181 construct_fail: 182 kfree(stream); 183 184 alloc_fail: 185 return NULL; 186 } 187 188 struct dc_stream_state *dc_copy_stream(const struct dc_stream_state *stream) 189 { 190 struct dc_stream_state *new_stream; 191 192 new_stream = kmemdup(stream, sizeof(struct dc_stream_state), GFP_KERNEL); 193 if (!new_stream) 194 return NULL; 195 196 if (new_stream->sink) 197 dc_sink_retain(new_stream->sink); 198 199 if (new_stream->out_transfer_func) 200 dc_transfer_func_retain(new_stream->out_transfer_func); 201 202 new_stream->stream_id = new_stream->ctx->dc_stream_id_count; 203 new_stream->ctx->dc_stream_id_count++; 204 205 /* If using dynamic encoder assignment, wait till stream committed to assign encoder. */ 206 if (new_stream->ctx->dc->res_pool->funcs->link_encs_assign) 207 new_stream->link_enc = NULL; 208 209 kref_init(&new_stream->refcount); 210 211 return new_stream; 212 } 213 214 /** 215 * dc_stream_get_status_from_state - Get stream status from given dc state 216 * @state: DC state to find the stream status in 217 * @stream: The stream to get the stream status for 218 * 219 * The given stream is expected to exist in the given dc state. Otherwise, NULL 220 * will be returned. 221 */ 222 struct dc_stream_status *dc_stream_get_status_from_state( 223 struct dc_state *state, 224 struct dc_stream_state *stream) 225 { 226 uint8_t i; 227 228 if (state == NULL) 229 return NULL; 230 231 for (i = 0; i < state->stream_count; i++) { 232 if (stream == state->streams[i]) 233 return &state->stream_status[i]; 234 } 235 236 return NULL; 237 } 238 239 /** 240 * dc_stream_get_status() - Get current stream status of the given stream state 241 * @stream: The stream to get the stream status for. 242 * 243 * The given stream is expected to exist in dc->current_state. Otherwise, NULL 244 * will be returned. 245 */ 246 struct dc_stream_status *dc_stream_get_status( 247 struct dc_stream_state *stream) 248 { 249 struct dc *dc = stream->ctx->dc; 250 return dc_stream_get_status_from_state(dc->current_state, stream); 251 } 252 253 static void program_cursor_attributes( 254 struct dc *dc, 255 struct dc_stream_state *stream, 256 const struct dc_cursor_attributes *attributes) 257 { 258 int i; 259 struct resource_context *res_ctx; 260 struct pipe_ctx *pipe_to_program = NULL; 261 262 if (!stream) 263 return; 264 265 res_ctx = &dc->current_state->res_ctx; 266 267 for (i = 0; i < MAX_PIPES; i++) { 268 struct pipe_ctx *pipe_ctx = &res_ctx->pipe_ctx[i]; 269 270 if (pipe_ctx->stream != stream) 271 continue; 272 273 if (!pipe_to_program) { 274 pipe_to_program = pipe_ctx; 275 dc->hwss.cursor_lock(dc, pipe_to_program, true); 276 } 277 278 dc->hwss.set_cursor_attribute(pipe_ctx); 279 if (dc->hwss.set_cursor_sdr_white_level) 280 dc->hwss.set_cursor_sdr_white_level(pipe_ctx); 281 } 282 283 if (pipe_to_program) 284 dc->hwss.cursor_lock(dc, pipe_to_program, false); 285 } 286 287 #ifndef TRIM_FSFT 288 /* 289 * dc_optimize_timing_for_fsft() - dc to optimize timing 290 */ 291 bool dc_optimize_timing_for_fsft( 292 struct dc_stream_state *pStream, 293 unsigned int max_input_rate_in_khz) 294 { 295 struct dc *dc; 296 297 dc = pStream->ctx->dc; 298 299 return (dc->hwss.optimize_timing_for_fsft && 300 dc->hwss.optimize_timing_for_fsft(dc, &pStream->timing, max_input_rate_in_khz)); 301 } 302 #endif 303 304 /* 305 * dc_stream_set_cursor_attributes() - Update cursor attributes and set cursor surface address 306 */ 307 bool dc_stream_set_cursor_attributes( 308 struct dc_stream_state *stream, 309 const struct dc_cursor_attributes *attributes) 310 { 311 struct dc *dc; 312 #if defined(CONFIG_DRM_AMD_DC_DCN) 313 bool reset_idle_optimizations = false; 314 #endif 315 316 if (NULL == stream) { 317 dm_error("DC: dc_stream is NULL!\n"); 318 return false; 319 } 320 if (NULL == attributes) { 321 dm_error("DC: attributes is NULL!\n"); 322 return false; 323 } 324 325 if (attributes->address.quad_part == 0) { 326 dm_output_to_console("DC: Cursor address is 0!\n"); 327 return false; 328 } 329 330 dc = stream->ctx->dc; 331 stream->cursor_attributes = *attributes; 332 333 #if defined(CONFIG_DRM_AMD_DC_DCN) 334 dc_z10_restore(dc); 335 /* disable idle optimizations while updating cursor */ 336 if (dc->idle_optimizations_allowed) { 337 dc_allow_idle_optimizations(dc, false); 338 reset_idle_optimizations = true; 339 } 340 341 #endif 342 program_cursor_attributes(dc, stream, attributes); 343 344 #if defined(CONFIG_DRM_AMD_DC_DCN) 345 /* re-enable idle optimizations if necessary */ 346 if (reset_idle_optimizations) 347 dc_allow_idle_optimizations(dc, true); 348 349 #endif 350 return true; 351 } 352 353 static void program_cursor_position( 354 struct dc *dc, 355 struct dc_stream_state *stream, 356 const struct dc_cursor_position *position) 357 { 358 int i; 359 struct resource_context *res_ctx; 360 struct pipe_ctx *pipe_to_program = NULL; 361 362 if (!stream) 363 return; 364 365 res_ctx = &dc->current_state->res_ctx; 366 367 for (i = 0; i < MAX_PIPES; i++) { 368 struct pipe_ctx *pipe_ctx = &res_ctx->pipe_ctx[i]; 369 370 if (pipe_ctx->stream != stream || 371 (!pipe_ctx->plane_res.mi && !pipe_ctx->plane_res.hubp) || 372 !pipe_ctx->plane_state || 373 (!pipe_ctx->plane_res.xfm && !pipe_ctx->plane_res.dpp) || 374 (!pipe_ctx->plane_res.ipp && !pipe_ctx->plane_res.dpp)) 375 continue; 376 377 if (!pipe_to_program) { 378 pipe_to_program = pipe_ctx; 379 dc->hwss.cursor_lock(dc, pipe_to_program, true); 380 } 381 382 dc->hwss.set_cursor_position(pipe_ctx); 383 } 384 385 if (pipe_to_program) 386 dc->hwss.cursor_lock(dc, pipe_to_program, false); 387 } 388 389 bool dc_stream_set_cursor_position( 390 struct dc_stream_state *stream, 391 const struct dc_cursor_position *position) 392 { 393 struct dc *dc; 394 #if defined(CONFIG_DRM_AMD_DC_DCN) 395 bool reset_idle_optimizations = false; 396 #endif 397 398 if (NULL == stream) { 399 dm_error("DC: dc_stream is NULL!\n"); 400 return false; 401 } 402 403 if (NULL == position) { 404 dm_error("DC: cursor position is NULL!\n"); 405 return false; 406 } 407 408 dc = stream->ctx->dc; 409 #if defined(CONFIG_DRM_AMD_DC_DCN) 410 dc_z10_restore(dc); 411 412 /* disable idle optimizations if enabling cursor */ 413 if (dc->idle_optimizations_allowed && !stream->cursor_position.enable && position->enable) { 414 dc_allow_idle_optimizations(dc, false); 415 reset_idle_optimizations = true; 416 } 417 418 #endif 419 stream->cursor_position = *position; 420 421 program_cursor_position(dc, stream, position); 422 #if defined(CONFIG_DRM_AMD_DC_DCN) 423 /* re-enable idle optimizations if necessary */ 424 if (reset_idle_optimizations) 425 dc_allow_idle_optimizations(dc, true); 426 427 #endif 428 return true; 429 } 430 431 bool dc_stream_add_writeback(struct dc *dc, 432 struct dc_stream_state *stream, 433 struct dc_writeback_info *wb_info) 434 { 435 bool isDrc = false; 436 int i = 0; 437 struct dwbc *dwb; 438 439 if (stream == NULL) { 440 dm_error("DC: dc_stream is NULL!\n"); 441 return false; 442 } 443 444 if (wb_info == NULL) { 445 dm_error("DC: dc_writeback_info is NULL!\n"); 446 return false; 447 } 448 449 if (wb_info->dwb_pipe_inst >= MAX_DWB_PIPES) { 450 dm_error("DC: writeback pipe is invalid!\n"); 451 return false; 452 } 453 454 wb_info->dwb_params.out_transfer_func = stream->out_transfer_func; 455 456 dwb = dc->res_pool->dwbc[wb_info->dwb_pipe_inst]; 457 dwb->dwb_is_drc = false; 458 459 /* recalculate and apply DML parameters */ 460 461 for (i = 0; i < stream->num_wb_info; i++) { 462 /*dynamic update*/ 463 if (stream->writeback_info[i].wb_enabled && 464 stream->writeback_info[i].dwb_pipe_inst == wb_info->dwb_pipe_inst) { 465 stream->writeback_info[i] = *wb_info; 466 isDrc = true; 467 } 468 } 469 470 if (!isDrc) { 471 stream->writeback_info[stream->num_wb_info++] = *wb_info; 472 } 473 474 if (dc->hwss.enable_writeback) { 475 struct dc_stream_status *stream_status = dc_stream_get_status(stream); 476 struct dwbc *dwb = dc->res_pool->dwbc[wb_info->dwb_pipe_inst]; 477 dwb->otg_inst = stream_status->primary_otg_inst; 478 } 479 if (IS_DIAG_DC(dc->ctx->dce_environment)) { 480 if (!dc->hwss.update_bandwidth(dc, dc->current_state)) { 481 dm_error("DC: update_bandwidth failed!\n"); 482 return false; 483 } 484 485 /* enable writeback */ 486 if (dc->hwss.enable_writeback) { 487 struct dwbc *dwb = dc->res_pool->dwbc[wb_info->dwb_pipe_inst]; 488 489 if (dwb->funcs->is_enabled(dwb)) { 490 /* writeback pipe already enabled, only need to update */ 491 dc->hwss.update_writeback(dc, wb_info, dc->current_state); 492 } else { 493 /* Enable writeback pipe from scratch*/ 494 dc->hwss.enable_writeback(dc, wb_info, dc->current_state); 495 } 496 } 497 } 498 return true; 499 } 500 501 bool dc_stream_remove_writeback(struct dc *dc, 502 struct dc_stream_state *stream, 503 uint32_t dwb_pipe_inst) 504 { 505 int i = 0, j = 0; 506 if (stream == NULL) { 507 dm_error("DC: dc_stream is NULL!\n"); 508 return false; 509 } 510 511 if (dwb_pipe_inst >= MAX_DWB_PIPES) { 512 dm_error("DC: writeback pipe is invalid!\n"); 513 return false; 514 } 515 516 // stream->writeback_info[dwb_pipe_inst].wb_enabled = false; 517 for (i = 0; i < stream->num_wb_info; i++) { 518 /*dynamic update*/ 519 if (stream->writeback_info[i].wb_enabled && 520 stream->writeback_info[i].dwb_pipe_inst == dwb_pipe_inst) { 521 stream->writeback_info[i].wb_enabled = false; 522 } 523 } 524 525 /* remove writeback info for disabled writeback pipes from stream */ 526 for (i = 0, j = 0; i < stream->num_wb_info; i++) { 527 if (stream->writeback_info[i].wb_enabled) { 528 if (i != j) 529 /* trim the array */ 530 stream->writeback_info[j] = stream->writeback_info[i]; 531 j++; 532 } 533 } 534 stream->num_wb_info = j; 535 536 if (IS_DIAG_DC(dc->ctx->dce_environment)) { 537 /* recalculate and apply DML parameters */ 538 if (!dc->hwss.update_bandwidth(dc, dc->current_state)) { 539 dm_error("DC: update_bandwidth failed!\n"); 540 return false; 541 } 542 543 /* disable writeback */ 544 if (dc->hwss.disable_writeback) 545 dc->hwss.disable_writeback(dc, dwb_pipe_inst); 546 } 547 return true; 548 } 549 550 bool dc_stream_warmup_writeback(struct dc *dc, 551 int num_dwb, 552 struct dc_writeback_info *wb_info) 553 { 554 if (dc->hwss.mmhubbub_warmup) 555 return dc->hwss.mmhubbub_warmup(dc, num_dwb, wb_info); 556 else 557 return false; 558 } 559 uint32_t dc_stream_get_vblank_counter(const struct dc_stream_state *stream) 560 { 561 uint8_t i; 562 struct dc *dc = stream->ctx->dc; 563 struct resource_context *res_ctx = 564 &dc->current_state->res_ctx; 565 566 for (i = 0; i < MAX_PIPES; i++) { 567 struct timing_generator *tg = res_ctx->pipe_ctx[i].stream_res.tg; 568 569 if (res_ctx->pipe_ctx[i].stream != stream) 570 continue; 571 572 return tg->funcs->get_frame_count(tg); 573 } 574 575 return 0; 576 } 577 578 bool dc_stream_send_dp_sdp(const struct dc_stream_state *stream, 579 const uint8_t *custom_sdp_message, 580 unsigned int sdp_message_size) 581 { 582 int i; 583 struct dc *dc; 584 struct resource_context *res_ctx; 585 586 if (stream == NULL) { 587 dm_error("DC: dc_stream is NULL!\n"); 588 return false; 589 } 590 591 dc = stream->ctx->dc; 592 res_ctx = &dc->current_state->res_ctx; 593 594 for (i = 0; i < MAX_PIPES; i++) { 595 struct pipe_ctx *pipe_ctx = &res_ctx->pipe_ctx[i]; 596 597 if (pipe_ctx->stream != stream) 598 continue; 599 600 if (dc->hwss.send_immediate_sdp_message != NULL) 601 dc->hwss.send_immediate_sdp_message(pipe_ctx, 602 custom_sdp_message, 603 sdp_message_size); 604 else 605 DC_LOG_WARNING("%s:send_immediate_sdp_message not implemented on this ASIC\n", 606 __func__); 607 608 } 609 610 return true; 611 } 612 613 bool dc_stream_get_scanoutpos(const struct dc_stream_state *stream, 614 uint32_t *v_blank_start, 615 uint32_t *v_blank_end, 616 uint32_t *h_position, 617 uint32_t *v_position) 618 { 619 uint8_t i; 620 bool ret = false; 621 struct dc *dc = stream->ctx->dc; 622 struct resource_context *res_ctx = 623 &dc->current_state->res_ctx; 624 625 for (i = 0; i < MAX_PIPES; i++) { 626 struct timing_generator *tg = res_ctx->pipe_ctx[i].stream_res.tg; 627 628 if (res_ctx->pipe_ctx[i].stream != stream) 629 continue; 630 631 tg->funcs->get_scanoutpos(tg, 632 v_blank_start, 633 v_blank_end, 634 h_position, 635 v_position); 636 637 ret = true; 638 break; 639 } 640 641 return ret; 642 } 643 644 bool dc_stream_dmdata_status_done(struct dc *dc, struct dc_stream_state *stream) 645 { 646 struct pipe_ctx *pipe = NULL; 647 int i; 648 649 if (!dc->hwss.dmdata_status_done) 650 return false; 651 652 for (i = 0; i < MAX_PIPES; i++) { 653 pipe = &dc->current_state->res_ctx.pipe_ctx[i]; 654 if (pipe->stream == stream) 655 break; 656 } 657 /* Stream not found, by default we'll assume HUBP fetched dm data */ 658 if (i == MAX_PIPES) 659 return true; 660 661 return dc->hwss.dmdata_status_done(pipe); 662 } 663 664 bool dc_stream_set_dynamic_metadata(struct dc *dc, 665 struct dc_stream_state *stream, 666 struct dc_dmdata_attributes *attr) 667 { 668 struct pipe_ctx *pipe_ctx = NULL; 669 struct hubp *hubp; 670 int i; 671 672 /* Dynamic metadata is only supported on HDMI or DP */ 673 if (!dc_is_hdmi_signal(stream->signal) && !dc_is_dp_signal(stream->signal)) 674 return false; 675 676 /* Check hardware support */ 677 if (!dc->hwss.program_dmdata_engine) 678 return false; 679 680 for (i = 0; i < MAX_PIPES; i++) { 681 pipe_ctx = &dc->current_state->res_ctx.pipe_ctx[i]; 682 if (pipe_ctx->stream == stream) 683 break; 684 } 685 686 if (i == MAX_PIPES) 687 return false; 688 689 hubp = pipe_ctx->plane_res.hubp; 690 if (hubp == NULL) 691 return false; 692 693 pipe_ctx->stream->dmdata_address = attr->address; 694 695 dc->hwss.program_dmdata_engine(pipe_ctx); 696 697 if (hubp->funcs->dmdata_set_attributes != NULL && 698 pipe_ctx->stream->dmdata_address.quad_part != 0) { 699 hubp->funcs->dmdata_set_attributes(hubp, attr); 700 } 701 702 return true; 703 } 704 705 enum dc_status dc_stream_add_dsc_to_resource(struct dc *dc, 706 struct dc_state *state, 707 struct dc_stream_state *stream) 708 { 709 if (dc->res_pool->funcs->add_dsc_to_stream_resource) { 710 return dc->res_pool->funcs->add_dsc_to_stream_resource(dc, state, stream); 711 } else { 712 return DC_NO_DSC_RESOURCE; 713 } 714 } 715 716 void dc_stream_log(const struct dc *dc, const struct dc_stream_state *stream) 717 { 718 DC_LOG_DC( 719 "core_stream 0x%p: src: %d, %d, %d, %d; dst: %d, %d, %d, %d, colorSpace:%d\n", 720 stream, 721 stream->src.x, 722 stream->src.y, 723 stream->src.width, 724 stream->src.height, 725 stream->dst.x, 726 stream->dst.y, 727 stream->dst.width, 728 stream->dst.height, 729 stream->output_color_space); 730 DC_LOG_DC( 731 "\tpix_clk_khz: %d, h_total: %d, v_total: %d, pixelencoder:%d, displaycolorDepth:%d\n", 732 stream->timing.pix_clk_100hz / 10, 733 stream->timing.h_total, 734 stream->timing.v_total, 735 stream->timing.pixel_encoding, 736 stream->timing.display_color_depth); 737 DC_LOG_DC( 738 "\tlink: %d\n", 739 stream->link->link_index); 740 } 741 742