1 /* 2 * Copyright 2012-15 Advanced Micro Devices, Inc. 3 * 4 * Permission is hereby granted, free of charge, to any person obtaining a 5 * copy of this software and associated documentation files (the "Software"), 6 * to deal in the Software without restriction, including without limitation 7 * the rights to use, copy, modify, merge, publish, distribute, sublicense, 8 * and/or sell copies of the Software, and to permit persons to whom the 9 * Software is furnished to do so, subject to the following conditions: 10 * 11 * The above copyright notice and this permission notice shall be included in 12 * all copies or substantial portions of the Software. 13 * 14 * THE SOFTWARE IS PROVIDED "AS IS", WITHOUT WARRANTY OF ANY KIND, EXPRESS OR 15 * IMPLIED, INCLUDING BUT NOT LIMITED TO THE WARRANTIES OF MERCHANTABILITY, 16 * FITNESS FOR A PARTICULAR PURPOSE AND NONINFRINGEMENT. IN NO EVENT SHALL 17 * THE COPYRIGHT HOLDER(S) OR AUTHOR(S) BE LIABLE FOR ANY CLAIM, DAMAGES OR 18 * OTHER LIABILITY, WHETHER IN AN ACTION OF CONTRACT, TORT OR OTHERWISE, 19 * ARISING FROM, OUT OF OR IN CONNECTION WITH THE SOFTWARE OR THE USE OR 20 * OTHER DEALINGS IN THE SOFTWARE. 21 * 22 * Authors: AMD 23 * 24 */ 25 26 #include "dm_services.h" 27 #include "basics/dc_common.h" 28 #include "dc.h" 29 #include "core_types.h" 30 #include "resource.h" 31 #include "ipp.h" 32 #include "timing_generator.h" 33 #include "dc_dmub_srv.h" 34 35 #define DC_LOGGER dc->ctx->logger 36 37 /******************************************************************************* 38 * Private functions 39 ******************************************************************************/ 40 void update_stream_signal(struct dc_stream_state *stream, struct dc_sink *sink) 41 { 42 if (sink->sink_signal == SIGNAL_TYPE_NONE) 43 stream->signal = stream->link->connector_signal; 44 else 45 stream->signal = sink->sink_signal; 46 47 if (dc_is_dvi_signal(stream->signal)) { 48 if (stream->ctx->dc->caps.dual_link_dvi && 49 (stream->timing.pix_clk_100hz / 10) > TMDS_MAX_PIXEL_CLOCK && 50 sink->sink_signal != SIGNAL_TYPE_DVI_SINGLE_LINK) 51 stream->signal = SIGNAL_TYPE_DVI_DUAL_LINK; 52 else 53 stream->signal = SIGNAL_TYPE_DVI_SINGLE_LINK; 54 } 55 } 56 57 static bool dc_stream_construct(struct dc_stream_state *stream, 58 struct dc_sink *dc_sink_data) 59 { 60 uint32_t i = 0; 61 62 stream->sink = dc_sink_data; 63 dc_sink_retain(dc_sink_data); 64 65 stream->ctx = dc_sink_data->ctx; 66 stream->link = dc_sink_data->link; 67 stream->sink_patches = dc_sink_data->edid_caps.panel_patch; 68 stream->converter_disable_audio = dc_sink_data->converter_disable_audio; 69 stream->qs_bit = dc_sink_data->edid_caps.qs_bit; 70 stream->qy_bit = dc_sink_data->edid_caps.qy_bit; 71 72 /* Copy audio modes */ 73 /* TODO - Remove this translation */ 74 for (i = 0; i < (dc_sink_data->edid_caps.audio_mode_count); i++) 75 { 76 stream->audio_info.modes[i].channel_count = dc_sink_data->edid_caps.audio_modes[i].channel_count; 77 stream->audio_info.modes[i].format_code = dc_sink_data->edid_caps.audio_modes[i].format_code; 78 stream->audio_info.modes[i].sample_rates.all = dc_sink_data->edid_caps.audio_modes[i].sample_rate; 79 stream->audio_info.modes[i].sample_size = dc_sink_data->edid_caps.audio_modes[i].sample_size; 80 } 81 stream->audio_info.mode_count = dc_sink_data->edid_caps.audio_mode_count; 82 stream->audio_info.audio_latency = dc_sink_data->edid_caps.audio_latency; 83 stream->audio_info.video_latency = dc_sink_data->edid_caps.video_latency; 84 memmove( 85 stream->audio_info.display_name, 86 dc_sink_data->edid_caps.display_name, 87 AUDIO_INFO_DISPLAY_NAME_SIZE_IN_CHARS); 88 stream->audio_info.manufacture_id = dc_sink_data->edid_caps.manufacturer_id; 89 stream->audio_info.product_id = dc_sink_data->edid_caps.product_id; 90 stream->audio_info.flags.all = dc_sink_data->edid_caps.speaker_flags; 91 92 if (dc_sink_data->dc_container_id != NULL) { 93 struct dc_container_id *dc_container_id = dc_sink_data->dc_container_id; 94 95 stream->audio_info.port_id[0] = dc_container_id->portId[0]; 96 stream->audio_info.port_id[1] = dc_container_id->portId[1]; 97 } else { 98 /* TODO - WindowDM has implemented, 99 other DMs need Unhardcode port_id */ 100 stream->audio_info.port_id[0] = 0x5558859e; 101 stream->audio_info.port_id[1] = 0xd989449; 102 } 103 104 /* EDID CAP translation for HDMI 2.0 */ 105 stream->timing.flags.LTE_340MCSC_SCRAMBLE = dc_sink_data->edid_caps.lte_340mcsc_scramble; 106 107 memset(&stream->timing.dsc_cfg, 0, sizeof(stream->timing.dsc_cfg)); 108 stream->timing.dsc_cfg.num_slices_h = 0; 109 stream->timing.dsc_cfg.num_slices_v = 0; 110 stream->timing.dsc_cfg.bits_per_pixel = 128; 111 stream->timing.dsc_cfg.block_pred_enable = 1; 112 stream->timing.dsc_cfg.linebuf_depth = 9; 113 stream->timing.dsc_cfg.version_minor = 2; 114 stream->timing.dsc_cfg.ycbcr422_simple = 0; 115 116 update_stream_signal(stream, dc_sink_data); 117 118 stream->out_transfer_func = dc_create_transfer_func(); 119 if (stream->out_transfer_func == NULL) { 120 dc_sink_release(dc_sink_data); 121 return false; 122 } 123 stream->out_transfer_func->type = TF_TYPE_BYPASS; 124 125 stream->stream_id = stream->ctx->dc_stream_id_count; 126 stream->ctx->dc_stream_id_count++; 127 128 return true; 129 } 130 131 static void dc_stream_destruct(struct dc_stream_state *stream) 132 { 133 dc_sink_release(stream->sink); 134 if (stream->out_transfer_func != NULL) { 135 dc_transfer_func_release(stream->out_transfer_func); 136 stream->out_transfer_func = NULL; 137 } 138 } 139 140 void dc_stream_retain(struct dc_stream_state *stream) 141 { 142 kref_get(&stream->refcount); 143 } 144 145 static void dc_stream_free(struct kref *kref) 146 { 147 struct dc_stream_state *stream = container_of(kref, struct dc_stream_state, refcount); 148 149 dc_stream_destruct(stream); 150 kfree(stream); 151 } 152 153 void dc_stream_release(struct dc_stream_state *stream) 154 { 155 if (stream != NULL) { 156 kref_put(&stream->refcount, dc_stream_free); 157 } 158 } 159 160 struct dc_stream_state *dc_create_stream_for_sink( 161 struct dc_sink *sink) 162 { 163 struct dc_stream_state *stream; 164 165 if (sink == NULL) 166 return NULL; 167 168 stream = kzalloc(sizeof(struct dc_stream_state), GFP_KERNEL); 169 if (stream == NULL) 170 goto alloc_fail; 171 172 if (dc_stream_construct(stream, sink) == false) 173 goto construct_fail; 174 175 kref_init(&stream->refcount); 176 177 return stream; 178 179 construct_fail: 180 kfree(stream); 181 182 alloc_fail: 183 return NULL; 184 } 185 186 struct dc_stream_state *dc_copy_stream(const struct dc_stream_state *stream) 187 { 188 struct dc_stream_state *new_stream; 189 190 new_stream = kmemdup(stream, sizeof(struct dc_stream_state), GFP_KERNEL); 191 if (!new_stream) 192 return NULL; 193 194 if (new_stream->sink) 195 dc_sink_retain(new_stream->sink); 196 197 if (new_stream->out_transfer_func) 198 dc_transfer_func_retain(new_stream->out_transfer_func); 199 200 new_stream->stream_id = new_stream->ctx->dc_stream_id_count; 201 new_stream->ctx->dc_stream_id_count++; 202 203 /* If using dynamic encoder assignment, wait till stream committed to assign encoder. */ 204 if (new_stream->ctx->dc->res_pool->funcs->link_encs_assign) 205 new_stream->link_enc = NULL; 206 207 kref_init(&new_stream->refcount); 208 209 return new_stream; 210 } 211 212 /** 213 * dc_stream_get_status_from_state - Get stream status from given dc state 214 * @state: DC state to find the stream status in 215 * @stream: The stream to get the stream status for 216 * 217 * The given stream is expected to exist in the given dc state. Otherwise, NULL 218 * will be returned. 219 */ 220 struct dc_stream_status *dc_stream_get_status_from_state( 221 struct dc_state *state, 222 struct dc_stream_state *stream) 223 { 224 uint8_t i; 225 226 if (state == NULL) 227 return NULL; 228 229 for (i = 0; i < state->stream_count; i++) { 230 if (stream == state->streams[i]) 231 return &state->stream_status[i]; 232 } 233 234 return NULL; 235 } 236 237 /** 238 * dc_stream_get_status() - Get current stream status of the given stream state 239 * @stream: The stream to get the stream status for. 240 * 241 * The given stream is expected to exist in dc->current_state. Otherwise, NULL 242 * will be returned. 243 */ 244 struct dc_stream_status *dc_stream_get_status( 245 struct dc_stream_state *stream) 246 { 247 struct dc *dc = stream->ctx->dc; 248 return dc_stream_get_status_from_state(dc->current_state, stream); 249 } 250 251 static void program_cursor_attributes( 252 struct dc *dc, 253 struct dc_stream_state *stream, 254 const struct dc_cursor_attributes *attributes) 255 { 256 int i; 257 struct resource_context *res_ctx; 258 struct pipe_ctx *pipe_to_program = NULL; 259 260 if (!stream) 261 return; 262 263 res_ctx = &dc->current_state->res_ctx; 264 265 for (i = 0; i < MAX_PIPES; i++) { 266 struct pipe_ctx *pipe_ctx = &res_ctx->pipe_ctx[i]; 267 268 if (pipe_ctx->stream != stream) 269 continue; 270 271 if (!pipe_to_program) { 272 pipe_to_program = pipe_ctx; 273 dc->hwss.cursor_lock(dc, pipe_to_program, true); 274 if (pipe_to_program->next_odm_pipe) 275 dc->hwss.cursor_lock(dc, pipe_to_program->next_odm_pipe, true); 276 } 277 278 dc->hwss.set_cursor_attribute(pipe_ctx); 279 280 dc_send_update_cursor_info_to_dmu(pipe_ctx, i); 281 if (dc->hwss.set_cursor_sdr_white_level) 282 dc->hwss.set_cursor_sdr_white_level(pipe_ctx); 283 } 284 285 if (pipe_to_program) { 286 dc->hwss.cursor_lock(dc, pipe_to_program, false); 287 if (pipe_to_program->next_odm_pipe) 288 dc->hwss.cursor_lock(dc, pipe_to_program->next_odm_pipe, false); 289 } 290 } 291 292 #ifndef TRIM_FSFT 293 /* 294 * dc_optimize_timing_for_fsft() - dc to optimize timing 295 */ 296 bool dc_optimize_timing_for_fsft( 297 struct dc_stream_state *pStream, 298 unsigned int max_input_rate_in_khz) 299 { 300 struct dc *dc; 301 302 dc = pStream->ctx->dc; 303 304 return (dc->hwss.optimize_timing_for_fsft && 305 dc->hwss.optimize_timing_for_fsft(dc, &pStream->timing, max_input_rate_in_khz)); 306 } 307 #endif 308 309 /* 310 * dc_stream_set_cursor_attributes() - Update cursor attributes and set cursor surface address 311 */ 312 bool dc_stream_set_cursor_attributes( 313 struct dc_stream_state *stream, 314 const struct dc_cursor_attributes *attributes) 315 { 316 struct dc *dc; 317 bool reset_idle_optimizations = false; 318 319 if (NULL == stream) { 320 dm_error("DC: dc_stream is NULL!\n"); 321 return false; 322 } 323 if (NULL == attributes) { 324 dm_error("DC: attributes is NULL!\n"); 325 return false; 326 } 327 328 if (attributes->address.quad_part == 0) { 329 dm_output_to_console("DC: Cursor address is 0!\n"); 330 return false; 331 } 332 333 dc = stream->ctx->dc; 334 335 if (dc->debug.allow_sw_cursor_fallback && attributes->height * attributes->width * 4 > 16384) 336 if (stream->mall_stream_config.type == SUBVP_MAIN) 337 return false; 338 339 stream->cursor_attributes = *attributes; 340 341 dc_z10_restore(dc); 342 /* disable idle optimizations while updating cursor */ 343 if (dc->idle_optimizations_allowed) { 344 dc_allow_idle_optimizations(dc, false); 345 reset_idle_optimizations = true; 346 } 347 348 program_cursor_attributes(dc, stream, attributes); 349 350 /* re-enable idle optimizations if necessary */ 351 if (reset_idle_optimizations) 352 dc_allow_idle_optimizations(dc, true); 353 354 return true; 355 } 356 357 static void program_cursor_position( 358 struct dc *dc, 359 struct dc_stream_state *stream, 360 const struct dc_cursor_position *position) 361 { 362 int i; 363 struct resource_context *res_ctx; 364 struct pipe_ctx *pipe_to_program = NULL; 365 366 if (!stream) 367 return; 368 369 res_ctx = &dc->current_state->res_ctx; 370 371 for (i = 0; i < MAX_PIPES; i++) { 372 struct pipe_ctx *pipe_ctx = &res_ctx->pipe_ctx[i]; 373 374 if (pipe_ctx->stream != stream || 375 (!pipe_ctx->plane_res.mi && !pipe_ctx->plane_res.hubp) || 376 !pipe_ctx->plane_state || 377 (!pipe_ctx->plane_res.xfm && !pipe_ctx->plane_res.dpp) || 378 (!pipe_ctx->plane_res.ipp && !pipe_ctx->plane_res.dpp)) 379 continue; 380 381 if (!pipe_to_program) { 382 pipe_to_program = pipe_ctx; 383 dc->hwss.cursor_lock(dc, pipe_to_program, true); 384 } 385 386 dc->hwss.set_cursor_position(pipe_ctx); 387 388 dc_send_update_cursor_info_to_dmu(pipe_ctx, i); 389 } 390 391 if (pipe_to_program) 392 dc->hwss.cursor_lock(dc, pipe_to_program, false); 393 } 394 395 bool dc_stream_set_cursor_position( 396 struct dc_stream_state *stream, 397 const struct dc_cursor_position *position) 398 { 399 struct dc *dc = stream->ctx->dc; 400 bool reset_idle_optimizations = false; 401 402 if (NULL == stream) { 403 dm_error("DC: dc_stream is NULL!\n"); 404 return false; 405 } 406 407 if (NULL == position) { 408 dm_error("DC: cursor position is NULL!\n"); 409 return false; 410 } 411 412 dc = stream->ctx->dc; 413 dc_z10_restore(dc); 414 415 /* disable idle optimizations if enabling cursor */ 416 if (dc->idle_optimizations_allowed && (!stream->cursor_position.enable || dc->debug.exit_idle_opt_for_cursor_updates) 417 && position->enable) { 418 dc_allow_idle_optimizations(dc, false); 419 reset_idle_optimizations = true; 420 } 421 422 stream->cursor_position = *position; 423 424 program_cursor_position(dc, stream, position); 425 /* re-enable idle optimizations if necessary */ 426 if (reset_idle_optimizations) 427 dc_allow_idle_optimizations(dc, true); 428 429 return true; 430 } 431 432 bool dc_stream_add_writeback(struct dc *dc, 433 struct dc_stream_state *stream, 434 struct dc_writeback_info *wb_info) 435 { 436 bool isDrc = false; 437 int i = 0; 438 struct dwbc *dwb; 439 440 if (stream == NULL) { 441 dm_error("DC: dc_stream is NULL!\n"); 442 return false; 443 } 444 445 if (wb_info == NULL) { 446 dm_error("DC: dc_writeback_info is NULL!\n"); 447 return false; 448 } 449 450 if (wb_info->dwb_pipe_inst >= MAX_DWB_PIPES) { 451 dm_error("DC: writeback pipe is invalid!\n"); 452 return false; 453 } 454 455 wb_info->dwb_params.out_transfer_func = stream->out_transfer_func; 456 457 dwb = dc->res_pool->dwbc[wb_info->dwb_pipe_inst]; 458 dwb->dwb_is_drc = false; 459 460 /* recalculate and apply DML parameters */ 461 462 for (i = 0; i < stream->num_wb_info; i++) { 463 /*dynamic update*/ 464 if (stream->writeback_info[i].wb_enabled && 465 stream->writeback_info[i].dwb_pipe_inst == wb_info->dwb_pipe_inst) { 466 stream->writeback_info[i] = *wb_info; 467 isDrc = true; 468 } 469 } 470 471 if (!isDrc) { 472 stream->writeback_info[stream->num_wb_info++] = *wb_info; 473 } 474 475 if (dc->hwss.enable_writeback) { 476 struct dc_stream_status *stream_status = dc_stream_get_status(stream); 477 struct dwbc *dwb = dc->res_pool->dwbc[wb_info->dwb_pipe_inst]; 478 dwb->otg_inst = stream_status->primary_otg_inst; 479 } 480 if (IS_DIAG_DC(dc->ctx->dce_environment)) { 481 if (!dc->hwss.update_bandwidth(dc, dc->current_state)) { 482 dm_error("DC: update_bandwidth failed!\n"); 483 return false; 484 } 485 486 /* enable writeback */ 487 if (dc->hwss.enable_writeback) { 488 struct dwbc *dwb = dc->res_pool->dwbc[wb_info->dwb_pipe_inst]; 489 490 if (dwb->funcs->is_enabled(dwb)) { 491 /* writeback pipe already enabled, only need to update */ 492 dc->hwss.update_writeback(dc, wb_info, dc->current_state); 493 } else { 494 /* Enable writeback pipe from scratch*/ 495 dc->hwss.enable_writeback(dc, wb_info, dc->current_state); 496 } 497 } 498 } 499 return true; 500 } 501 502 bool dc_stream_remove_writeback(struct dc *dc, 503 struct dc_stream_state *stream, 504 uint32_t dwb_pipe_inst) 505 { 506 int i = 0, j = 0; 507 if (stream == NULL) { 508 dm_error("DC: dc_stream is NULL!\n"); 509 return false; 510 } 511 512 if (dwb_pipe_inst >= MAX_DWB_PIPES) { 513 dm_error("DC: writeback pipe is invalid!\n"); 514 return false; 515 } 516 517 // stream->writeback_info[dwb_pipe_inst].wb_enabled = false; 518 for (i = 0; i < stream->num_wb_info; i++) { 519 /*dynamic update*/ 520 if (stream->writeback_info[i].wb_enabled && 521 stream->writeback_info[i].dwb_pipe_inst == dwb_pipe_inst) { 522 stream->writeback_info[i].wb_enabled = false; 523 } 524 } 525 526 /* remove writeback info for disabled writeback pipes from stream */ 527 for (i = 0, j = 0; i < stream->num_wb_info; i++) { 528 if (stream->writeback_info[i].wb_enabled) { 529 if (j < i) 530 /* trim the array */ 531 stream->writeback_info[j] = stream->writeback_info[i]; 532 j++; 533 } 534 } 535 stream->num_wb_info = j; 536 537 if (IS_DIAG_DC(dc->ctx->dce_environment)) { 538 /* recalculate and apply DML parameters */ 539 if (!dc->hwss.update_bandwidth(dc, dc->current_state)) { 540 dm_error("DC: update_bandwidth failed!\n"); 541 return false; 542 } 543 544 /* disable writeback */ 545 if (dc->hwss.disable_writeback) 546 dc->hwss.disable_writeback(dc, dwb_pipe_inst); 547 } 548 return true; 549 } 550 551 bool dc_stream_warmup_writeback(struct dc *dc, 552 int num_dwb, 553 struct dc_writeback_info *wb_info) 554 { 555 if (dc->hwss.mmhubbub_warmup) 556 return dc->hwss.mmhubbub_warmup(dc, num_dwb, wb_info); 557 else 558 return false; 559 } 560 uint32_t dc_stream_get_vblank_counter(const struct dc_stream_state *stream) 561 { 562 uint8_t i; 563 struct dc *dc = stream->ctx->dc; 564 struct resource_context *res_ctx = 565 &dc->current_state->res_ctx; 566 567 for (i = 0; i < MAX_PIPES; i++) { 568 struct timing_generator *tg = res_ctx->pipe_ctx[i].stream_res.tg; 569 570 if (res_ctx->pipe_ctx[i].stream != stream) 571 continue; 572 573 return tg->funcs->get_frame_count(tg); 574 } 575 576 return 0; 577 } 578 579 bool dc_stream_send_dp_sdp(const struct dc_stream_state *stream, 580 const uint8_t *custom_sdp_message, 581 unsigned int sdp_message_size) 582 { 583 int i; 584 struct dc *dc; 585 struct resource_context *res_ctx; 586 587 if (stream == NULL) { 588 dm_error("DC: dc_stream is NULL!\n"); 589 return false; 590 } 591 592 dc = stream->ctx->dc; 593 res_ctx = &dc->current_state->res_ctx; 594 595 for (i = 0; i < MAX_PIPES; i++) { 596 struct pipe_ctx *pipe_ctx = &res_ctx->pipe_ctx[i]; 597 598 if (pipe_ctx->stream != stream) 599 continue; 600 601 if (dc->hwss.send_immediate_sdp_message != NULL) 602 dc->hwss.send_immediate_sdp_message(pipe_ctx, 603 custom_sdp_message, 604 sdp_message_size); 605 else 606 DC_LOG_WARNING("%s:send_immediate_sdp_message not implemented on this ASIC\n", 607 __func__); 608 609 } 610 611 return true; 612 } 613 614 bool dc_stream_get_scanoutpos(const struct dc_stream_state *stream, 615 uint32_t *v_blank_start, 616 uint32_t *v_blank_end, 617 uint32_t *h_position, 618 uint32_t *v_position) 619 { 620 uint8_t i; 621 bool ret = false; 622 struct dc *dc = stream->ctx->dc; 623 struct resource_context *res_ctx = 624 &dc->current_state->res_ctx; 625 626 for (i = 0; i < MAX_PIPES; i++) { 627 struct timing_generator *tg = res_ctx->pipe_ctx[i].stream_res.tg; 628 629 if (res_ctx->pipe_ctx[i].stream != stream) 630 continue; 631 632 tg->funcs->get_scanoutpos(tg, 633 v_blank_start, 634 v_blank_end, 635 h_position, 636 v_position); 637 638 ret = true; 639 break; 640 } 641 642 return ret; 643 } 644 645 bool dc_stream_dmdata_status_done(struct dc *dc, struct dc_stream_state *stream) 646 { 647 struct pipe_ctx *pipe = NULL; 648 int i; 649 650 if (!dc->hwss.dmdata_status_done) 651 return false; 652 653 for (i = 0; i < MAX_PIPES; i++) { 654 pipe = &dc->current_state->res_ctx.pipe_ctx[i]; 655 if (pipe->stream == stream) 656 break; 657 } 658 /* Stream not found, by default we'll assume HUBP fetched dm data */ 659 if (i == MAX_PIPES) 660 return true; 661 662 return dc->hwss.dmdata_status_done(pipe); 663 } 664 665 bool dc_stream_set_dynamic_metadata(struct dc *dc, 666 struct dc_stream_state *stream, 667 struct dc_dmdata_attributes *attr) 668 { 669 struct pipe_ctx *pipe_ctx = NULL; 670 struct hubp *hubp; 671 int i; 672 673 /* Dynamic metadata is only supported on HDMI or DP */ 674 if (!dc_is_hdmi_signal(stream->signal) && !dc_is_dp_signal(stream->signal)) 675 return false; 676 677 /* Check hardware support */ 678 if (!dc->hwss.program_dmdata_engine) 679 return false; 680 681 for (i = 0; i < MAX_PIPES; i++) { 682 pipe_ctx = &dc->current_state->res_ctx.pipe_ctx[i]; 683 if (pipe_ctx->stream == stream) 684 break; 685 } 686 687 if (i == MAX_PIPES) 688 return false; 689 690 hubp = pipe_ctx->plane_res.hubp; 691 if (hubp == NULL) 692 return false; 693 694 pipe_ctx->stream->dmdata_address = attr->address; 695 696 dc->hwss.program_dmdata_engine(pipe_ctx); 697 698 if (hubp->funcs->dmdata_set_attributes != NULL && 699 pipe_ctx->stream->dmdata_address.quad_part != 0) { 700 hubp->funcs->dmdata_set_attributes(hubp, attr); 701 } 702 703 return true; 704 } 705 706 enum dc_status dc_stream_add_dsc_to_resource(struct dc *dc, 707 struct dc_state *state, 708 struct dc_stream_state *stream) 709 { 710 if (dc->res_pool->funcs->add_dsc_to_stream_resource) { 711 return dc->res_pool->funcs->add_dsc_to_stream_resource(dc, state, stream); 712 } else { 713 return DC_NO_DSC_RESOURCE; 714 } 715 } 716 717 struct pipe_ctx *dc_stream_get_pipe_ctx(struct dc_stream_state *stream) 718 { 719 int i = 0; 720 721 for (i = 0; i < MAX_PIPES; i++) { 722 struct pipe_ctx *pipe = &stream->ctx->dc->current_state->res_ctx.pipe_ctx[i]; 723 724 if (pipe->stream == stream) 725 return pipe; 726 } 727 728 return NULL; 729 } 730 731 void dc_stream_log(const struct dc *dc, const struct dc_stream_state *stream) 732 { 733 DC_LOG_DC( 734 "core_stream 0x%p: src: %d, %d, %d, %d; dst: %d, %d, %d, %d, colorSpace:%d\n", 735 stream, 736 stream->src.x, 737 stream->src.y, 738 stream->src.width, 739 stream->src.height, 740 stream->dst.x, 741 stream->dst.y, 742 stream->dst.width, 743 stream->dst.height, 744 stream->output_color_space); 745 DC_LOG_DC( 746 "\tpix_clk_khz: %d, h_total: %d, v_total: %d, pixelencoder:%d, displaycolorDepth:%d\n", 747 stream->timing.pix_clk_100hz / 10, 748 stream->timing.h_total, 749 stream->timing.v_total, 750 stream->timing.pixel_encoding, 751 stream->timing.display_color_depth); 752 DC_LOG_DC( 753 "\tlink: %d\n", 754 stream->link->link_index); 755 756 DC_LOG_DC( 757 "\tdsc: %d, mst_pbn: %d\n", 758 stream->timing.flags.DSC, 759 stream->timing.dsc_cfg.mst_pbn); 760 761 if (stream->sink) { 762 if (stream->sink->sink_signal != SIGNAL_TYPE_VIRTUAL && 763 stream->sink->sink_signal != SIGNAL_TYPE_NONE) { 764 765 DC_LOG_DC( 766 "\tdispname: %s signal: %x\n", 767 stream->sink->edid_caps.display_name, 768 stream->signal); 769 } 770 } 771 } 772 773