1 /* 2 * Copyright 2012-15 Advanced Micro Devices, Inc. 3 * 4 * Permission is hereby granted, free of charge, to any person obtaining a 5 * copy of this software and associated documentation files (the "Software"), 6 * to deal in the Software without restriction, including without limitation 7 * the rights to use, copy, modify, merge, publish, distribute, sublicense, 8 * and/or sell copies of the Software, and to permit persons to whom the 9 * Software is furnished to do so, subject to the following conditions: 10 * 11 * The above copyright notice and this permission notice shall be included in 12 * all copies or substantial portions of the Software. 13 * 14 * THE SOFTWARE IS PROVIDED "AS IS", WITHOUT WARRANTY OF ANY KIND, EXPRESS OR 15 * IMPLIED, INCLUDING BUT NOT LIMITED TO THE WARRANTIES OF MERCHANTABILITY, 16 * FITNESS FOR A PARTICULAR PURPOSE AND NONINFRINGEMENT. IN NO EVENT SHALL 17 * THE COPYRIGHT HOLDER(S) OR AUTHOR(S) BE LIABLE FOR ANY CLAIM, DAMAGES OR 18 * OTHER LIABILITY, WHETHER IN AN ACTION OF CONTRACT, TORT OR OTHERWISE, 19 * ARISING FROM, OUT OF OR IN CONNECTION WITH THE SOFTWARE OR THE USE OR 20 * OTHER DEALINGS IN THE SOFTWARE. 21 * 22 * Authors: AMD 23 * 24 */ 25 26 #include <linux/delay.h> 27 #include <linux/slab.h> 28 29 #include "dm_services.h" 30 #include "basics/dc_common.h" 31 #include "dc.h" 32 #include "core_types.h" 33 #include "resource.h" 34 #include "ipp.h" 35 #include "timing_generator.h" 36 37 #define DC_LOGGER dc->ctx->logger 38 39 /******************************************************************************* 40 * Private functions 41 ******************************************************************************/ 42 void update_stream_signal(struct dc_stream_state *stream, struct dc_sink *sink) 43 { 44 if (sink->sink_signal == SIGNAL_TYPE_NONE) 45 stream->signal = stream->link->connector_signal; 46 else 47 stream->signal = sink->sink_signal; 48 49 if (dc_is_dvi_signal(stream->signal)) { 50 if (stream->ctx->dc->caps.dual_link_dvi && 51 (stream->timing.pix_clk_100hz / 10) > TMDS_MAX_PIXEL_CLOCK && 52 sink->sink_signal != SIGNAL_TYPE_DVI_SINGLE_LINK) 53 stream->signal = SIGNAL_TYPE_DVI_DUAL_LINK; 54 else 55 stream->signal = SIGNAL_TYPE_DVI_SINGLE_LINK; 56 } 57 } 58 59 static bool dc_stream_construct(struct dc_stream_state *stream, 60 struct dc_sink *dc_sink_data) 61 { 62 uint32_t i = 0; 63 64 stream->sink = dc_sink_data; 65 dc_sink_retain(dc_sink_data); 66 67 stream->ctx = dc_sink_data->ctx; 68 stream->link = dc_sink_data->link; 69 stream->sink_patches = dc_sink_data->edid_caps.panel_patch; 70 stream->converter_disable_audio = dc_sink_data->converter_disable_audio; 71 stream->qs_bit = dc_sink_data->edid_caps.qs_bit; 72 stream->qy_bit = dc_sink_data->edid_caps.qy_bit; 73 74 /* Copy audio modes */ 75 /* TODO - Remove this translation */ 76 for (i = 0; i < (dc_sink_data->edid_caps.audio_mode_count); i++) 77 { 78 stream->audio_info.modes[i].channel_count = dc_sink_data->edid_caps.audio_modes[i].channel_count; 79 stream->audio_info.modes[i].format_code = dc_sink_data->edid_caps.audio_modes[i].format_code; 80 stream->audio_info.modes[i].sample_rates.all = dc_sink_data->edid_caps.audio_modes[i].sample_rate; 81 stream->audio_info.modes[i].sample_size = dc_sink_data->edid_caps.audio_modes[i].sample_size; 82 } 83 stream->audio_info.mode_count = dc_sink_data->edid_caps.audio_mode_count; 84 stream->audio_info.audio_latency = dc_sink_data->edid_caps.audio_latency; 85 stream->audio_info.video_latency = dc_sink_data->edid_caps.video_latency; 86 memmove( 87 stream->audio_info.display_name, 88 dc_sink_data->edid_caps.display_name, 89 AUDIO_INFO_DISPLAY_NAME_SIZE_IN_CHARS); 90 stream->audio_info.manufacture_id = dc_sink_data->edid_caps.manufacturer_id; 91 stream->audio_info.product_id = dc_sink_data->edid_caps.product_id; 92 stream->audio_info.flags.all = dc_sink_data->edid_caps.speaker_flags; 93 94 if (dc_sink_data->dc_container_id != NULL) { 95 struct dc_container_id *dc_container_id = dc_sink_data->dc_container_id; 96 97 stream->audio_info.port_id[0] = dc_container_id->portId[0]; 98 stream->audio_info.port_id[1] = dc_container_id->portId[1]; 99 } else { 100 /* TODO - WindowDM has implemented, 101 other DMs need Unhardcode port_id */ 102 stream->audio_info.port_id[0] = 0x5558859e; 103 stream->audio_info.port_id[1] = 0xd989449; 104 } 105 106 /* EDID CAP translation for HDMI 2.0 */ 107 stream->timing.flags.LTE_340MCSC_SCRAMBLE = dc_sink_data->edid_caps.lte_340mcsc_scramble; 108 109 memset(&stream->timing.dsc_cfg, 0, sizeof(stream->timing.dsc_cfg)); 110 stream->timing.dsc_cfg.num_slices_h = 0; 111 stream->timing.dsc_cfg.num_slices_v = 0; 112 stream->timing.dsc_cfg.bits_per_pixel = 128; 113 stream->timing.dsc_cfg.block_pred_enable = 1; 114 stream->timing.dsc_cfg.linebuf_depth = 9; 115 stream->timing.dsc_cfg.version_minor = 2; 116 stream->timing.dsc_cfg.ycbcr422_simple = 0; 117 118 update_stream_signal(stream, dc_sink_data); 119 120 stream->out_transfer_func = dc_create_transfer_func(); 121 if (stream->out_transfer_func == NULL) { 122 dc_sink_release(dc_sink_data); 123 return false; 124 } 125 stream->out_transfer_func->type = TF_TYPE_BYPASS; 126 stream->out_transfer_func->ctx = stream->ctx; 127 128 stream->stream_id = stream->ctx->dc_stream_id_count; 129 stream->ctx->dc_stream_id_count++; 130 131 return true; 132 } 133 134 static void dc_stream_destruct(struct dc_stream_state *stream) 135 { 136 dc_sink_release(stream->sink); 137 if (stream->out_transfer_func != NULL) { 138 dc_transfer_func_release(stream->out_transfer_func); 139 stream->out_transfer_func = NULL; 140 } 141 } 142 143 void dc_stream_retain(struct dc_stream_state *stream) 144 { 145 kref_get(&stream->refcount); 146 } 147 148 static void dc_stream_free(struct kref *kref) 149 { 150 struct dc_stream_state *stream = container_of(kref, struct dc_stream_state, refcount); 151 152 dc_stream_destruct(stream); 153 kfree(stream); 154 } 155 156 void dc_stream_release(struct dc_stream_state *stream) 157 { 158 if (stream != NULL) { 159 kref_put(&stream->refcount, dc_stream_free); 160 } 161 } 162 163 struct dc_stream_state *dc_create_stream_for_sink( 164 struct dc_sink *sink) 165 { 166 struct dc_stream_state *stream; 167 168 if (sink == NULL) 169 return NULL; 170 171 stream = kzalloc(sizeof(struct dc_stream_state), GFP_KERNEL); 172 if (stream == NULL) 173 goto alloc_fail; 174 175 if (dc_stream_construct(stream, sink) == false) 176 goto construct_fail; 177 178 kref_init(&stream->refcount); 179 180 return stream; 181 182 construct_fail: 183 kfree(stream); 184 185 alloc_fail: 186 return NULL; 187 } 188 189 struct dc_stream_state *dc_copy_stream(const struct dc_stream_state *stream) 190 { 191 struct dc_stream_state *new_stream; 192 193 new_stream = kmemdup(stream, sizeof(struct dc_stream_state), GFP_KERNEL); 194 if (!new_stream) 195 return NULL; 196 197 if (new_stream->sink) 198 dc_sink_retain(new_stream->sink); 199 200 if (new_stream->out_transfer_func) 201 dc_transfer_func_retain(new_stream->out_transfer_func); 202 203 new_stream->stream_id = new_stream->ctx->dc_stream_id_count; 204 new_stream->ctx->dc_stream_id_count++; 205 206 kref_init(&new_stream->refcount); 207 208 return new_stream; 209 } 210 211 /** 212 * dc_stream_get_status_from_state - Get stream status from given dc state 213 * @state: DC state to find the stream status in 214 * @stream: The stream to get the stream status for 215 * 216 * The given stream is expected to exist in the given dc state. Otherwise, NULL 217 * will be returned. 218 */ 219 struct dc_stream_status *dc_stream_get_status_from_state( 220 struct dc_state *state, 221 struct dc_stream_state *stream) 222 { 223 uint8_t i; 224 225 for (i = 0; i < state->stream_count; i++) { 226 if (stream == state->streams[i]) 227 return &state->stream_status[i]; 228 } 229 230 return NULL; 231 } 232 233 /** 234 * dc_stream_get_status() - Get current stream status of the given stream state 235 * @stream: The stream to get the stream status for. 236 * 237 * The given stream is expected to exist in dc->current_state. Otherwise, NULL 238 * will be returned. 239 */ 240 struct dc_stream_status *dc_stream_get_status( 241 struct dc_stream_state *stream) 242 { 243 struct dc *dc = stream->ctx->dc; 244 return dc_stream_get_status_from_state(dc->current_state, stream); 245 } 246 247 #ifndef TRIM_FSFT 248 /** 249 * dc_optimize_timing_for_fsft() - dc to optimize timing 250 */ 251 bool dc_optimize_timing_for_fsft( 252 struct dc_stream_state *pStream, 253 unsigned int max_input_rate_in_khz) 254 { 255 struct dc *dc; 256 257 dc = pStream->ctx->dc; 258 259 return (dc->hwss.optimize_timing_for_fsft && 260 dc->hwss.optimize_timing_for_fsft(dc, &pStream->timing, max_input_rate_in_khz)); 261 } 262 #endif 263 264 265 /** 266 * dc_stream_set_cursor_attributes() - Update cursor attributes and set cursor surface address 267 */ 268 bool dc_stream_set_cursor_attributes( 269 struct dc_stream_state *stream, 270 const struct dc_cursor_attributes *attributes) 271 { 272 int i; 273 struct dc *dc; 274 struct resource_context *res_ctx; 275 struct pipe_ctx *pipe_to_program = NULL; 276 #if defined(CONFIG_DRM_AMD_DC_DCN3_0) 277 bool reset_idle_optimizations = false; 278 #endif 279 280 if (NULL == stream) { 281 dm_error("DC: dc_stream is NULL!\n"); 282 return false; 283 } 284 if (NULL == attributes) { 285 dm_error("DC: attributes is NULL!\n"); 286 return false; 287 } 288 289 if (attributes->address.quad_part == 0) { 290 dm_output_to_console("DC: Cursor address is 0!\n"); 291 return false; 292 } 293 294 dc = stream->ctx->dc; 295 res_ctx = &dc->current_state->res_ctx; 296 stream->cursor_attributes = *attributes; 297 298 #if defined(CONFIG_DRM_AMD_DC_DCN3_0) 299 /* disable idle optimizations while updating cursor */ 300 if (dc->idle_optimizations_allowed) { 301 dc->hwss.apply_idle_power_optimizations(dc, false); 302 reset_idle_optimizations = true; 303 } 304 305 #endif 306 307 for (i = 0; i < MAX_PIPES; i++) { 308 struct pipe_ctx *pipe_ctx = &res_ctx->pipe_ctx[i]; 309 310 if (pipe_ctx->stream != stream) 311 continue; 312 313 if (!pipe_to_program) { 314 pipe_to_program = pipe_ctx; 315 dc->hwss.cursor_lock(dc, pipe_to_program, true); 316 } 317 318 dc->hwss.set_cursor_attribute(pipe_ctx); 319 if (dc->hwss.set_cursor_sdr_white_level) 320 dc->hwss.set_cursor_sdr_white_level(pipe_ctx); 321 } 322 323 if (pipe_to_program) 324 dc->hwss.cursor_lock(dc, pipe_to_program, false); 325 326 #if defined(CONFIG_DRM_AMD_DC_DCN3_0) 327 /* re-enable idle optimizations if necessary */ 328 if (reset_idle_optimizations) 329 dc->hwss.apply_idle_power_optimizations(dc, true); 330 331 #endif 332 return true; 333 } 334 335 bool dc_stream_set_cursor_position( 336 struct dc_stream_state *stream, 337 const struct dc_cursor_position *position) 338 { 339 int i; 340 struct dc *dc; 341 struct resource_context *res_ctx; 342 struct pipe_ctx *pipe_to_program = NULL; 343 #if defined(CONFIG_DRM_AMD_DC_DCN3_0) 344 bool reset_idle_optimizations = false; 345 #endif 346 347 if (NULL == stream) { 348 dm_error("DC: dc_stream is NULL!\n"); 349 return false; 350 } 351 352 if (NULL == position) { 353 dm_error("DC: cursor position is NULL!\n"); 354 return false; 355 } 356 357 dc = stream->ctx->dc; 358 res_ctx = &dc->current_state->res_ctx; 359 #if defined(CONFIG_DRM_AMD_DC_DCN3_0) 360 361 /* disable idle optimizations if enabling cursor */ 362 if (dc->idle_optimizations_allowed && 363 !stream->cursor_position.enable && position->enable) { 364 dc->hwss.apply_idle_power_optimizations(dc, false); 365 reset_idle_optimizations = true; 366 } 367 368 #endif 369 stream->cursor_position = *position; 370 371 for (i = 0; i < MAX_PIPES; i++) { 372 struct pipe_ctx *pipe_ctx = &res_ctx->pipe_ctx[i]; 373 374 if (pipe_ctx->stream != stream || 375 (!pipe_ctx->plane_res.mi && !pipe_ctx->plane_res.hubp) || 376 !pipe_ctx->plane_state || 377 (!pipe_ctx->plane_res.xfm && !pipe_ctx->plane_res.dpp) || 378 (!pipe_ctx->plane_res.ipp && !pipe_ctx->plane_res.dpp)) 379 continue; 380 381 if (!pipe_to_program) { 382 pipe_to_program = pipe_ctx; 383 dc->hwss.cursor_lock(dc, pipe_to_program, true); 384 } 385 386 dc->hwss.set_cursor_position(pipe_ctx); 387 } 388 389 if (pipe_to_program) 390 dc->hwss.cursor_lock(dc, pipe_to_program, false); 391 392 #if defined(CONFIG_DRM_AMD_DC_DCN3_0) 393 /* re-enable idle optimizations if necessary */ 394 if (reset_idle_optimizations) 395 dc->hwss.apply_idle_power_optimizations(dc, true); 396 397 #endif 398 return true; 399 } 400 401 bool dc_stream_add_writeback(struct dc *dc, 402 struct dc_stream_state *stream, 403 struct dc_writeback_info *wb_info) 404 { 405 bool isDrc = false; 406 int i = 0; 407 struct dwbc *dwb; 408 409 if (stream == NULL) { 410 dm_error("DC: dc_stream is NULL!\n"); 411 return false; 412 } 413 414 if (wb_info == NULL) { 415 dm_error("DC: dc_writeback_info is NULL!\n"); 416 return false; 417 } 418 419 if (wb_info->dwb_pipe_inst >= MAX_DWB_PIPES) { 420 dm_error("DC: writeback pipe is invalid!\n"); 421 return false; 422 } 423 424 wb_info->dwb_params.out_transfer_func = stream->out_transfer_func; 425 426 dwb = dc->res_pool->dwbc[wb_info->dwb_pipe_inst]; 427 dwb->dwb_is_drc = false; 428 429 /* recalculate and apply DML parameters */ 430 431 for (i = 0; i < stream->num_wb_info; i++) { 432 /*dynamic update*/ 433 if (stream->writeback_info[i].wb_enabled && 434 stream->writeback_info[i].dwb_pipe_inst == wb_info->dwb_pipe_inst) { 435 stream->writeback_info[i] = *wb_info; 436 isDrc = true; 437 } 438 } 439 440 if (!isDrc) { 441 stream->writeback_info[stream->num_wb_info++] = *wb_info; 442 } 443 444 if (dc->hwss.enable_writeback) { 445 struct dc_stream_status *stream_status = dc_stream_get_status(stream); 446 struct dwbc *dwb = dc->res_pool->dwbc[wb_info->dwb_pipe_inst]; 447 dwb->otg_inst = stream_status->primary_otg_inst; 448 } 449 if (IS_DIAG_DC(dc->ctx->dce_environment)) { 450 if (!dc->hwss.update_bandwidth(dc, dc->current_state)) { 451 dm_error("DC: update_bandwidth failed!\n"); 452 return false; 453 } 454 455 /* enable writeback */ 456 if (dc->hwss.enable_writeback) { 457 struct dwbc *dwb = dc->res_pool->dwbc[wb_info->dwb_pipe_inst]; 458 459 if (dwb->funcs->is_enabled(dwb)) { 460 /* writeback pipe already enabled, only need to update */ 461 dc->hwss.update_writeback(dc, wb_info, dc->current_state); 462 } else { 463 /* Enable writeback pipe from scratch*/ 464 dc->hwss.enable_writeback(dc, wb_info, dc->current_state); 465 } 466 } 467 } 468 return true; 469 } 470 471 bool dc_stream_remove_writeback(struct dc *dc, 472 struct dc_stream_state *stream, 473 uint32_t dwb_pipe_inst) 474 { 475 int i = 0, j = 0; 476 if (stream == NULL) { 477 dm_error("DC: dc_stream is NULL!\n"); 478 return false; 479 } 480 481 if (dwb_pipe_inst >= MAX_DWB_PIPES) { 482 dm_error("DC: writeback pipe is invalid!\n"); 483 return false; 484 } 485 486 // stream->writeback_info[dwb_pipe_inst].wb_enabled = false; 487 for (i = 0; i < stream->num_wb_info; i++) { 488 /*dynamic update*/ 489 if (stream->writeback_info[i].wb_enabled && 490 stream->writeback_info[i].dwb_pipe_inst == dwb_pipe_inst) { 491 stream->writeback_info[i].wb_enabled = false; 492 } 493 } 494 495 /* remove writeback info for disabled writeback pipes from stream */ 496 for (i = 0, j = 0; i < stream->num_wb_info; i++) { 497 if (stream->writeback_info[i].wb_enabled) { 498 if (i != j) 499 /* trim the array */ 500 stream->writeback_info[j] = stream->writeback_info[i]; 501 j++; 502 } 503 } 504 stream->num_wb_info = j; 505 506 if (IS_DIAG_DC(dc->ctx->dce_environment)) { 507 /* recalculate and apply DML parameters */ 508 if (!dc->hwss.update_bandwidth(dc, dc->current_state)) { 509 dm_error("DC: update_bandwidth failed!\n"); 510 return false; 511 } 512 513 /* disable writeback */ 514 if (dc->hwss.disable_writeback) 515 dc->hwss.disable_writeback(dc, dwb_pipe_inst); 516 } 517 return true; 518 } 519 520 bool dc_stream_warmup_writeback(struct dc *dc, 521 int num_dwb, 522 struct dc_writeback_info *wb_info) 523 { 524 if (dc->hwss.mmhubbub_warmup) 525 return dc->hwss.mmhubbub_warmup(dc, num_dwb, wb_info); 526 else 527 return false; 528 } 529 uint32_t dc_stream_get_vblank_counter(const struct dc_stream_state *stream) 530 { 531 uint8_t i; 532 struct dc *dc = stream->ctx->dc; 533 struct resource_context *res_ctx = 534 &dc->current_state->res_ctx; 535 536 for (i = 0; i < MAX_PIPES; i++) { 537 struct timing_generator *tg = res_ctx->pipe_ctx[i].stream_res.tg; 538 539 if (res_ctx->pipe_ctx[i].stream != stream) 540 continue; 541 542 return tg->funcs->get_frame_count(tg); 543 } 544 545 return 0; 546 } 547 548 bool dc_stream_send_dp_sdp(const struct dc_stream_state *stream, 549 const uint8_t *custom_sdp_message, 550 unsigned int sdp_message_size) 551 { 552 int i; 553 struct dc *dc; 554 struct resource_context *res_ctx; 555 556 if (stream == NULL) { 557 dm_error("DC: dc_stream is NULL!\n"); 558 return false; 559 } 560 561 dc = stream->ctx->dc; 562 res_ctx = &dc->current_state->res_ctx; 563 564 for (i = 0; i < MAX_PIPES; i++) { 565 struct pipe_ctx *pipe_ctx = &res_ctx->pipe_ctx[i]; 566 567 if (pipe_ctx->stream != stream) 568 continue; 569 570 if (dc->hwss.send_immediate_sdp_message != NULL) 571 dc->hwss.send_immediate_sdp_message(pipe_ctx, 572 custom_sdp_message, 573 sdp_message_size); 574 else 575 DC_LOG_WARNING("%s:send_immediate_sdp_message not implemented on this ASIC\n", 576 __func__); 577 578 } 579 580 return true; 581 } 582 583 bool dc_stream_get_scanoutpos(const struct dc_stream_state *stream, 584 uint32_t *v_blank_start, 585 uint32_t *v_blank_end, 586 uint32_t *h_position, 587 uint32_t *v_position) 588 { 589 uint8_t i; 590 bool ret = false; 591 struct dc *dc = stream->ctx->dc; 592 struct resource_context *res_ctx = 593 &dc->current_state->res_ctx; 594 595 for (i = 0; i < MAX_PIPES; i++) { 596 struct timing_generator *tg = res_ctx->pipe_ctx[i].stream_res.tg; 597 598 if (res_ctx->pipe_ctx[i].stream != stream) 599 continue; 600 601 tg->funcs->get_scanoutpos(tg, 602 v_blank_start, 603 v_blank_end, 604 h_position, 605 v_position); 606 607 ret = true; 608 break; 609 } 610 611 return ret; 612 } 613 614 bool dc_stream_dmdata_status_done(struct dc *dc, struct dc_stream_state *stream) 615 { 616 struct pipe_ctx *pipe = NULL; 617 int i; 618 619 if (!dc->hwss.dmdata_status_done) 620 return false; 621 622 for (i = 0; i < MAX_PIPES; i++) { 623 pipe = &dc->current_state->res_ctx.pipe_ctx[i]; 624 if (pipe->stream == stream) 625 break; 626 } 627 /* Stream not found, by default we'll assume HUBP fetched dm data */ 628 if (i == MAX_PIPES) 629 return true; 630 631 return dc->hwss.dmdata_status_done(pipe); 632 } 633 634 bool dc_stream_set_dynamic_metadata(struct dc *dc, 635 struct dc_stream_state *stream, 636 struct dc_dmdata_attributes *attr) 637 { 638 struct pipe_ctx *pipe_ctx = NULL; 639 struct hubp *hubp; 640 int i; 641 642 /* Dynamic metadata is only supported on HDMI or DP */ 643 if (!dc_is_hdmi_signal(stream->signal) && !dc_is_dp_signal(stream->signal)) 644 return false; 645 646 /* Check hardware support */ 647 if (!dc->hwss.program_dmdata_engine) 648 return false; 649 650 for (i = 0; i < MAX_PIPES; i++) { 651 pipe_ctx = &dc->current_state->res_ctx.pipe_ctx[i]; 652 if (pipe_ctx->stream == stream) 653 break; 654 } 655 656 if (i == MAX_PIPES) 657 return false; 658 659 hubp = pipe_ctx->plane_res.hubp; 660 if (hubp == NULL) 661 return false; 662 663 pipe_ctx->stream->dmdata_address = attr->address; 664 665 dc->hwss.program_dmdata_engine(pipe_ctx); 666 667 if (hubp->funcs->dmdata_set_attributes != NULL && 668 pipe_ctx->stream->dmdata_address.quad_part != 0) { 669 hubp->funcs->dmdata_set_attributes(hubp, attr); 670 } 671 672 return true; 673 } 674 675 enum dc_status dc_stream_add_dsc_to_resource(struct dc *dc, 676 struct dc_state *state, 677 struct dc_stream_state *stream) 678 { 679 if (dc->res_pool->funcs->add_dsc_to_stream_resource) { 680 return dc->res_pool->funcs->add_dsc_to_stream_resource(dc, state, stream); 681 } else { 682 return DC_NO_DSC_RESOURCE; 683 } 684 } 685 686 void dc_stream_log(const struct dc *dc, const struct dc_stream_state *stream) 687 { 688 DC_LOG_DC( 689 "core_stream 0x%p: src: %d, %d, %d, %d; dst: %d, %d, %d, %d, colorSpace:%d\n", 690 stream, 691 stream->src.x, 692 stream->src.y, 693 stream->src.width, 694 stream->src.height, 695 stream->dst.x, 696 stream->dst.y, 697 stream->dst.width, 698 stream->dst.height, 699 stream->output_color_space); 700 DC_LOG_DC( 701 "\tpix_clk_khz: %d, h_total: %d, v_total: %d, pixelencoder:%d, displaycolorDepth:%d\n", 702 stream->timing.pix_clk_100hz / 10, 703 stream->timing.h_total, 704 stream->timing.v_total, 705 stream->timing.pixel_encoding, 706 stream->timing.display_color_depth); 707 DC_LOG_DC( 708 "\tlink: %d\n", 709 stream->link->link_index); 710 } 711