1 /* 2 * Copyright 2012-15 Advanced Micro Devices, Inc. 3 * 4 * Permission is hereby granted, free of charge, to any person obtaining a 5 * copy of this software and associated documentation files (the "Software"), 6 * to deal in the Software without restriction, including without limitation 7 * the rights to use, copy, modify, merge, publish, distribute, sublicense, 8 * and/or sell copies of the Software, and to permit persons to whom the 9 * Software is furnished to do so, subject to the following conditions: 10 * 11 * The above copyright notice and this permission notice shall be included in 12 * all copies or substantial portions of the Software. 13 * 14 * THE SOFTWARE IS PROVIDED "AS IS", WITHOUT WARRANTY OF ANY KIND, EXPRESS OR 15 * IMPLIED, INCLUDING BUT NOT LIMITED TO THE WARRANTIES OF MERCHANTABILITY, 16 * FITNESS FOR A PARTICULAR PURPOSE AND NONINFRINGEMENT. IN NO EVENT SHALL 17 * THE COPYRIGHT HOLDER(S) OR AUTHOR(S) BE LIABLE FOR ANY CLAIM, DAMAGES OR 18 * OTHER LIABILITY, WHETHER IN AN ACTION OF CONTRACT, TORT OR OTHERWISE, 19 * ARISING FROM, OUT OF OR IN CONNECTION WITH THE SOFTWARE OR THE USE OR 20 * OTHER DEALINGS IN THE SOFTWARE. 21 * 22 * Authors: AMD 23 * 24 */ 25 26 #include <linux/delay.h> 27 #include <linux/slab.h> 28 29 #include "dm_services.h" 30 #include "basics/dc_common.h" 31 #include "dc.h" 32 #include "core_types.h" 33 #include "resource.h" 34 #include "ipp.h" 35 #include "timing_generator.h" 36 37 #define DC_LOGGER dc->ctx->logger 38 39 /******************************************************************************* 40 * Private functions 41 ******************************************************************************/ 42 void update_stream_signal(struct dc_stream_state *stream, struct dc_sink *sink) 43 { 44 if (sink->sink_signal == SIGNAL_TYPE_NONE) 45 stream->signal = stream->link->connector_signal; 46 else 47 stream->signal = sink->sink_signal; 48 49 if (dc_is_dvi_signal(stream->signal)) { 50 if (stream->ctx->dc->caps.dual_link_dvi && 51 (stream->timing.pix_clk_100hz / 10) > TMDS_MAX_PIXEL_CLOCK && 52 sink->sink_signal != SIGNAL_TYPE_DVI_SINGLE_LINK) 53 stream->signal = SIGNAL_TYPE_DVI_DUAL_LINK; 54 else 55 stream->signal = SIGNAL_TYPE_DVI_SINGLE_LINK; 56 } 57 } 58 59 static bool dc_stream_construct(struct dc_stream_state *stream, 60 struct dc_sink *dc_sink_data) 61 { 62 uint32_t i = 0; 63 64 stream->sink = dc_sink_data; 65 dc_sink_retain(dc_sink_data); 66 67 stream->ctx = dc_sink_data->ctx; 68 stream->link = dc_sink_data->link; 69 stream->sink_patches = dc_sink_data->edid_caps.panel_patch; 70 stream->converter_disable_audio = dc_sink_data->converter_disable_audio; 71 stream->qs_bit = dc_sink_data->edid_caps.qs_bit; 72 stream->qy_bit = dc_sink_data->edid_caps.qy_bit; 73 74 /* Copy audio modes */ 75 /* TODO - Remove this translation */ 76 for (i = 0; i < (dc_sink_data->edid_caps.audio_mode_count); i++) 77 { 78 stream->audio_info.modes[i].channel_count = dc_sink_data->edid_caps.audio_modes[i].channel_count; 79 stream->audio_info.modes[i].format_code = dc_sink_data->edid_caps.audio_modes[i].format_code; 80 stream->audio_info.modes[i].sample_rates.all = dc_sink_data->edid_caps.audio_modes[i].sample_rate; 81 stream->audio_info.modes[i].sample_size = dc_sink_data->edid_caps.audio_modes[i].sample_size; 82 } 83 stream->audio_info.mode_count = dc_sink_data->edid_caps.audio_mode_count; 84 stream->audio_info.audio_latency = dc_sink_data->edid_caps.audio_latency; 85 stream->audio_info.video_latency = dc_sink_data->edid_caps.video_latency; 86 memmove( 87 stream->audio_info.display_name, 88 dc_sink_data->edid_caps.display_name, 89 AUDIO_INFO_DISPLAY_NAME_SIZE_IN_CHARS); 90 stream->audio_info.manufacture_id = dc_sink_data->edid_caps.manufacturer_id; 91 stream->audio_info.product_id = dc_sink_data->edid_caps.product_id; 92 stream->audio_info.flags.all = dc_sink_data->edid_caps.speaker_flags; 93 94 if (dc_sink_data->dc_container_id != NULL) { 95 struct dc_container_id *dc_container_id = dc_sink_data->dc_container_id; 96 97 stream->audio_info.port_id[0] = dc_container_id->portId[0]; 98 stream->audio_info.port_id[1] = dc_container_id->portId[1]; 99 } else { 100 /* TODO - WindowDM has implemented, 101 other DMs need Unhardcode port_id */ 102 stream->audio_info.port_id[0] = 0x5558859e; 103 stream->audio_info.port_id[1] = 0xd989449; 104 } 105 106 /* EDID CAP translation for HDMI 2.0 */ 107 stream->timing.flags.LTE_340MCSC_SCRAMBLE = dc_sink_data->edid_caps.lte_340mcsc_scramble; 108 109 memset(&stream->timing.dsc_cfg, 0, sizeof(stream->timing.dsc_cfg)); 110 stream->timing.dsc_cfg.num_slices_h = 0; 111 stream->timing.dsc_cfg.num_slices_v = 0; 112 stream->timing.dsc_cfg.bits_per_pixel = 128; 113 stream->timing.dsc_cfg.block_pred_enable = 1; 114 stream->timing.dsc_cfg.linebuf_depth = 9; 115 stream->timing.dsc_cfg.version_minor = 2; 116 stream->timing.dsc_cfg.ycbcr422_simple = 0; 117 118 update_stream_signal(stream, dc_sink_data); 119 120 stream->out_transfer_func = dc_create_transfer_func(); 121 if (stream->out_transfer_func == NULL) { 122 dc_sink_release(dc_sink_data); 123 return false; 124 } 125 stream->out_transfer_func->type = TF_TYPE_BYPASS; 126 127 stream->stream_id = stream->ctx->dc_stream_id_count; 128 stream->ctx->dc_stream_id_count++; 129 130 return true; 131 } 132 133 static void dc_stream_destruct(struct dc_stream_state *stream) 134 { 135 dc_sink_release(stream->sink); 136 if (stream->out_transfer_func != NULL) { 137 dc_transfer_func_release(stream->out_transfer_func); 138 stream->out_transfer_func = NULL; 139 } 140 } 141 142 void dc_stream_retain(struct dc_stream_state *stream) 143 { 144 kref_get(&stream->refcount); 145 } 146 147 static void dc_stream_free(struct kref *kref) 148 { 149 struct dc_stream_state *stream = container_of(kref, struct dc_stream_state, refcount); 150 151 dc_stream_destruct(stream); 152 kfree(stream); 153 } 154 155 void dc_stream_release(struct dc_stream_state *stream) 156 { 157 if (stream != NULL) { 158 kref_put(&stream->refcount, dc_stream_free); 159 } 160 } 161 162 struct dc_stream_state *dc_create_stream_for_sink( 163 struct dc_sink *sink) 164 { 165 struct dc_stream_state *stream; 166 167 if (sink == NULL) 168 return NULL; 169 170 stream = kzalloc(sizeof(struct dc_stream_state), GFP_KERNEL); 171 if (stream == NULL) 172 goto alloc_fail; 173 174 if (dc_stream_construct(stream, sink) == false) 175 goto construct_fail; 176 177 kref_init(&stream->refcount); 178 179 return stream; 180 181 construct_fail: 182 kfree(stream); 183 184 alloc_fail: 185 return NULL; 186 } 187 188 struct dc_stream_state *dc_copy_stream(const struct dc_stream_state *stream) 189 { 190 struct dc_stream_state *new_stream; 191 192 new_stream = kmemdup(stream, sizeof(struct dc_stream_state), GFP_KERNEL); 193 if (!new_stream) 194 return NULL; 195 196 if (new_stream->sink) 197 dc_sink_retain(new_stream->sink); 198 199 if (new_stream->out_transfer_func) 200 dc_transfer_func_retain(new_stream->out_transfer_func); 201 202 new_stream->stream_id = new_stream->ctx->dc_stream_id_count; 203 new_stream->ctx->dc_stream_id_count++; 204 205 /* If using dynamic encoder assignment, wait till stream committed to assign encoder. */ 206 if (new_stream->ctx->dc->res_pool->funcs->link_encs_assign) 207 new_stream->link_enc = NULL; 208 209 kref_init(&new_stream->refcount); 210 211 return new_stream; 212 } 213 214 /** 215 * dc_stream_get_status_from_state - Get stream status from given dc state 216 * @state: DC state to find the stream status in 217 * @stream: The stream to get the stream status for 218 * 219 * The given stream is expected to exist in the given dc state. Otherwise, NULL 220 * will be returned. 221 */ 222 struct dc_stream_status *dc_stream_get_status_from_state( 223 struct dc_state *state, 224 struct dc_stream_state *stream) 225 { 226 uint8_t i; 227 228 if (state == NULL) 229 return NULL; 230 231 for (i = 0; i < state->stream_count; i++) { 232 if (stream == state->streams[i]) 233 return &state->stream_status[i]; 234 } 235 236 return NULL; 237 } 238 239 /** 240 * dc_stream_get_status() - Get current stream status of the given stream state 241 * @stream: The stream to get the stream status for. 242 * 243 * The given stream is expected to exist in dc->current_state. Otherwise, NULL 244 * will be returned. 245 */ 246 struct dc_stream_status *dc_stream_get_status( 247 struct dc_stream_state *stream) 248 { 249 struct dc *dc = stream->ctx->dc; 250 return dc_stream_get_status_from_state(dc->current_state, stream); 251 } 252 253 static void program_cursor_attributes( 254 struct dc *dc, 255 struct dc_stream_state *stream, 256 const struct dc_cursor_attributes *attributes) 257 { 258 int i; 259 struct resource_context *res_ctx; 260 struct pipe_ctx *pipe_to_program = NULL; 261 262 if (!stream) 263 return; 264 265 res_ctx = &dc->current_state->res_ctx; 266 267 for (i = 0; i < MAX_PIPES; i++) { 268 struct pipe_ctx *pipe_ctx = &res_ctx->pipe_ctx[i]; 269 270 if (pipe_ctx->stream != stream) 271 continue; 272 273 if (!pipe_to_program) { 274 pipe_to_program = pipe_ctx; 275 dc->hwss.cursor_lock(dc, pipe_to_program, true); 276 if (pipe_to_program->next_odm_pipe) 277 dc->hwss.cursor_lock(dc, pipe_to_program->next_odm_pipe, true); 278 } 279 280 dc->hwss.set_cursor_attribute(pipe_ctx); 281 if (dc->hwss.set_cursor_sdr_white_level) 282 dc->hwss.set_cursor_sdr_white_level(pipe_ctx); 283 } 284 285 if (pipe_to_program) { 286 dc->hwss.cursor_lock(dc, pipe_to_program, false); 287 if (pipe_to_program->next_odm_pipe) 288 dc->hwss.cursor_lock(dc, pipe_to_program->next_odm_pipe, false); 289 } 290 } 291 292 #ifndef TRIM_FSFT 293 /* 294 * dc_optimize_timing_for_fsft() - dc to optimize timing 295 */ 296 bool dc_optimize_timing_for_fsft( 297 struct dc_stream_state *pStream, 298 unsigned int max_input_rate_in_khz) 299 { 300 struct dc *dc; 301 302 dc = pStream->ctx->dc; 303 304 return (dc->hwss.optimize_timing_for_fsft && 305 dc->hwss.optimize_timing_for_fsft(dc, &pStream->timing, max_input_rate_in_khz)); 306 } 307 #endif 308 309 /* 310 * dc_stream_set_cursor_attributes() - Update cursor attributes and set cursor surface address 311 */ 312 bool dc_stream_set_cursor_attributes( 313 struct dc_stream_state *stream, 314 const struct dc_cursor_attributes *attributes) 315 { 316 struct dc *dc; 317 #if defined(CONFIG_DRM_AMD_DC_DCN) 318 bool reset_idle_optimizations = false; 319 #endif 320 321 if (NULL == stream) { 322 dm_error("DC: dc_stream is NULL!\n"); 323 return false; 324 } 325 if (NULL == attributes) { 326 dm_error("DC: attributes is NULL!\n"); 327 return false; 328 } 329 330 if (attributes->address.quad_part == 0) { 331 dm_output_to_console("DC: Cursor address is 0!\n"); 332 return false; 333 } 334 335 dc = stream->ctx->dc; 336 stream->cursor_attributes = *attributes; 337 338 #if defined(CONFIG_DRM_AMD_DC_DCN) 339 dc_z10_restore(dc); 340 /* disable idle optimizations while updating cursor */ 341 if (dc->idle_optimizations_allowed) { 342 dc_allow_idle_optimizations(dc, false); 343 reset_idle_optimizations = true; 344 } 345 346 #endif 347 program_cursor_attributes(dc, stream, attributes); 348 349 #if defined(CONFIG_DRM_AMD_DC_DCN) 350 /* re-enable idle optimizations if necessary */ 351 if (reset_idle_optimizations) 352 dc_allow_idle_optimizations(dc, true); 353 354 #endif 355 return true; 356 } 357 358 static void program_cursor_position( 359 struct dc *dc, 360 struct dc_stream_state *stream, 361 const struct dc_cursor_position *position) 362 { 363 int i; 364 struct resource_context *res_ctx; 365 struct pipe_ctx *pipe_to_program = NULL; 366 367 if (!stream) 368 return; 369 370 res_ctx = &dc->current_state->res_ctx; 371 372 for (i = 0; i < MAX_PIPES; i++) { 373 struct pipe_ctx *pipe_ctx = &res_ctx->pipe_ctx[i]; 374 375 if (pipe_ctx->stream != stream || 376 (!pipe_ctx->plane_res.mi && !pipe_ctx->plane_res.hubp) || 377 !pipe_ctx->plane_state || 378 (!pipe_ctx->plane_res.xfm && !pipe_ctx->plane_res.dpp) || 379 (!pipe_ctx->plane_res.ipp && !pipe_ctx->plane_res.dpp)) 380 continue; 381 382 if (!pipe_to_program) { 383 pipe_to_program = pipe_ctx; 384 dc->hwss.cursor_lock(dc, pipe_to_program, true); 385 } 386 387 dc->hwss.set_cursor_position(pipe_ctx); 388 } 389 390 if (pipe_to_program) 391 dc->hwss.cursor_lock(dc, pipe_to_program, false); 392 } 393 394 bool dc_stream_set_cursor_position( 395 struct dc_stream_state *stream, 396 const struct dc_cursor_position *position) 397 { 398 struct dc *dc; 399 #if defined(CONFIG_DRM_AMD_DC_DCN) 400 bool reset_idle_optimizations = false; 401 #endif 402 403 if (NULL == stream) { 404 dm_error("DC: dc_stream is NULL!\n"); 405 return false; 406 } 407 408 if (NULL == position) { 409 dm_error("DC: cursor position is NULL!\n"); 410 return false; 411 } 412 413 dc = stream->ctx->dc; 414 #if defined(CONFIG_DRM_AMD_DC_DCN) 415 dc_z10_restore(dc); 416 417 /* disable idle optimizations if enabling cursor */ 418 if (dc->idle_optimizations_allowed && !stream->cursor_position.enable && position->enable) { 419 dc_allow_idle_optimizations(dc, false); 420 reset_idle_optimizations = true; 421 } 422 423 #endif 424 stream->cursor_position = *position; 425 426 program_cursor_position(dc, stream, position); 427 #if defined(CONFIG_DRM_AMD_DC_DCN) 428 /* re-enable idle optimizations if necessary */ 429 if (reset_idle_optimizations) 430 dc_allow_idle_optimizations(dc, true); 431 432 #endif 433 return true; 434 } 435 436 bool dc_stream_add_writeback(struct dc *dc, 437 struct dc_stream_state *stream, 438 struct dc_writeback_info *wb_info) 439 { 440 bool isDrc = false; 441 int i = 0; 442 struct dwbc *dwb; 443 444 if (stream == NULL) { 445 dm_error("DC: dc_stream is NULL!\n"); 446 return false; 447 } 448 449 if (wb_info == NULL) { 450 dm_error("DC: dc_writeback_info is NULL!\n"); 451 return false; 452 } 453 454 if (wb_info->dwb_pipe_inst >= MAX_DWB_PIPES) { 455 dm_error("DC: writeback pipe is invalid!\n"); 456 return false; 457 } 458 459 wb_info->dwb_params.out_transfer_func = stream->out_transfer_func; 460 461 dwb = dc->res_pool->dwbc[wb_info->dwb_pipe_inst]; 462 dwb->dwb_is_drc = false; 463 464 /* recalculate and apply DML parameters */ 465 466 for (i = 0; i < stream->num_wb_info; i++) { 467 /*dynamic update*/ 468 if (stream->writeback_info[i].wb_enabled && 469 stream->writeback_info[i].dwb_pipe_inst == wb_info->dwb_pipe_inst) { 470 stream->writeback_info[i] = *wb_info; 471 isDrc = true; 472 } 473 } 474 475 if (!isDrc) { 476 stream->writeback_info[stream->num_wb_info++] = *wb_info; 477 } 478 479 if (dc->hwss.enable_writeback) { 480 struct dc_stream_status *stream_status = dc_stream_get_status(stream); 481 struct dwbc *dwb = dc->res_pool->dwbc[wb_info->dwb_pipe_inst]; 482 dwb->otg_inst = stream_status->primary_otg_inst; 483 } 484 if (IS_DIAG_DC(dc->ctx->dce_environment)) { 485 if (!dc->hwss.update_bandwidth(dc, dc->current_state)) { 486 dm_error("DC: update_bandwidth failed!\n"); 487 return false; 488 } 489 490 /* enable writeback */ 491 if (dc->hwss.enable_writeback) { 492 struct dwbc *dwb = dc->res_pool->dwbc[wb_info->dwb_pipe_inst]; 493 494 if (dwb->funcs->is_enabled(dwb)) { 495 /* writeback pipe already enabled, only need to update */ 496 dc->hwss.update_writeback(dc, wb_info, dc->current_state); 497 } else { 498 /* Enable writeback pipe from scratch*/ 499 dc->hwss.enable_writeback(dc, wb_info, dc->current_state); 500 } 501 } 502 } 503 return true; 504 } 505 506 bool dc_stream_remove_writeback(struct dc *dc, 507 struct dc_stream_state *stream, 508 uint32_t dwb_pipe_inst) 509 { 510 int i = 0, j = 0; 511 if (stream == NULL) { 512 dm_error("DC: dc_stream is NULL!\n"); 513 return false; 514 } 515 516 if (dwb_pipe_inst >= MAX_DWB_PIPES) { 517 dm_error("DC: writeback pipe is invalid!\n"); 518 return false; 519 } 520 521 // stream->writeback_info[dwb_pipe_inst].wb_enabled = false; 522 for (i = 0; i < stream->num_wb_info; i++) { 523 /*dynamic update*/ 524 if (stream->writeback_info[i].wb_enabled && 525 stream->writeback_info[i].dwb_pipe_inst == dwb_pipe_inst) { 526 stream->writeback_info[i].wb_enabled = false; 527 } 528 } 529 530 /* remove writeback info for disabled writeback pipes from stream */ 531 for (i = 0, j = 0; i < stream->num_wb_info; i++) { 532 if (stream->writeback_info[i].wb_enabled) { 533 if (i != j) 534 /* trim the array */ 535 stream->writeback_info[j] = stream->writeback_info[i]; 536 j++; 537 } 538 } 539 stream->num_wb_info = j; 540 541 if (IS_DIAG_DC(dc->ctx->dce_environment)) { 542 /* recalculate and apply DML parameters */ 543 if (!dc->hwss.update_bandwidth(dc, dc->current_state)) { 544 dm_error("DC: update_bandwidth failed!\n"); 545 return false; 546 } 547 548 /* disable writeback */ 549 if (dc->hwss.disable_writeback) 550 dc->hwss.disable_writeback(dc, dwb_pipe_inst); 551 } 552 return true; 553 } 554 555 bool dc_stream_warmup_writeback(struct dc *dc, 556 int num_dwb, 557 struct dc_writeback_info *wb_info) 558 { 559 if (dc->hwss.mmhubbub_warmup) 560 return dc->hwss.mmhubbub_warmup(dc, num_dwb, wb_info); 561 else 562 return false; 563 } 564 uint32_t dc_stream_get_vblank_counter(const struct dc_stream_state *stream) 565 { 566 uint8_t i; 567 struct dc *dc = stream->ctx->dc; 568 struct resource_context *res_ctx = 569 &dc->current_state->res_ctx; 570 571 for (i = 0; i < MAX_PIPES; i++) { 572 struct timing_generator *tg = res_ctx->pipe_ctx[i].stream_res.tg; 573 574 if (res_ctx->pipe_ctx[i].stream != stream) 575 continue; 576 577 return tg->funcs->get_frame_count(tg); 578 } 579 580 return 0; 581 } 582 583 bool dc_stream_send_dp_sdp(const struct dc_stream_state *stream, 584 const uint8_t *custom_sdp_message, 585 unsigned int sdp_message_size) 586 { 587 int i; 588 struct dc *dc; 589 struct resource_context *res_ctx; 590 591 if (stream == NULL) { 592 dm_error("DC: dc_stream is NULL!\n"); 593 return false; 594 } 595 596 dc = stream->ctx->dc; 597 res_ctx = &dc->current_state->res_ctx; 598 599 for (i = 0; i < MAX_PIPES; i++) { 600 struct pipe_ctx *pipe_ctx = &res_ctx->pipe_ctx[i]; 601 602 if (pipe_ctx->stream != stream) 603 continue; 604 605 if (dc->hwss.send_immediate_sdp_message != NULL) 606 dc->hwss.send_immediate_sdp_message(pipe_ctx, 607 custom_sdp_message, 608 sdp_message_size); 609 else 610 DC_LOG_WARNING("%s:send_immediate_sdp_message not implemented on this ASIC\n", 611 __func__); 612 613 } 614 615 return true; 616 } 617 618 bool dc_stream_get_scanoutpos(const struct dc_stream_state *stream, 619 uint32_t *v_blank_start, 620 uint32_t *v_blank_end, 621 uint32_t *h_position, 622 uint32_t *v_position) 623 { 624 uint8_t i; 625 bool ret = false; 626 struct dc *dc = stream->ctx->dc; 627 struct resource_context *res_ctx = 628 &dc->current_state->res_ctx; 629 630 for (i = 0; i < MAX_PIPES; i++) { 631 struct timing_generator *tg = res_ctx->pipe_ctx[i].stream_res.tg; 632 633 if (res_ctx->pipe_ctx[i].stream != stream) 634 continue; 635 636 tg->funcs->get_scanoutpos(tg, 637 v_blank_start, 638 v_blank_end, 639 h_position, 640 v_position); 641 642 ret = true; 643 break; 644 } 645 646 return ret; 647 } 648 649 bool dc_stream_dmdata_status_done(struct dc *dc, struct dc_stream_state *stream) 650 { 651 struct pipe_ctx *pipe = NULL; 652 int i; 653 654 if (!dc->hwss.dmdata_status_done) 655 return false; 656 657 for (i = 0; i < MAX_PIPES; i++) { 658 pipe = &dc->current_state->res_ctx.pipe_ctx[i]; 659 if (pipe->stream == stream) 660 break; 661 } 662 /* Stream not found, by default we'll assume HUBP fetched dm data */ 663 if (i == MAX_PIPES) 664 return true; 665 666 return dc->hwss.dmdata_status_done(pipe); 667 } 668 669 bool dc_stream_set_dynamic_metadata(struct dc *dc, 670 struct dc_stream_state *stream, 671 struct dc_dmdata_attributes *attr) 672 { 673 struct pipe_ctx *pipe_ctx = NULL; 674 struct hubp *hubp; 675 int i; 676 677 /* Dynamic metadata is only supported on HDMI or DP */ 678 if (!dc_is_hdmi_signal(stream->signal) && !dc_is_dp_signal(stream->signal)) 679 return false; 680 681 /* Check hardware support */ 682 if (!dc->hwss.program_dmdata_engine) 683 return false; 684 685 for (i = 0; i < MAX_PIPES; i++) { 686 pipe_ctx = &dc->current_state->res_ctx.pipe_ctx[i]; 687 if (pipe_ctx->stream == stream) 688 break; 689 } 690 691 if (i == MAX_PIPES) 692 return false; 693 694 hubp = pipe_ctx->plane_res.hubp; 695 if (hubp == NULL) 696 return false; 697 698 pipe_ctx->stream->dmdata_address = attr->address; 699 700 dc->hwss.program_dmdata_engine(pipe_ctx); 701 702 if (hubp->funcs->dmdata_set_attributes != NULL && 703 pipe_ctx->stream->dmdata_address.quad_part != 0) { 704 hubp->funcs->dmdata_set_attributes(hubp, attr); 705 } 706 707 return true; 708 } 709 710 enum dc_status dc_stream_add_dsc_to_resource(struct dc *dc, 711 struct dc_state *state, 712 struct dc_stream_state *stream) 713 { 714 if (dc->res_pool->funcs->add_dsc_to_stream_resource) { 715 return dc->res_pool->funcs->add_dsc_to_stream_resource(dc, state, stream); 716 } else { 717 return DC_NO_DSC_RESOURCE; 718 } 719 } 720 721 struct pipe_ctx *dc_stream_get_pipe_ctx(struct dc_stream_state *stream) 722 { 723 int i = 0; 724 725 for (i = 0; i < MAX_PIPES; i++) { 726 struct pipe_ctx *pipe = &stream->ctx->dc->current_state->res_ctx.pipe_ctx[i]; 727 728 if (pipe->stream == stream) 729 return pipe; 730 } 731 732 return NULL; 733 } 734 735 void dc_stream_log(const struct dc *dc, const struct dc_stream_state *stream) 736 { 737 DC_LOG_DC( 738 "core_stream 0x%p: src: %d, %d, %d, %d; dst: %d, %d, %d, %d, colorSpace:%d\n", 739 stream, 740 stream->src.x, 741 stream->src.y, 742 stream->src.width, 743 stream->src.height, 744 stream->dst.x, 745 stream->dst.y, 746 stream->dst.width, 747 stream->dst.height, 748 stream->output_color_space); 749 DC_LOG_DC( 750 "\tpix_clk_khz: %d, h_total: %d, v_total: %d, pixelencoder:%d, displaycolorDepth:%d\n", 751 stream->timing.pix_clk_100hz / 10, 752 stream->timing.h_total, 753 stream->timing.v_total, 754 stream->timing.pixel_encoding, 755 stream->timing.display_color_depth); 756 DC_LOG_DC( 757 "\tlink: %d\n", 758 stream->link->link_index); 759 760 DC_LOG_DC( 761 "\tdsc: %d, mst_pbn: %d\n", 762 stream->timing.flags.DSC, 763 stream->timing.dsc_cfg.mst_pbn); 764 765 if (stream->sink) { 766 if (stream->sink->sink_signal != SIGNAL_TYPE_VIRTUAL && 767 stream->sink->sink_signal != SIGNAL_TYPE_NONE) { 768 769 DC_LOG_DC( 770 "\tdispname: %s signal: %x\n", 771 stream->sink->edid_caps.display_name, 772 stream->signal); 773 } 774 } 775 } 776 777