1 /*
2  * Copyright 2021 Advanced Micro Devices, Inc.
3  *
4  * Permission is hereby granted, free of charge, to any person obtaining a
5  * copy of this software and associated documentation files (the "Software"),
6  * to deal in the Software without restriction, including without limitation
7  * the rights to use, copy, modify, merge, publish, distribute, sublicense,
8  * and/or sell copies of the Software, and to permit persons to whom the
9  * Software is furnished to do so, subject to the following conditions:
10  *
11  * The above copyright notice and this permission notice shall be included in
12  * all copies or substantial portions of the Software.
13  *
14  * THE SOFTWARE IS PROVIDED "AS IS", WITHOUT WARRANTY OF ANY KIND, EXPRESS OR
15  * IMPLIED, INCLUDING BUT NOT LIMITED TO THE WARRANTIES OF MERCHANTABILITY,
16  * FITNESS FOR A PARTICULAR PURPOSE AND NONINFRINGEMENT.  IN NO EVENT SHALL
17  * THE COPYRIGHT HOLDER(S) OR AUTHOR(S) BE LIABLE FOR ANY CLAIM, DAMAGES OR
18  * OTHER LIABILITY, WHETHER IN AN ACTION OF CONTRACT, TORT OR OTHERWISE,
19  * ARISING FROM, OUT OF OR IN CONNECTION WITH THE SOFTWARE OR THE USE OR
20  * OTHER DEALINGS IN THE SOFTWARE.
21  *
22  * Authors: AMD
23  *
24  */
25 #ifndef SMU13_DRIVER_IF_DCN32_H
26 #define SMU13_DRIVER_IF_DCN32_H
27 
28 // *** IMPORTANT ***
29 // PMFW TEAM: Always increment the interface version on any change to this file
30 #define SMU13_DRIVER_IF_VERSION  0x18
31 
32 //Only Clks that have DPM descriptors are listed here
33 typedef enum {
34   PPCLK_GFXCLK = 0,
35   PPCLK_SOCCLK,
36   PPCLK_UCLK,
37   PPCLK_FCLK,
38   PPCLK_DCLK_0,
39   PPCLK_VCLK_0,
40   PPCLK_DCLK_1,
41   PPCLK_VCLK_1,
42   PPCLK_DISPCLK,
43   PPCLK_DPPCLK,
44   PPCLK_DPREFCLK,
45   PPCLK_DCFCLK,
46   PPCLK_DTBCLK,
47   PPCLK_COUNT,
48 } PPCLK_e;
49 
50 typedef enum {
51   UCLK_DIV_BY_1 = 0,
52   UCLK_DIV_BY_2,
53   UCLK_DIV_BY_4,
54   UCLK_DIV_BY_8,
55 } UCLK_DIV_e;
56 
57 typedef struct {
58   uint8_t  WmSetting;
59   uint8_t  Flags;
60   uint8_t  Padding[2];
61 
62 } WatermarkRowGeneric_t;
63 
64 #define NUM_WM_RANGES 4
65 
66 typedef enum {
67   WATERMARKS_CLOCK_RANGE = 0,
68   WATERMARKS_DUMMY_PSTATE,
69   WATERMARKS_MALL,
70   WATERMARKS_COUNT,
71 } WATERMARKS_FLAGS_e;
72 
73 typedef struct {
74   // Watermarks
75   WatermarkRowGeneric_t WatermarkRow[NUM_WM_RANGES];
76 } Watermarks_t;
77 
78 typedef struct {
79   Watermarks_t Watermarks;
80   uint32_t  Spare[16];
81 
82   uint32_t     MmHubPadding[8]; // SMU internal use
83 } WatermarksExternal_t;
84 
85 // These defines are used with the following messages:
86 // SMC_MSG_TransferTableDram2Smu
87 // SMC_MSG_TransferTableSmu2Dram
88 
89 // Table transfer status
90 #define TABLE_TRANSFER_OK         0x0
91 #define TABLE_TRANSFER_FAILED     0xFF
92 #define TABLE_TRANSFER_PENDING    0xAB
93 
94 // Table types
95 #define TABLE_PMFW_PPTABLE            0
96 #define TABLE_COMBO_PPTABLE           1
97 #define TABLE_WATERMARKS              2
98 #define TABLE_AVFS_PSM_DEBUG          3
99 #define TABLE_PMSTATUSLOG             4
100 #define TABLE_SMU_METRICS             5
101 #define TABLE_DRIVER_SMU_CONFIG       6
102 #define TABLE_ACTIVITY_MONITOR_COEFF  7
103 #define TABLE_OVERDRIVE               8
104 #define TABLE_I2C_COMMANDS            9
105 #define TABLE_DRIVER_INFO             10
106 #define TABLE_COUNT                   11
107 
108 #endif
109