1 /* 2 * Copyright 2021 Advanced Micro Devices, Inc. 3 * 4 * Permission is hereby granted, free of charge, to any person obtaining a 5 * copy of this software and associated documentation files (the "Software"), 6 * to deal in the Software without restriction, including without limitation 7 * the rights to use, copy, modify, merge, publish, distribute, sublicense, 8 * and/or sell copies of the Software, and to permit persons to whom the 9 * Software is furnished to do so, subject to the following conditions: 10 * 11 * The above copyright notice and this permission notice shall be included in 12 * all copies or substantial portions of the Software. 13 * 14 * THE SOFTWARE IS PROVIDED "AS IS", WITHOUT WARRANTY OF ANY KIND, EXPRESS OR 15 * IMPLIED, INCLUDING BUT NOT LIMITED TO THE WARRANTIES OF MERCHANTABILITY, 16 * FITNESS FOR A PARTICULAR PURPOSE AND NONINFRINGEMENT. IN NO EVENT SHALL 17 * THE COPYRIGHT HOLDER(S) OR AUTHOR(S) BE LIABLE FOR ANY CLAIM, DAMAGES OR 18 * OTHER LIABILITY, WHETHER IN AN ACTION OF CONTRACT, TORT OR OTHERWISE, 19 * ARISING FROM, OUT OF OR IN CONNECTION WITH THE SOFTWARE OR THE USE OR 20 * OTHER DEALINGS IN THE SOFTWARE. 21 * 22 * Authors: AMD 23 * 24 */ 25 26 #include "dccg.h" 27 #include "clk_mgr_internal.h" 28 29 #include "dcn32/dcn32_clk_mgr_smu_msg.h" 30 #include "dcn20/dcn20_clk_mgr.h" 31 #include "dce100/dce_clk_mgr.h" 32 #include "dcn31/dcn31_clk_mgr.h" 33 #include "reg_helper.h" 34 #include "core_types.h" 35 #include "dm_helpers.h" 36 #include "link.h" 37 38 #include "atomfirmware.h" 39 #include "smu13_driver_if.h" 40 41 #include "dcn/dcn_3_2_0_offset.h" 42 #include "dcn/dcn_3_2_0_sh_mask.h" 43 44 #include "dcn32/dcn32_clk_mgr.h" 45 #include "dml/dcn32/dcn32_fpu.h" 46 47 #define DCN_BASE__INST0_SEG1 0x000000C0 48 49 #define mmCLK1_CLK_PLL_REQ 0x16E37 50 #define mmCLK1_CLK0_DFS_CNTL 0x16E69 51 #define mmCLK1_CLK1_DFS_CNTL 0x16E6C 52 #define mmCLK1_CLK2_DFS_CNTL 0x16E6F 53 #define mmCLK1_CLK3_DFS_CNTL 0x16E72 54 #define mmCLK1_CLK4_DFS_CNTL 0x16E75 55 56 #define CLK1_CLK_PLL_REQ__FbMult_int_MASK 0x000001ffUL 57 #define CLK1_CLK_PLL_REQ__PllSpineDiv_MASK 0x0000f000UL 58 #define CLK1_CLK_PLL_REQ__FbMult_frac_MASK 0xffff0000UL 59 #define CLK1_CLK_PLL_REQ__FbMult_int__SHIFT 0x00000000 60 #define CLK1_CLK_PLL_REQ__PllSpineDiv__SHIFT 0x0000000c 61 #define CLK1_CLK_PLL_REQ__FbMult_frac__SHIFT 0x00000010 62 63 #define mmCLK01_CLK0_CLK_PLL_REQ 0x16E37 64 #define mmCLK01_CLK0_CLK0_DFS_CNTL 0x16E64 65 #define mmCLK01_CLK0_CLK1_DFS_CNTL 0x16E67 66 #define mmCLK01_CLK0_CLK2_DFS_CNTL 0x16E6A 67 #define mmCLK01_CLK0_CLK3_DFS_CNTL 0x16E6D 68 #define mmCLK01_CLK0_CLK4_DFS_CNTL 0x16E70 69 70 #define CLK0_CLK_PLL_REQ__FbMult_int_MASK 0x000001ffL 71 #define CLK0_CLK_PLL_REQ__PllSpineDiv_MASK 0x0000f000L 72 #define CLK0_CLK_PLL_REQ__FbMult_frac_MASK 0xffff0000L 73 #define CLK0_CLK_PLL_REQ__FbMult_int__SHIFT 0x00000000 74 #define CLK0_CLK_PLL_REQ__PllSpineDiv__SHIFT 0x0000000c 75 #define CLK0_CLK_PLL_REQ__FbMult_frac__SHIFT 0x00000010 76 77 #undef FN 78 #define FN(reg_name, field_name) \ 79 clk_mgr->clk_mgr_shift->field_name, clk_mgr->clk_mgr_mask->field_name 80 81 #define REG(reg) \ 82 (clk_mgr->regs->reg) 83 84 #define BASE_INNER(seg) DCN_BASE__INST0_SEG ## seg 85 86 #define BASE(seg) BASE_INNER(seg) 87 88 #define SR(reg_name)\ 89 .reg_name = BASE(reg ## reg_name ## _BASE_IDX) + \ 90 reg ## reg_name 91 92 #define CLK_SR_DCN32(reg_name)\ 93 .reg_name = mm ## reg_name 94 95 static const struct clk_mgr_registers clk_mgr_regs_dcn32 = { 96 CLK_REG_LIST_DCN32() 97 }; 98 99 static const struct clk_mgr_shift clk_mgr_shift_dcn32 = { 100 CLK_COMMON_MASK_SH_LIST_DCN32(__SHIFT) 101 }; 102 103 static const struct clk_mgr_mask clk_mgr_mask_dcn32 = { 104 CLK_COMMON_MASK_SH_LIST_DCN32(_MASK) 105 }; 106 107 108 #define CLK_SR_DCN321(reg_name, block, inst)\ 109 .reg_name = mm ## block ## _ ## reg_name 110 111 static const struct clk_mgr_registers clk_mgr_regs_dcn321 = { 112 CLK_REG_LIST_DCN321() 113 }; 114 115 static const struct clk_mgr_shift clk_mgr_shift_dcn321 = { 116 CLK_COMMON_MASK_SH_LIST_DCN321(__SHIFT) 117 }; 118 119 static const struct clk_mgr_mask clk_mgr_mask_dcn321 = { 120 CLK_COMMON_MASK_SH_LIST_DCN321(_MASK) 121 }; 122 123 124 /* Query SMU for all clock states for a particular clock */ 125 static void dcn32_init_single_clock(struct clk_mgr_internal *clk_mgr, PPCLK_e clk, unsigned int *entry_0, 126 unsigned int *num_levels) 127 { 128 unsigned int i; 129 char *entry_i = (char *)entry_0; 130 131 uint32_t ret = dcn30_smu_get_dpm_freq_by_index(clk_mgr, clk, 0xFF); 132 133 if (ret & (1 << 31)) 134 /* fine-grained, only min and max */ 135 *num_levels = 2; 136 else 137 /* discrete, a number of fixed states */ 138 /* will set num_levels to 0 on failure */ 139 *num_levels = ret & 0xFF; 140 141 /* if the initial message failed, num_levels will be 0 */ 142 for (i = 0; i < *num_levels; i++) { 143 *((unsigned int *)entry_i) = (dcn30_smu_get_dpm_freq_by_index(clk_mgr, clk, i) & 0xFFFF); 144 entry_i += sizeof(clk_mgr->base.bw_params->clk_table.entries[0]); 145 } 146 } 147 148 static void dcn32_build_wm_range_table(struct clk_mgr_internal *clk_mgr) 149 { 150 DC_FP_START(); 151 dcn32_build_wm_range_table_fpu(clk_mgr); 152 DC_FP_END(); 153 } 154 155 void dcn32_init_clocks(struct clk_mgr *clk_mgr_base) 156 { 157 struct clk_mgr_internal *clk_mgr = TO_CLK_MGR_INTERNAL(clk_mgr_base); 158 unsigned int num_levels; 159 struct clk_limit_num_entries *num_entries_per_clk = &clk_mgr_base->bw_params->clk_table.num_entries_per_clk; 160 unsigned int i; 161 162 memset(&(clk_mgr_base->clks), 0, sizeof(struct dc_clocks)); 163 clk_mgr_base->clks.p_state_change_support = true; 164 clk_mgr_base->clks.prev_p_state_change_support = true; 165 clk_mgr_base->clks.fclk_prev_p_state_change_support = true; 166 clk_mgr->smu_present = false; 167 clk_mgr->dpm_present = false; 168 169 if (!clk_mgr_base->bw_params) 170 return; 171 172 if (!clk_mgr_base->force_smu_not_present && dcn30_smu_get_smu_version(clk_mgr, &clk_mgr->smu_ver)) 173 clk_mgr->smu_present = true; 174 175 if (!clk_mgr->smu_present) 176 return; 177 178 dcn30_smu_check_driver_if_version(clk_mgr); 179 dcn30_smu_check_msg_header_version(clk_mgr); 180 181 /* DCFCLK */ 182 dcn32_init_single_clock(clk_mgr, PPCLK_DCFCLK, 183 &clk_mgr_base->bw_params->clk_table.entries[0].dcfclk_mhz, 184 &num_entries_per_clk->num_dcfclk_levels); 185 186 /* SOCCLK */ 187 dcn32_init_single_clock(clk_mgr, PPCLK_SOCCLK, 188 &clk_mgr_base->bw_params->clk_table.entries[0].socclk_mhz, 189 &num_entries_per_clk->num_socclk_levels); 190 191 /* DTBCLK */ 192 if (!clk_mgr->base.ctx->dc->debug.disable_dtb_ref_clk_switch) 193 dcn32_init_single_clock(clk_mgr, PPCLK_DTBCLK, 194 &clk_mgr_base->bw_params->clk_table.entries[0].dtbclk_mhz, 195 &num_entries_per_clk->num_dtbclk_levels); 196 197 /* DISPCLK */ 198 dcn32_init_single_clock(clk_mgr, PPCLK_DISPCLK, 199 &clk_mgr_base->bw_params->clk_table.entries[0].dispclk_mhz, 200 &num_entries_per_clk->num_dispclk_levels); 201 num_levels = num_entries_per_clk->num_dispclk_levels; 202 203 if (num_entries_per_clk->num_dcfclk_levels && 204 num_entries_per_clk->num_dtbclk_levels && 205 num_entries_per_clk->num_dispclk_levels) 206 clk_mgr->dpm_present = true; 207 208 if (clk_mgr_base->ctx->dc->debug.min_disp_clk_khz) { 209 for (i = 0; i < num_levels; i++) 210 if (clk_mgr_base->bw_params->clk_table.entries[i].dispclk_mhz 211 < khz_to_mhz_ceil(clk_mgr_base->ctx->dc->debug.min_disp_clk_khz)) 212 clk_mgr_base->bw_params->clk_table.entries[i].dispclk_mhz 213 = khz_to_mhz_ceil(clk_mgr_base->ctx->dc->debug.min_disp_clk_khz); 214 } 215 for (i = 0; i < num_levels; i++) 216 if (clk_mgr_base->bw_params->clk_table.entries[i].dispclk_mhz > 1950) 217 clk_mgr_base->bw_params->clk_table.entries[i].dispclk_mhz = 1950; 218 219 if (clk_mgr_base->ctx->dc->debug.min_dpp_clk_khz) { 220 for (i = 0; i < num_levels; i++) 221 if (clk_mgr_base->bw_params->clk_table.entries[i].dppclk_mhz 222 < khz_to_mhz_ceil(clk_mgr_base->ctx->dc->debug.min_dpp_clk_khz)) 223 clk_mgr_base->bw_params->clk_table.entries[i].dppclk_mhz 224 = khz_to_mhz_ceil(clk_mgr_base->ctx->dc->debug.min_dpp_clk_khz); 225 } 226 227 /* Get UCLK, update bounding box */ 228 clk_mgr_base->funcs->get_memclk_states_from_smu(clk_mgr_base); 229 230 DC_FP_START(); 231 /* WM range table */ 232 dcn32_build_wm_range_table(clk_mgr); 233 DC_FP_END(); 234 } 235 236 static void dcn32_update_clocks_update_dtb_dto(struct clk_mgr_internal *clk_mgr, 237 struct dc_state *context, 238 int ref_dtbclk_khz) 239 { 240 struct dccg *dccg = clk_mgr->dccg; 241 uint32_t tg_mask = 0; 242 int i; 243 244 for (i = 0; i < clk_mgr->base.ctx->dc->res_pool->pipe_count; i++) { 245 struct pipe_ctx *pipe_ctx = &context->res_ctx.pipe_ctx[i]; 246 struct dtbclk_dto_params dto_params = {0}; 247 248 /* use mask to program DTO once per tg */ 249 if (pipe_ctx->stream_res.tg && 250 !(tg_mask & (1 << pipe_ctx->stream_res.tg->inst))) { 251 tg_mask |= (1 << pipe_ctx->stream_res.tg->inst); 252 253 dto_params.otg_inst = pipe_ctx->stream_res.tg->inst; 254 dto_params.ref_dtbclk_khz = ref_dtbclk_khz; 255 256 dccg->funcs->set_dtbclk_dto(clk_mgr->dccg, &dto_params); 257 //dccg->funcs->set_audio_dtbclk_dto(clk_mgr->dccg, &dto_params); 258 } 259 } 260 } 261 262 /* Since DPPCLK request to PMFW needs to be exact (due to DPP DTO programming), 263 * update DPPCLK to be the exact frequency that will be set after the DPPCLK 264 * divider is updated. This will prevent rounding issues that could cause DPP 265 * refclk and DPP DTO to not match up. 266 */ 267 static void dcn32_update_dppclk_dispclk_freq(struct clk_mgr_internal *clk_mgr, struct dc_clocks *new_clocks) 268 { 269 int dpp_divider = 0; 270 int disp_divider = 0; 271 272 if (new_clocks->dppclk_khz) { 273 dpp_divider = DENTIST_DIVIDER_RANGE_SCALE_FACTOR 274 * clk_mgr->base.dentist_vco_freq_khz / new_clocks->dppclk_khz; 275 new_clocks->dppclk_khz = (DENTIST_DIVIDER_RANGE_SCALE_FACTOR * clk_mgr->base.dentist_vco_freq_khz) / dpp_divider; 276 } 277 if (new_clocks->dispclk_khz > 0) { 278 disp_divider = DENTIST_DIVIDER_RANGE_SCALE_FACTOR 279 * clk_mgr->base.dentist_vco_freq_khz / new_clocks->dispclk_khz; 280 new_clocks->dispclk_khz = (DENTIST_DIVIDER_RANGE_SCALE_FACTOR * clk_mgr->base.dentist_vco_freq_khz) / disp_divider; 281 } 282 } 283 284 void dcn32_update_clocks_update_dpp_dto(struct clk_mgr_internal *clk_mgr, 285 struct dc_state *context, bool safe_to_lower) 286 { 287 int i; 288 289 clk_mgr->dccg->ref_dppclk = clk_mgr->base.clks.dppclk_khz; 290 for (i = 0; i < clk_mgr->base.ctx->dc->res_pool->pipe_count; i++) { 291 int dpp_inst, dppclk_khz, prev_dppclk_khz; 292 293 dppclk_khz = context->res_ctx.pipe_ctx[i].plane_res.bw.dppclk_khz; 294 295 if (context->res_ctx.pipe_ctx[i].plane_res.dpp) 296 dpp_inst = context->res_ctx.pipe_ctx[i].plane_res.dpp->inst; 297 else if (!context->res_ctx.pipe_ctx[i].plane_res.dpp && dppclk_khz == 0) { 298 /* dpp == NULL && dppclk_khz == 0 is valid because of pipe harvesting. 299 * In this case just continue in loop 300 */ 301 continue; 302 } else if (!context->res_ctx.pipe_ctx[i].plane_res.dpp && dppclk_khz > 0) { 303 /* The software state is not valid if dpp resource is NULL and 304 * dppclk_khz > 0. 305 */ 306 ASSERT(false); 307 continue; 308 } 309 310 prev_dppclk_khz = clk_mgr->dccg->pipe_dppclk_khz[i]; 311 312 if (safe_to_lower || prev_dppclk_khz < dppclk_khz) 313 clk_mgr->dccg->funcs->update_dpp_dto( 314 clk_mgr->dccg, dpp_inst, dppclk_khz); 315 } 316 } 317 318 static void dcn32_update_clocks_update_dentist( 319 struct clk_mgr_internal *clk_mgr, 320 struct dc_state *context) 321 { 322 uint32_t new_disp_divider = 0; 323 uint32_t new_dispclk_wdivider = 0; 324 uint32_t old_dispclk_wdivider = 0; 325 uint32_t i; 326 uint32_t dentist_dispclk_wdivider_readback = 0; 327 struct dc *dc = clk_mgr->base.ctx->dc; 328 329 if (clk_mgr->base.clks.dispclk_khz == 0) 330 return; 331 332 new_disp_divider = DENTIST_DIVIDER_RANGE_SCALE_FACTOR 333 * clk_mgr->base.dentist_vco_freq_khz / clk_mgr->base.clks.dispclk_khz; 334 335 new_dispclk_wdivider = dentist_get_did_from_divider(new_disp_divider); 336 REG_GET(DENTIST_DISPCLK_CNTL, 337 DENTIST_DISPCLK_WDIVIDER, &old_dispclk_wdivider); 338 339 /* When changing divider to or from 127, some extra programming is required to prevent corruption */ 340 if (old_dispclk_wdivider == 127 && new_dispclk_wdivider != 127) { 341 for (i = 0; i < clk_mgr->base.ctx->dc->res_pool->pipe_count; i++) { 342 struct pipe_ctx *pipe_ctx = &context->res_ctx.pipe_ctx[i]; 343 uint32_t fifo_level; 344 struct dccg *dccg = clk_mgr->base.ctx->dc->res_pool->dccg; 345 struct stream_encoder *stream_enc = pipe_ctx->stream_res.stream_enc; 346 int32_t N; 347 int32_t j; 348 349 if (!pipe_ctx->stream) 350 continue; 351 /* Virtual encoders don't have this function */ 352 if (!stream_enc->funcs->get_fifo_cal_average_level) 353 continue; 354 fifo_level = stream_enc->funcs->get_fifo_cal_average_level( 355 stream_enc); 356 N = fifo_level / 4; 357 dccg->funcs->set_fifo_errdet_ovr_en( 358 dccg, 359 true); 360 for (j = 0; j < N - 4; j++) 361 dccg->funcs->otg_drop_pixel( 362 dccg, 363 pipe_ctx->stream_res.tg->inst); 364 dccg->funcs->set_fifo_errdet_ovr_en( 365 dccg, 366 false); 367 } 368 } else if (new_dispclk_wdivider == 127 && old_dispclk_wdivider != 127) { 369 /* request clock with 126 divider first */ 370 uint32_t temp_disp_divider = dentist_get_divider_from_did(126); 371 uint32_t temp_dispclk_khz = (DENTIST_DIVIDER_RANGE_SCALE_FACTOR * clk_mgr->base.dentist_vco_freq_khz) / temp_disp_divider; 372 373 if (clk_mgr->smu_present) 374 dcn32_smu_set_hard_min_by_freq(clk_mgr, PPCLK_DISPCLK, khz_to_mhz_ceil(temp_dispclk_khz)); 375 376 if (dc->debug.override_dispclk_programming) { 377 REG_GET(DENTIST_DISPCLK_CNTL, 378 DENTIST_DISPCLK_WDIVIDER, &dentist_dispclk_wdivider_readback); 379 380 if (dentist_dispclk_wdivider_readback != 126) { 381 REG_UPDATE(DENTIST_DISPCLK_CNTL, 382 DENTIST_DISPCLK_WDIVIDER, 126); 383 REG_WAIT(DENTIST_DISPCLK_CNTL, DENTIST_DISPCLK_CHG_DONE, 1, 50, 2000); 384 } 385 } 386 387 for (i = 0; i < clk_mgr->base.ctx->dc->res_pool->pipe_count; i++) { 388 struct pipe_ctx *pipe_ctx = &context->res_ctx.pipe_ctx[i]; 389 struct dccg *dccg = clk_mgr->base.ctx->dc->res_pool->dccg; 390 struct stream_encoder *stream_enc = pipe_ctx->stream_res.stream_enc; 391 uint32_t fifo_level; 392 int32_t N; 393 int32_t j; 394 395 if (!pipe_ctx->stream) 396 continue; 397 /* Virtual encoders don't have this function */ 398 if (!stream_enc->funcs->get_fifo_cal_average_level) 399 continue; 400 fifo_level = stream_enc->funcs->get_fifo_cal_average_level( 401 stream_enc); 402 N = fifo_level / 4; 403 dccg->funcs->set_fifo_errdet_ovr_en(dccg, true); 404 for (j = 0; j < 12 - N; j++) 405 dccg->funcs->otg_add_pixel(dccg, 406 pipe_ctx->stream_res.tg->inst); 407 dccg->funcs->set_fifo_errdet_ovr_en(dccg, false); 408 } 409 } 410 411 /* do requested DISPCLK updates*/ 412 if (clk_mgr->smu_present) 413 dcn32_smu_set_hard_min_by_freq(clk_mgr, PPCLK_DISPCLK, khz_to_mhz_ceil(clk_mgr->base.clks.dispclk_khz)); 414 415 if (dc->debug.override_dispclk_programming) { 416 REG_GET(DENTIST_DISPCLK_CNTL, 417 DENTIST_DISPCLK_WDIVIDER, &dentist_dispclk_wdivider_readback); 418 419 if (dentist_dispclk_wdivider_readback > new_dispclk_wdivider) { 420 REG_UPDATE(DENTIST_DISPCLK_CNTL, 421 DENTIST_DISPCLK_WDIVIDER, new_dispclk_wdivider); 422 REG_WAIT(DENTIST_DISPCLK_CNTL, DENTIST_DISPCLK_CHG_DONE, 1, 50, 2000); 423 } 424 } 425 426 } 427 428 static int dcn32_get_dispclk_from_dentist(struct clk_mgr *clk_mgr_base) 429 { 430 struct clk_mgr_internal *clk_mgr = TO_CLK_MGR_INTERNAL(clk_mgr_base); 431 uint32_t dispclk_wdivider; 432 int disp_divider; 433 434 REG_GET(DENTIST_DISPCLK_CNTL, DENTIST_DISPCLK_WDIVIDER, &dispclk_wdivider); 435 disp_divider = dentist_get_divider_from_did(dispclk_wdivider); 436 437 /* Return DISPCLK freq in Khz */ 438 if (disp_divider) 439 return (DENTIST_DIVIDER_RANGE_SCALE_FACTOR * clk_mgr->base.dentist_vco_freq_khz) / disp_divider; 440 441 return 0; 442 } 443 444 445 static void dcn32_update_clocks(struct clk_mgr *clk_mgr_base, 446 struct dc_state *context, 447 bool safe_to_lower) 448 { 449 struct clk_mgr_internal *clk_mgr = TO_CLK_MGR_INTERNAL(clk_mgr_base); 450 struct dc_clocks *new_clocks = &context->bw_ctx.bw.dcn.clk; 451 struct dc *dc = clk_mgr_base->ctx->dc; 452 int display_count; 453 bool update_dppclk = false; 454 bool update_dispclk = false; 455 bool enter_display_off = false; 456 bool dpp_clock_lowered = false; 457 struct dmcu *dmcu = clk_mgr_base->ctx->dc->res_pool->dmcu; 458 bool force_reset = false; 459 bool update_uclk = false, update_fclk = false; 460 bool p_state_change_support; 461 bool fclk_p_state_change_support; 462 463 if (clk_mgr_base->clks.dispclk_khz == 0 || 464 (dc->debug.force_clock_mode & 0x1)) { 465 /* This is from resume or boot up, if forced_clock cfg option used, 466 * we bypass program dispclk and DPPCLK, but need set them for S3. 467 */ 468 force_reset = true; 469 470 dcn2_read_clocks_from_hw_dentist(clk_mgr_base); 471 472 /* Force_clock_mode 0x1: force reset the clock even it is the same clock 473 * as long as it is in Passive level. 474 */ 475 } 476 display_count = clk_mgr_helper_get_active_display_cnt(dc, context); 477 478 if (display_count == 0) 479 enter_display_off = true; 480 481 if (clk_mgr->smu_present) { 482 if (enter_display_off == safe_to_lower) 483 dcn30_smu_set_num_of_displays(clk_mgr, display_count); 484 485 clk_mgr_base->clks.fclk_prev_p_state_change_support = clk_mgr_base->clks.fclk_p_state_change_support; 486 487 fclk_p_state_change_support = new_clocks->fclk_p_state_change_support; 488 489 if (should_update_pstate_support(safe_to_lower, fclk_p_state_change_support, clk_mgr_base->clks.fclk_p_state_change_support) && 490 !dc->work_arounds.clock_update_disable_mask.fclk) { 491 clk_mgr_base->clks.fclk_p_state_change_support = fclk_p_state_change_support; 492 493 /* To enable FCLK P-state switching, send FCLK_PSTATE_SUPPORTED message to PMFW */ 494 if (clk_mgr_base->ctx->dce_version != DCN_VERSION_3_21 && clk_mgr_base->clks.fclk_p_state_change_support) { 495 /* Handle the code for sending a message to PMFW that FCLK P-state change is supported */ 496 dcn32_smu_send_fclk_pstate_message(clk_mgr, FCLK_PSTATE_SUPPORTED); 497 } 498 } 499 500 if (dc->debug.force_min_dcfclk_mhz > 0) 501 new_clocks->dcfclk_khz = (new_clocks->dcfclk_khz > (dc->debug.force_min_dcfclk_mhz * 1000)) ? 502 new_clocks->dcfclk_khz : (dc->debug.force_min_dcfclk_mhz * 1000); 503 504 if (should_set_clock(safe_to_lower, new_clocks->dcfclk_khz, clk_mgr_base->clks.dcfclk_khz) && 505 !dc->work_arounds.clock_update_disable_mask.dcfclk) { 506 clk_mgr_base->clks.dcfclk_khz = new_clocks->dcfclk_khz; 507 dcn32_smu_set_hard_min_by_freq(clk_mgr, PPCLK_DCFCLK, khz_to_mhz_ceil(clk_mgr_base->clks.dcfclk_khz)); 508 } 509 510 if (should_set_clock(safe_to_lower, new_clocks->dcfclk_deep_sleep_khz, clk_mgr_base->clks.dcfclk_deep_sleep_khz) && 511 !dc->work_arounds.clock_update_disable_mask.dcfclk_ds) { 512 clk_mgr_base->clks.dcfclk_deep_sleep_khz = new_clocks->dcfclk_deep_sleep_khz; 513 dcn30_smu_set_min_deep_sleep_dcef_clk(clk_mgr, khz_to_mhz_ceil(clk_mgr_base->clks.dcfclk_deep_sleep_khz)); 514 } 515 516 if (should_set_clock(safe_to_lower, new_clocks->socclk_khz, clk_mgr_base->clks.socclk_khz)) 517 /* We don't actually care about socclk, don't notify SMU of hard min */ 518 clk_mgr_base->clks.socclk_khz = new_clocks->socclk_khz; 519 520 clk_mgr_base->clks.prev_p_state_change_support = clk_mgr_base->clks.p_state_change_support; 521 clk_mgr_base->clks.prev_num_ways = clk_mgr_base->clks.num_ways; 522 523 if (clk_mgr_base->clks.num_ways != new_clocks->num_ways && 524 clk_mgr_base->clks.num_ways < new_clocks->num_ways) { 525 clk_mgr_base->clks.num_ways = new_clocks->num_ways; 526 dcn32_smu_send_cab_for_uclk_message(clk_mgr, clk_mgr_base->clks.num_ways); 527 } 528 529 p_state_change_support = new_clocks->p_state_change_support; 530 if (should_update_pstate_support(safe_to_lower, p_state_change_support, clk_mgr_base->clks.p_state_change_support) && 531 !dc->work_arounds.clock_update_disable_mask.uclk) { 532 clk_mgr_base->clks.p_state_change_support = p_state_change_support; 533 534 /* to disable P-State switching, set UCLK min = max */ 535 if (!clk_mgr_base->clks.p_state_change_support) 536 dcn32_smu_set_hard_min_by_freq(clk_mgr, PPCLK_UCLK, 537 clk_mgr_base->bw_params->clk_table.entries[clk_mgr_base->bw_params->clk_table.num_entries_per_clk.num_memclk_levels - 1].memclk_mhz); 538 } 539 540 /* Always update saved value, even if new value not set due to P-State switching unsupported. Also check safe_to_lower for FCLK */ 541 if (safe_to_lower && (clk_mgr_base->clks.fclk_p_state_change_support != clk_mgr_base->clks.fclk_prev_p_state_change_support)) { 542 update_fclk = true; 543 } 544 545 if (clk_mgr_base->ctx->dce_version != DCN_VERSION_3_21 && !clk_mgr_base->clks.fclk_p_state_change_support && update_fclk && 546 !dc->work_arounds.clock_update_disable_mask.fclk) { 547 /* Handle code for sending a message to PMFW that FCLK P-state change is not supported */ 548 dcn32_smu_send_fclk_pstate_message(clk_mgr, FCLK_PSTATE_NOTSUPPORTED); 549 } 550 551 /* Always update saved value, even if new value not set due to P-State switching unsupported */ 552 if (should_set_clock(safe_to_lower, new_clocks->dramclk_khz, clk_mgr_base->clks.dramclk_khz) && 553 !dc->work_arounds.clock_update_disable_mask.uclk) { 554 clk_mgr_base->clks.dramclk_khz = new_clocks->dramclk_khz; 555 update_uclk = true; 556 } 557 558 /* set UCLK to requested value if P-State switching is supported, or to re-enable P-State switching */ 559 if (clk_mgr_base->clks.p_state_change_support && 560 (update_uclk || !clk_mgr_base->clks.prev_p_state_change_support) && 561 !dc->work_arounds.clock_update_disable_mask.uclk) 562 dcn32_smu_set_hard_min_by_freq(clk_mgr, PPCLK_UCLK, khz_to_mhz_ceil(clk_mgr_base->clks.dramclk_khz)); 563 564 if (clk_mgr_base->clks.num_ways != new_clocks->num_ways && 565 clk_mgr_base->clks.num_ways > new_clocks->num_ways) { 566 clk_mgr_base->clks.num_ways = new_clocks->num_ways; 567 dcn32_smu_send_cab_for_uclk_message(clk_mgr, clk_mgr_base->clks.num_ways); 568 } 569 } 570 571 dcn32_update_dppclk_dispclk_freq(clk_mgr, new_clocks); 572 if (should_set_clock(safe_to_lower, new_clocks->dppclk_khz, clk_mgr_base->clks.dppclk_khz)) { 573 if (clk_mgr_base->clks.dppclk_khz > new_clocks->dppclk_khz) 574 dpp_clock_lowered = true; 575 576 clk_mgr_base->clks.dppclk_khz = new_clocks->dppclk_khz; 577 578 if (clk_mgr->smu_present && !dpp_clock_lowered) 579 dcn32_smu_set_hard_min_by_freq(clk_mgr, PPCLK_DPPCLK, khz_to_mhz_ceil(clk_mgr_base->clks.dppclk_khz)); 580 581 update_dppclk = true; 582 } 583 584 if (should_set_clock(safe_to_lower, new_clocks->dispclk_khz, clk_mgr_base->clks.dispclk_khz)) { 585 clk_mgr_base->clks.dispclk_khz = new_clocks->dispclk_khz; 586 587 update_dispclk = true; 588 } 589 590 if (!new_clocks->dtbclk_en) { 591 new_clocks->ref_dtbclk_khz = clk_mgr_base->bw_params->clk_table.entries[0].dtbclk_mhz * 1000; 592 } 593 594 /* clock limits are received with MHz precision, divide by 1000 to prevent setting clocks at every call */ 595 if (!dc->debug.disable_dtb_ref_clk_switch && 596 should_set_clock(safe_to_lower, new_clocks->ref_dtbclk_khz / 1000, clk_mgr_base->clks.ref_dtbclk_khz / 1000)) { 597 /* DCCG requires KHz precision for DTBCLK */ 598 clk_mgr_base->clks.ref_dtbclk_khz = 599 dcn32_smu_set_hard_min_by_freq(clk_mgr, PPCLK_DTBCLK, khz_to_mhz_ceil(new_clocks->ref_dtbclk_khz)); 600 dcn32_update_clocks_update_dtb_dto(clk_mgr, context, clk_mgr_base->clks.ref_dtbclk_khz); 601 } 602 603 if (dc->config.forced_clocks == false || (force_reset && safe_to_lower)) { 604 if (dpp_clock_lowered) { 605 /* if clock is being lowered, increase DTO before lowering refclk */ 606 dcn32_update_clocks_update_dpp_dto(clk_mgr, context, safe_to_lower); 607 dcn32_update_clocks_update_dentist(clk_mgr, context); 608 if (clk_mgr->smu_present) 609 dcn32_smu_set_hard_min_by_freq(clk_mgr, PPCLK_DPPCLK, khz_to_mhz_ceil(clk_mgr_base->clks.dppclk_khz)); 610 } else { 611 /* if clock is being raised, increase refclk before lowering DTO */ 612 if (update_dppclk || update_dispclk) 613 dcn32_update_clocks_update_dentist(clk_mgr, context); 614 /* There is a check inside dcn20_update_clocks_update_dpp_dto which ensures 615 * that we do not lower dto when it is not safe to lower. We do not need to 616 * compare the current and new dppclk before calling this function. 617 */ 618 dcn32_update_clocks_update_dpp_dto(clk_mgr, context, safe_to_lower); 619 } 620 } 621 622 if (update_dispclk && dmcu && dmcu->funcs->is_dmcu_initialized(dmcu)) 623 /*update dmcu for wait_loop count*/ 624 dmcu->funcs->set_psr_wait_loop(dmcu, 625 clk_mgr_base->clks.dispclk_khz / 1000 / 7); 626 } 627 628 static uint32_t dcn32_get_vco_frequency_from_reg(struct clk_mgr_internal *clk_mgr) 629 { 630 struct fixed31_32 pll_req; 631 uint32_t pll_req_reg = 0; 632 633 /* get FbMult value */ 634 if (ASICREV_IS_GC_11_0_2(clk_mgr->base.ctx->asic_id.hw_internal_rev)) 635 pll_req_reg = REG_READ(CLK0_CLK_PLL_REQ); 636 else 637 pll_req_reg = REG_READ(CLK1_CLK_PLL_REQ); 638 639 /* set up a fixed-point number 640 * this works because the int part is on the right edge of the register 641 * and the frac part is on the left edge 642 */ 643 pll_req = dc_fixpt_from_int(pll_req_reg & clk_mgr->clk_mgr_mask->FbMult_int); 644 pll_req.value |= pll_req_reg & clk_mgr->clk_mgr_mask->FbMult_frac; 645 646 /* multiply by REFCLK period */ 647 pll_req = dc_fixpt_mul_int(pll_req, clk_mgr->dfs_ref_freq_khz); 648 649 return dc_fixpt_floor(pll_req); 650 } 651 652 static void dcn32_dump_clk_registers(struct clk_state_registers_and_bypass *regs_and_bypass, 653 struct clk_mgr *clk_mgr_base, struct clk_log_info *log_info) 654 { 655 struct clk_mgr_internal *clk_mgr = TO_CLK_MGR_INTERNAL(clk_mgr_base); 656 uint32_t dprefclk_did = 0; 657 uint32_t dcfclk_did = 0; 658 uint32_t dtbclk_did = 0; 659 uint32_t dispclk_did = 0; 660 uint32_t dppclk_did = 0; 661 uint32_t target_div = 0; 662 663 if (ASICREV_IS_GC_11_0_2(clk_mgr->base.ctx->asic_id.hw_internal_rev)) { 664 /* DFS Slice 0 is used for DISPCLK */ 665 dispclk_did = REG_READ(CLK0_CLK0_DFS_CNTL); 666 /* DFS Slice 1 is used for DPPCLK */ 667 dppclk_did = REG_READ(CLK0_CLK1_DFS_CNTL); 668 /* DFS Slice 2 is used for DPREFCLK */ 669 dprefclk_did = REG_READ(CLK0_CLK2_DFS_CNTL); 670 /* DFS Slice 3 is used for DCFCLK */ 671 dcfclk_did = REG_READ(CLK0_CLK3_DFS_CNTL); 672 /* DFS Slice 4 is used for DTBCLK */ 673 dtbclk_did = REG_READ(CLK0_CLK4_DFS_CNTL); 674 } else { 675 /* DFS Slice 0 is used for DISPCLK */ 676 dispclk_did = REG_READ(CLK1_CLK0_DFS_CNTL); 677 /* DFS Slice 1 is used for DPPCLK */ 678 dppclk_did = REG_READ(CLK1_CLK1_DFS_CNTL); 679 /* DFS Slice 2 is used for DPREFCLK */ 680 dprefclk_did = REG_READ(CLK1_CLK2_DFS_CNTL); 681 /* DFS Slice 3 is used for DCFCLK */ 682 dcfclk_did = REG_READ(CLK1_CLK3_DFS_CNTL); 683 /* DFS Slice 4 is used for DTBCLK */ 684 dtbclk_did = REG_READ(CLK1_CLK4_DFS_CNTL); 685 } 686 687 /* Convert DISPCLK DFS Slice DID to divider*/ 688 target_div = dentist_get_divider_from_did(dispclk_did); 689 //Get dispclk in khz 690 regs_and_bypass->dispclk = (DENTIST_DIVIDER_RANGE_SCALE_FACTOR 691 * clk_mgr->base.dentist_vco_freq_khz) / target_div; 692 693 /* Convert DISPCLK DFS Slice DID to divider*/ 694 target_div = dentist_get_divider_from_did(dppclk_did); 695 //Get dppclk in khz 696 regs_and_bypass->dppclk = (DENTIST_DIVIDER_RANGE_SCALE_FACTOR 697 * clk_mgr->base.dentist_vco_freq_khz) / target_div; 698 699 /* Convert DPREFCLK DFS Slice DID to divider*/ 700 target_div = dentist_get_divider_from_did(dprefclk_did); 701 //Get dprefclk in khz 702 regs_and_bypass->dprefclk = (DENTIST_DIVIDER_RANGE_SCALE_FACTOR 703 * clk_mgr->base.dentist_vco_freq_khz) / target_div; 704 705 /* Convert DCFCLK DFS Slice DID to divider*/ 706 target_div = dentist_get_divider_from_did(dcfclk_did); 707 //Get dcfclk in khz 708 regs_and_bypass->dcfclk = (DENTIST_DIVIDER_RANGE_SCALE_FACTOR 709 * clk_mgr->base.dentist_vco_freq_khz) / target_div; 710 711 /* Convert DTBCLK DFS Slice DID to divider*/ 712 target_div = dentist_get_divider_from_did(dtbclk_did); 713 //Get dtbclk in khz 714 regs_and_bypass->dtbclk = (DENTIST_DIVIDER_RANGE_SCALE_FACTOR 715 * clk_mgr->base.dentist_vco_freq_khz) / target_div; 716 } 717 718 static void dcn32_clock_read_ss_info(struct clk_mgr_internal *clk_mgr) 719 { 720 struct dc_bios *bp = clk_mgr->base.ctx->dc_bios; 721 int ss_info_num = bp->funcs->get_ss_entry_number( 722 bp, AS_SIGNAL_TYPE_GPU_PLL); 723 724 if (ss_info_num) { 725 struct spread_spectrum_info info = { { 0 } }; 726 enum bp_result result = bp->funcs->get_spread_spectrum_info( 727 bp, AS_SIGNAL_TYPE_GPU_PLL, 0, &info); 728 729 /* SSInfo.spreadSpectrumPercentage !=0 would be sign 730 * that SS is enabled 731 */ 732 if (result == BP_RESULT_OK && 733 info.spread_spectrum_percentage != 0) { 734 clk_mgr->ss_on_dprefclk = true; 735 clk_mgr->dprefclk_ss_divider = info.spread_percentage_divider; 736 737 if (info.type.CENTER_MODE == 0) { 738 /* Currently for DP Reference clock we 739 * need only SS percentage for 740 * downspread 741 */ 742 clk_mgr->dprefclk_ss_percentage = 743 info.spread_spectrum_percentage; 744 } 745 } 746 } 747 } 748 static void dcn32_notify_wm_ranges(struct clk_mgr *clk_mgr_base) 749 { 750 unsigned int i; 751 struct clk_mgr_internal *clk_mgr = TO_CLK_MGR_INTERNAL(clk_mgr_base); 752 WatermarksExternal_t *table = (WatermarksExternal_t *) clk_mgr->wm_range_table; 753 754 if (!clk_mgr->smu_present) 755 return; 756 757 if (!table) 758 return; 759 760 memset(table, 0, sizeof(*table)); 761 762 /* collect valid ranges, place in pmfw table */ 763 for (i = 0; i < WM_SET_COUNT; i++) 764 if (clk_mgr->base.bw_params->wm_table.nv_entries[i].valid) { 765 table->Watermarks.WatermarkRow[i].WmSetting = i; 766 table->Watermarks.WatermarkRow[i].Flags = clk_mgr->base.bw_params->wm_table.nv_entries[i].pmfw_breakdown.wm_type; 767 } 768 dcn30_smu_set_dram_addr_high(clk_mgr, clk_mgr->wm_range_table_addr >> 32); 769 dcn30_smu_set_dram_addr_low(clk_mgr, clk_mgr->wm_range_table_addr & 0xFFFFFFFF); 770 dcn32_smu_transfer_wm_table_dram_2_smu(clk_mgr); 771 } 772 773 /* Set min memclk to minimum, either constrained by the current mode or DPM0 */ 774 static void dcn32_set_hard_min_memclk(struct clk_mgr *clk_mgr_base, bool current_mode) 775 { 776 struct clk_mgr_internal *clk_mgr = TO_CLK_MGR_INTERNAL(clk_mgr_base); 777 778 if (!clk_mgr->smu_present) 779 return; 780 781 if (current_mode) { 782 if (clk_mgr_base->clks.p_state_change_support) 783 dcn32_smu_set_hard_min_by_freq(clk_mgr, PPCLK_UCLK, 784 khz_to_mhz_ceil(clk_mgr_base->clks.dramclk_khz)); 785 else 786 dcn32_smu_set_hard_min_by_freq(clk_mgr, PPCLK_UCLK, 787 clk_mgr_base->bw_params->clk_table.entries[clk_mgr_base->bw_params->clk_table.num_entries_per_clk.num_memclk_levels - 1].memclk_mhz); 788 } else { 789 dcn32_smu_set_hard_min_by_freq(clk_mgr, PPCLK_UCLK, 790 clk_mgr_base->bw_params->clk_table.entries[0].memclk_mhz); 791 } 792 } 793 794 /* Set max memclk to highest DPM value */ 795 static void dcn32_set_hard_max_memclk(struct clk_mgr *clk_mgr_base) 796 { 797 struct clk_mgr_internal *clk_mgr = TO_CLK_MGR_INTERNAL(clk_mgr_base); 798 799 if (!clk_mgr->smu_present) 800 return; 801 802 dcn30_smu_set_hard_max_by_freq(clk_mgr, PPCLK_UCLK, 803 clk_mgr_base->bw_params->clk_table.entries[clk_mgr_base->bw_params->clk_table.num_entries_per_clk.num_memclk_levels - 1].memclk_mhz); 804 } 805 806 /* Get current memclk states, update bounding box */ 807 static void dcn32_get_memclk_states_from_smu(struct clk_mgr *clk_mgr_base) 808 { 809 struct clk_mgr_internal *clk_mgr = TO_CLK_MGR_INTERNAL(clk_mgr_base); 810 struct clk_limit_num_entries *num_entries_per_clk = &clk_mgr_base->bw_params->clk_table.num_entries_per_clk; 811 unsigned int num_levels; 812 813 if (!clk_mgr->smu_present) 814 return; 815 816 /* Refresh memclk and fclk states */ 817 dcn32_init_single_clock(clk_mgr, PPCLK_UCLK, 818 &clk_mgr_base->bw_params->clk_table.entries[0].memclk_mhz, 819 &num_entries_per_clk->num_memclk_levels); 820 821 /* memclk must have at least one level */ 822 num_entries_per_clk->num_memclk_levels = num_entries_per_clk->num_memclk_levels ? num_entries_per_clk->num_memclk_levels : 1; 823 824 dcn32_init_single_clock(clk_mgr, PPCLK_FCLK, 825 &clk_mgr_base->bw_params->clk_table.entries[0].fclk_mhz, 826 &num_entries_per_clk->num_fclk_levels); 827 828 if (num_entries_per_clk->num_memclk_levels >= num_entries_per_clk->num_fclk_levels) { 829 num_levels = num_entries_per_clk->num_memclk_levels; 830 } else { 831 num_levels = num_entries_per_clk->num_fclk_levels; 832 } 833 834 clk_mgr_base->bw_params->clk_table.num_entries = num_levels ? num_levels : 1; 835 836 if (clk_mgr->dpm_present && !num_levels) 837 clk_mgr->dpm_present = false; 838 839 if (!clk_mgr->dpm_present) 840 dcn32_patch_dpm_table(clk_mgr_base->bw_params); 841 842 DC_FP_START(); 843 /* Refresh bounding box */ 844 clk_mgr_base->ctx->dc->res_pool->funcs->update_bw_bounding_box( 845 clk_mgr->base.ctx->dc, clk_mgr_base->bw_params); 846 DC_FP_END(); 847 } 848 849 static bool dcn32_are_clock_states_equal(struct dc_clocks *a, 850 struct dc_clocks *b) 851 { 852 if (a->dispclk_khz != b->dispclk_khz) 853 return false; 854 else if (a->dppclk_khz != b->dppclk_khz) 855 return false; 856 else if (a->dcfclk_khz != b->dcfclk_khz) 857 return false; 858 else if (a->dcfclk_deep_sleep_khz != b->dcfclk_deep_sleep_khz) 859 return false; 860 else if (a->dramclk_khz != b->dramclk_khz) 861 return false; 862 else if (a->p_state_change_support != b->p_state_change_support) 863 return false; 864 else if (a->fclk_p_state_change_support != b->fclk_p_state_change_support) 865 return false; 866 867 return true; 868 } 869 870 static void dcn32_enable_pme_wa(struct clk_mgr *clk_mgr_base) 871 { 872 struct clk_mgr_internal *clk_mgr = TO_CLK_MGR_INTERNAL(clk_mgr_base); 873 874 if (!clk_mgr->smu_present) 875 return; 876 877 dcn32_smu_set_pme_workaround(clk_mgr); 878 } 879 880 static bool dcn32_is_smu_present(struct clk_mgr *clk_mgr_base) 881 { 882 struct clk_mgr_internal *clk_mgr = TO_CLK_MGR_INTERNAL(clk_mgr_base); 883 return clk_mgr->smu_present; 884 } 885 886 887 static struct clk_mgr_funcs dcn32_funcs = { 888 .get_dp_ref_clk_frequency = dce12_get_dp_ref_freq_khz, 889 .get_dtb_ref_clk_frequency = dcn31_get_dtb_ref_freq_khz, 890 .update_clocks = dcn32_update_clocks, 891 .dump_clk_registers = dcn32_dump_clk_registers, 892 .init_clocks = dcn32_init_clocks, 893 .notify_wm_ranges = dcn32_notify_wm_ranges, 894 .set_hard_min_memclk = dcn32_set_hard_min_memclk, 895 .set_hard_max_memclk = dcn32_set_hard_max_memclk, 896 .get_memclk_states_from_smu = dcn32_get_memclk_states_from_smu, 897 .are_clock_states_equal = dcn32_are_clock_states_equal, 898 .enable_pme_wa = dcn32_enable_pme_wa, 899 .is_smu_present = dcn32_is_smu_present, 900 .get_dispclk_from_dentist = dcn32_get_dispclk_from_dentist, 901 }; 902 903 void dcn32_clk_mgr_construct( 904 struct dc_context *ctx, 905 struct clk_mgr_internal *clk_mgr, 906 struct pp_smu_funcs *pp_smu, 907 struct dccg *dccg) 908 { 909 struct clk_log_info log_info = {0}; 910 911 clk_mgr->base.ctx = ctx; 912 clk_mgr->base.funcs = &dcn32_funcs; 913 if (ASICREV_IS_GC_11_0_2(clk_mgr->base.ctx->asic_id.hw_internal_rev)) { 914 clk_mgr->regs = &clk_mgr_regs_dcn321; 915 clk_mgr->clk_mgr_shift = &clk_mgr_shift_dcn321; 916 clk_mgr->clk_mgr_mask = &clk_mgr_mask_dcn321; 917 } else { 918 clk_mgr->regs = &clk_mgr_regs_dcn32; 919 clk_mgr->clk_mgr_shift = &clk_mgr_shift_dcn32; 920 clk_mgr->clk_mgr_mask = &clk_mgr_mask_dcn32; 921 } 922 923 clk_mgr->dccg = dccg; 924 clk_mgr->dfs_bypass_disp_clk = 0; 925 926 clk_mgr->dprefclk_ss_percentage = 0; 927 clk_mgr->dprefclk_ss_divider = 1000; 928 clk_mgr->ss_on_dprefclk = false; 929 clk_mgr->dfs_ref_freq_khz = 100000; 930 931 /* Changed from DCN3.2_clock_frequency doc to match 932 * dcn32_dump_clk_registers from 4 * dentist_vco_freq_khz / 933 * dprefclk DID divider 934 */ 935 clk_mgr->base.dprefclk_khz = 716666; 936 if (ctx->dc->debug.disable_dtb_ref_clk_switch) { 937 //initialize DTB ref clock value if DPM disabled 938 if (ctx->dce_version == DCN_VERSION_3_21) 939 clk_mgr->base.clks.ref_dtbclk_khz = 477800; 940 else 941 clk_mgr->base.clks.ref_dtbclk_khz = 268750; 942 } 943 944 945 /* integer part is now VCO frequency in kHz */ 946 clk_mgr->base.dentist_vco_freq_khz = dcn32_get_vco_frequency_from_reg(clk_mgr); 947 948 /* in case we don't get a value from the register, use default */ 949 if (clk_mgr->base.dentist_vco_freq_khz == 0) 950 clk_mgr->base.dentist_vco_freq_khz = 4300000; /* Updated as per HW docs */ 951 952 dcn32_dump_clk_registers(&clk_mgr->base.boot_snapshot, &clk_mgr->base, &log_info); 953 954 if (ctx->dc->debug.disable_dtb_ref_clk_switch && 955 clk_mgr->base.clks.ref_dtbclk_khz != clk_mgr->base.boot_snapshot.dtbclk) { 956 clk_mgr->base.clks.ref_dtbclk_khz = clk_mgr->base.boot_snapshot.dtbclk; 957 } 958 959 if (clk_mgr->base.boot_snapshot.dprefclk != 0) { 960 clk_mgr->base.dprefclk_khz = clk_mgr->base.boot_snapshot.dprefclk; 961 } 962 dcn32_clock_read_ss_info(clk_mgr); 963 964 clk_mgr->dfs_bypass_enabled = false; 965 966 clk_mgr->smu_present = false; 967 968 clk_mgr->base.bw_params = kzalloc(sizeof(*clk_mgr->base.bw_params), GFP_KERNEL); 969 970 /* need physical address of table to give to PMFW */ 971 clk_mgr->wm_range_table = dm_helpers_allocate_gpu_mem(clk_mgr->base.ctx, 972 DC_MEM_ALLOC_TYPE_GART, sizeof(WatermarksExternal_t), 973 &clk_mgr->wm_range_table_addr); 974 } 975 976 void dcn32_clk_mgr_destroy(struct clk_mgr_internal *clk_mgr) 977 { 978 kfree(clk_mgr->base.bw_params); 979 980 if (clk_mgr->wm_range_table) 981 dm_helpers_free_gpu_mem(clk_mgr->base.ctx, DC_MEM_ALLOC_TYPE_GART, 982 clk_mgr->wm_range_table); 983 } 984 985