1*265280b9SAurabindo Pillai /* SPDX-License-Identifier: MIT */ 2*265280b9SAurabindo Pillai /* 3*265280b9SAurabindo Pillai * Copyright 2022 Advanced Micro Devices, Inc. 4*265280b9SAurabindo Pillai * 5*265280b9SAurabindo Pillai * Permission is hereby granted, free of charge, to any person obtaining a 6*265280b9SAurabindo Pillai * copy of this software and associated documentation files (the "Software"), 7*265280b9SAurabindo Pillai * to deal in the Software without restriction, including without limitation 8*265280b9SAurabindo Pillai * the rights to use, copy, modify, merge, publish, distribute, sublicense, 9*265280b9SAurabindo Pillai * and/or sell copies of the Software, and to permit persons to whom the 10*265280b9SAurabindo Pillai * Software is furnished to do so, subject to the following conditions: 11*265280b9SAurabindo Pillai * 12*265280b9SAurabindo Pillai * The above copyright notice and this permission notice shall be included in 13*265280b9SAurabindo Pillai * all copies or substantial portions of the Software. 14*265280b9SAurabindo Pillai * 15*265280b9SAurabindo Pillai * THE SOFTWARE IS PROVIDED "AS IS", WITHOUT WARRANTY OF ANY KIND, EXPRESS OR 16*265280b9SAurabindo Pillai * IMPLIED, INCLUDING BUT NOT LIMITED TO THE WARRANTIES OF MERCHANTABILITY, 17*265280b9SAurabindo Pillai * FITNESS FOR A PARTICULAR PURPOSE AND NONINFRINGEMENT. IN NO EVENT SHALL 18*265280b9SAurabindo Pillai * THE COPYRIGHT HOLDER(S) OR AUTHOR(S) BE LIABLE FOR ANY CLAIM, DAMAGES OR 19*265280b9SAurabindo Pillai * OTHER LIABILITY, WHETHER IN AN ACTION OF CONTRACT, TORT OR OTHERWISE, 20*265280b9SAurabindo Pillai * ARISING FROM, OUT OF OR IN CONNECTION WITH THE SOFTWARE OR THE USE OR 21*265280b9SAurabindo Pillai * OTHER DEALINGS IN THE SOFTWARE. 22*265280b9SAurabindo Pillai * 23*265280b9SAurabindo Pillai * Authors: AMD 24*265280b9SAurabindo Pillai * 25*265280b9SAurabindo Pillai */ 26*265280b9SAurabindo Pillai #ifndef DALSMC_H 27*265280b9SAurabindo Pillai #define DALSMC_H 28*265280b9SAurabindo Pillai 29*265280b9SAurabindo Pillai #define DALSMC_VERSION 0x1 30*265280b9SAurabindo Pillai 31*265280b9SAurabindo Pillai // SMU Response Codes: 32*265280b9SAurabindo Pillai #define DALSMC_Result_OK 0x1 33*265280b9SAurabindo Pillai #define DALSMC_Result_Failed 0xFF 34*265280b9SAurabindo Pillai #define DALSMC_Result_UnknownCmd 0xFE 35*265280b9SAurabindo Pillai #define DALSMC_Result_CmdRejectedPrereq 0xFD 36*265280b9SAurabindo Pillai #define DALSMC_Result_CmdRejectedBusy 0xFC 37*265280b9SAurabindo Pillai 38*265280b9SAurabindo Pillai // Message Definitions: 39*265280b9SAurabindo Pillai #define DALSMC_MSG_TestMessage 0x1 40*265280b9SAurabindo Pillai #define DALSMC_MSG_GetSmuVersion 0x2 41*265280b9SAurabindo Pillai #define DALSMC_MSG_GetDriverIfVersion 0x3 42*265280b9SAurabindo Pillai #define DALSMC_MSG_GetMsgHeaderVersion 0x4 43*265280b9SAurabindo Pillai #define DALSMC_MSG_SetDalDramAddrHigh 0x5 44*265280b9SAurabindo Pillai #define DALSMC_MSG_SetDalDramAddrLow 0x6 45*265280b9SAurabindo Pillai #define DALSMC_MSG_TransferTableSmu2Dram 0x7 46*265280b9SAurabindo Pillai #define DALSMC_MSG_TransferTableDram2Smu 0x8 47*265280b9SAurabindo Pillai #define DALSMC_MSG_SetHardMinByFreq 0x9 48*265280b9SAurabindo Pillai #define DALSMC_MSG_SetHardMaxByFreq 0xA 49*265280b9SAurabindo Pillai #define DALSMC_MSG_GetDpmFreqByIndex 0xB 50*265280b9SAurabindo Pillai #define DALSMC_MSG_GetDcModeMaxDpmFreq 0xC 51*265280b9SAurabindo Pillai #define DALSMC_MSG_SetMinDeepSleepDcfclk 0xD 52*265280b9SAurabindo Pillai #define DALSMC_MSG_NumOfDisplays 0xE 53*265280b9SAurabindo Pillai #define DALSMC_MSG_SetExternalClientDfCstateAllow 0xF 54*265280b9SAurabindo Pillai #define DALSMC_MSG_BacoAudioD3PME 0x10 55*265280b9SAurabindo Pillai #define DALSMC_MSG_SetFclkSwitchAllow 0x11 56*265280b9SAurabindo Pillai #define DALSMC_MSG_SetCabForUclkPstate 0x12 57*265280b9SAurabindo Pillai #define DALSMC_MSG_SetWorstCaseUclkLatency 0x13 58*265280b9SAurabindo Pillai #define DALSMC_Message_Count 0x14 59*265280b9SAurabindo Pillai 60*265280b9SAurabindo Pillai typedef enum { 61*265280b9SAurabindo Pillai FCLK_SWITCH_DISALLOW, 62*265280b9SAurabindo Pillai FCLK_SWITCH_ALLOW, 63*265280b9SAurabindo Pillai } FclkSwitchAllow_e; 64*265280b9SAurabindo Pillai 65*265280b9SAurabindo Pillai #endif 66