1 /* 2 * Copyright 2021 Advanced Micro Devices, Inc. 3 * 4 * Permission is hereby granted, free of charge, to any person obtaining a 5 * copy of this software and associated documentation files (the "Software"), 6 * to deal in the Software without restriction, including without limitation 7 * the rights to use, copy, modify, merge, publish, distribute, sublicense, 8 * and/or sell copies of the Software, and to permit persons to whom the 9 * Software is furnished to do so, subject to the following conditions: 10 * 11 * The above copyright notice and this permission notice shall be included in 12 * all copies or substantial portions of the Software. 13 * 14 * THE SOFTWARE IS PROVIDED "AS IS", WITHOUT WARRANTY OF ANY KIND, EXPRESS OR 15 * IMPLIED, INCLUDING BUT NOT LIMITED TO THE WARRANTIES OF MERCHANTABILITY, 16 * FITNESS FOR A PARTICULAR PURPOSE AND NONINFRINGEMENT. IN NO EVENT SHALL 17 * THE COPYRIGHT HOLDER(S) OR AUTHOR(S) BE LIABLE FOR ANY CLAIM, DAMAGES OR 18 * OTHER LIABILITY, WHETHER IN AN ACTION OF CONTRACT, TORT OR OTHERWISE, 19 * ARISING FROM, OUT OF OR IN CONNECTION WITH THE SOFTWARE OR THE USE OR 20 * OTHER DEALINGS IN THE SOFTWARE. 21 * 22 * Authors: AMD 23 * 24 */ 25 26 27 28 #include "dccg.h" 29 #include "clk_mgr_internal.h" 30 31 // For dce12_get_dp_ref_freq_khz 32 #include "dce100/dce_clk_mgr.h" 33 // For dcn20_update_clocks_update_dpp_dto 34 #include "dcn20/dcn20_clk_mgr.h" 35 #include "dcn31/dcn31_clk_mgr.h" 36 #include "dcn316_clk_mgr.h" 37 #include "reg_helper.h" 38 #include "core_types.h" 39 #include "dcn316_smu.h" 40 #include "dm_helpers.h" 41 #include "dc_dmub_srv.h" 42 #include "dc_link_dp.h" 43 44 // DCN316 this is CLK1 instance 45 #define MAX_INSTANCE 7 46 #define MAX_SEGMENT 6 47 48 struct IP_BASE_INSTANCE 49 { 50 unsigned int segment[MAX_SEGMENT]; 51 }; 52 53 struct IP_BASE 54 { 55 struct IP_BASE_INSTANCE instance[MAX_INSTANCE]; 56 }; 57 58 static const struct IP_BASE CLK_BASE = { { { { 0x00016C00, 0x02401800, 0, 0, 0, 0 } }, 59 { { 0x00016E00, 0x02401C00, 0, 0, 0, 0 } }, 60 { { 0x00017000, 0x02402000, 0, 0, 0, 0 } }, 61 { { 0x00017200, 0x02402400, 0, 0, 0, 0 } }, 62 { { 0x0001B000, 0x0242D800, 0, 0, 0, 0 } }, 63 { { 0x0001B200, 0x0242DC00, 0, 0, 0, 0 } }, 64 { { 0x0001B400, 0x0242E000, 0, 0, 0, 0 } } } }; 65 66 #define regCLK1_CLK_PLL_REQ 0x0237 67 #define regCLK1_CLK_PLL_REQ_BASE_IDX 0 68 69 #define CLK1_CLK_PLL_REQ__FbMult_int__SHIFT 0x0 70 #define CLK1_CLK_PLL_REQ__PllSpineDiv__SHIFT 0xc 71 #define CLK1_CLK_PLL_REQ__FbMult_frac__SHIFT 0x10 72 #define CLK1_CLK_PLL_REQ__FbMult_int_MASK 0x000001FFL 73 #define CLK1_CLK_PLL_REQ__PllSpineDiv_MASK 0x0000F000L 74 #define CLK1_CLK_PLL_REQ__FbMult_frac_MASK 0xFFFF0000L 75 76 #define REG(reg_name) \ 77 (CLK_BASE.instance[0].segment[reg ## reg_name ## _BASE_IDX] + reg ## reg_name) 78 79 #define TO_CLK_MGR_DCN316(clk_mgr)\ 80 container_of(clk_mgr, struct clk_mgr_dcn316, base) 81 82 static int dcn316_get_active_display_cnt_wa( 83 struct dc *dc, 84 struct dc_state *context) 85 { 86 int i, display_count; 87 bool tmds_present = false; 88 89 display_count = 0; 90 for (i = 0; i < context->stream_count; i++) { 91 const struct dc_stream_state *stream = context->streams[i]; 92 93 if (stream->signal == SIGNAL_TYPE_HDMI_TYPE_A || 94 stream->signal == SIGNAL_TYPE_DVI_SINGLE_LINK || 95 stream->signal == SIGNAL_TYPE_DVI_DUAL_LINK) 96 tmds_present = true; 97 } 98 99 for (i = 0; i < dc->link_count; i++) { 100 const struct dc_link *link = dc->links[i]; 101 102 /* abusing the fact that the dig and phy are coupled to see if the phy is enabled */ 103 if (link->link_enc && link->link_enc->funcs->is_dig_enabled && 104 link->link_enc->funcs->is_dig_enabled(link->link_enc)) 105 display_count++; 106 } 107 108 /* WA for hang on HDMI after display off back back on*/ 109 if (display_count == 0 && tmds_present) 110 display_count = 1; 111 112 return display_count; 113 } 114 115 static void dcn316_disable_otg_wa(struct clk_mgr *clk_mgr_base, bool disable) 116 { 117 struct dc *dc = clk_mgr_base->ctx->dc; 118 int i; 119 120 for (i = 0; i < dc->res_pool->pipe_count; ++i) { 121 struct pipe_ctx *pipe = &dc->current_state->res_ctx.pipe_ctx[i]; 122 123 if (pipe->top_pipe || pipe->prev_odm_pipe) 124 continue; 125 if (pipe->stream && (pipe->stream->dpms_off || dc_is_virtual_signal(pipe->stream->signal))) { 126 if (disable) 127 pipe->stream_res.tg->funcs->immediate_disable_crtc(pipe->stream_res.tg); 128 else 129 pipe->stream_res.tg->funcs->enable_crtc(pipe->stream_res.tg); 130 } 131 } 132 } 133 134 static void dcn316_enable_pme_wa(struct clk_mgr *clk_mgr_base) 135 { 136 struct clk_mgr_internal *clk_mgr = TO_CLK_MGR_INTERNAL(clk_mgr_base); 137 138 dcn316_smu_enable_pme_wa(clk_mgr); 139 } 140 141 static void dcn316_update_clocks(struct clk_mgr *clk_mgr_base, 142 struct dc_state *context, 143 bool safe_to_lower) 144 { 145 union dmub_rb_cmd cmd; 146 struct clk_mgr_internal *clk_mgr = TO_CLK_MGR_INTERNAL(clk_mgr_base); 147 struct dc_clocks *new_clocks = &context->bw_ctx.bw.dcn.clk; 148 struct dc *dc = clk_mgr_base->ctx->dc; 149 int display_count; 150 bool update_dppclk = false; 151 bool update_dispclk = false; 152 bool dpp_clock_lowered = false; 153 154 if (dc->work_arounds.skip_clock_update) 155 return; 156 157 /* 158 * if it is safe to lower, but we are already in the lower state, we don't have to do anything 159 * also if safe to lower is false, we just go in the higher state 160 */ 161 clk_mgr_base->clks.zstate_support = new_clocks->zstate_support; 162 if (safe_to_lower) { 163 if (clk_mgr_base->clks.dtbclk_en && !new_clocks->dtbclk_en) { 164 dcn316_smu_set_dtbclk(clk_mgr, false); 165 clk_mgr_base->clks.dtbclk_en = new_clocks->dtbclk_en; 166 } 167 /* check that we're not already in lower */ 168 if (clk_mgr_base->clks.pwr_state != DCN_PWR_STATE_LOW_POWER) { 169 display_count = dcn316_get_active_display_cnt_wa(dc, context); 170 /* if we can go lower, go lower */ 171 if (display_count == 0) { 172 union display_idle_optimization_u idle_info = { 0 }; 173 idle_info.idle_info.df_request_disabled = 1; 174 idle_info.idle_info.phy_ref_clk_off = 1; 175 idle_info.idle_info.s0i2_rdy = 1; 176 dcn316_smu_set_display_idle_optimization(clk_mgr, idle_info.data); 177 /* update power state */ 178 clk_mgr_base->clks.pwr_state = DCN_PWR_STATE_LOW_POWER; 179 } 180 } 181 } else { 182 if (!clk_mgr_base->clks.dtbclk_en && new_clocks->dtbclk_en) { 183 dcn316_smu_set_dtbclk(clk_mgr, true); 184 clk_mgr_base->clks.dtbclk_en = new_clocks->dtbclk_en; 185 } 186 187 /* check that we're not already in D0 */ 188 if (clk_mgr_base->clks.pwr_state != DCN_PWR_STATE_MISSION_MODE) { 189 union display_idle_optimization_u idle_info = { 0 }; 190 dcn316_smu_set_display_idle_optimization(clk_mgr, idle_info.data); 191 /* update power state */ 192 clk_mgr_base->clks.pwr_state = DCN_PWR_STATE_MISSION_MODE; 193 } 194 } 195 196 if (should_set_clock(safe_to_lower, new_clocks->dcfclk_khz, clk_mgr_base->clks.dcfclk_khz)) { 197 clk_mgr_base->clks.dcfclk_khz = new_clocks->dcfclk_khz; 198 dcn316_smu_set_hard_min_dcfclk(clk_mgr, clk_mgr_base->clks.dcfclk_khz); 199 } 200 201 if (should_set_clock(safe_to_lower, 202 new_clocks->dcfclk_deep_sleep_khz, clk_mgr_base->clks.dcfclk_deep_sleep_khz)) { 203 clk_mgr_base->clks.dcfclk_deep_sleep_khz = new_clocks->dcfclk_deep_sleep_khz; 204 dcn316_smu_set_min_deep_sleep_dcfclk(clk_mgr, clk_mgr_base->clks.dcfclk_deep_sleep_khz); 205 } 206 207 // workaround: Limit dppclk to 100Mhz to avoid lower eDP panel switch to plus 4K monitor underflow. 208 if (!IS_DIAG_DC(dc->ctx->dce_environment)) { 209 if (new_clocks->dppclk_khz < 100000) 210 new_clocks->dppclk_khz = 100000; 211 if (new_clocks->dispclk_khz < 100000) 212 new_clocks->dispclk_khz = 100000; 213 } 214 215 if (should_set_clock(safe_to_lower, new_clocks->dppclk_khz, clk_mgr->base.clks.dppclk_khz)) { 216 if (clk_mgr->base.clks.dppclk_khz > new_clocks->dppclk_khz) 217 dpp_clock_lowered = true; 218 clk_mgr_base->clks.dppclk_khz = new_clocks->dppclk_khz; 219 update_dppclk = true; 220 } 221 222 if (should_set_clock(safe_to_lower, new_clocks->dispclk_khz, clk_mgr_base->clks.dispclk_khz)) { 223 dcn316_disable_otg_wa(clk_mgr_base, true); 224 225 clk_mgr_base->clks.dispclk_khz = new_clocks->dispclk_khz; 226 dcn316_smu_set_dispclk(clk_mgr, clk_mgr_base->clks.dispclk_khz); 227 dcn316_disable_otg_wa(clk_mgr_base, false); 228 229 update_dispclk = true; 230 } 231 232 if (dpp_clock_lowered) { 233 // increase per DPP DTO before lowering global dppclk 234 dcn20_update_clocks_update_dpp_dto(clk_mgr, context, safe_to_lower); 235 dcn316_smu_set_dppclk(clk_mgr, clk_mgr_base->clks.dppclk_khz); 236 } else { 237 // increase global DPPCLK before lowering per DPP DTO 238 if (update_dppclk || update_dispclk) 239 dcn316_smu_set_dppclk(clk_mgr, clk_mgr_base->clks.dppclk_khz); 240 // always update dtos unless clock is lowered and not safe to lower 241 if (new_clocks->dppclk_khz >= dc->current_state->bw_ctx.bw.dcn.clk.dppclk_khz) 242 dcn20_update_clocks_update_dpp_dto(clk_mgr, context, safe_to_lower); 243 } 244 245 // notify DMCUB of latest clocks 246 memset(&cmd, 0, sizeof(cmd)); 247 cmd.notify_clocks.header.type = DMUB_CMD__CLK_MGR; 248 cmd.notify_clocks.header.sub_type = DMUB_CMD__CLK_MGR_NOTIFY_CLOCKS; 249 cmd.notify_clocks.clocks.dcfclk_khz = clk_mgr_base->clks.dcfclk_khz; 250 cmd.notify_clocks.clocks.dcfclk_deep_sleep_khz = 251 clk_mgr_base->clks.dcfclk_deep_sleep_khz; 252 cmd.notify_clocks.clocks.dispclk_khz = clk_mgr_base->clks.dispclk_khz; 253 cmd.notify_clocks.clocks.dppclk_khz = clk_mgr_base->clks.dppclk_khz; 254 255 dc_dmub_srv_cmd_queue(dc->ctx->dmub_srv, &cmd); 256 dc_dmub_srv_cmd_execute(dc->ctx->dmub_srv); 257 dc_dmub_srv_wait_idle(dc->ctx->dmub_srv); 258 } 259 260 static void dcn316_dump_clk_registers(struct clk_state_registers_and_bypass *regs_and_bypass, 261 struct clk_mgr *clk_mgr_base, struct clk_log_info *log_info) 262 { 263 return; 264 } 265 266 static struct clk_bw_params dcn316_bw_params = { 267 .vram_type = Ddr4MemType, 268 .num_channels = 1, 269 .clk_table = { 270 .num_entries = 5, 271 }, 272 273 }; 274 275 static struct wm_table ddr4_wm_table = { 276 .entries = { 277 { 278 .wm_inst = WM_A, 279 .wm_type = WM_TYPE_PSTATE_CHG, 280 .pstate_latency_us = 11.72, 281 .sr_exit_time_us = 6.09, 282 .sr_enter_plus_exit_time_us = 7.14, 283 .valid = true, 284 }, 285 { 286 .wm_inst = WM_B, 287 .wm_type = WM_TYPE_PSTATE_CHG, 288 .pstate_latency_us = 11.72, 289 .sr_exit_time_us = 10.12, 290 .sr_enter_plus_exit_time_us = 11.48, 291 .valid = true, 292 }, 293 { 294 .wm_inst = WM_C, 295 .wm_type = WM_TYPE_PSTATE_CHG, 296 .pstate_latency_us = 11.72, 297 .sr_exit_time_us = 10.12, 298 .sr_enter_plus_exit_time_us = 11.48, 299 .valid = true, 300 }, 301 { 302 .wm_inst = WM_D, 303 .wm_type = WM_TYPE_PSTATE_CHG, 304 .pstate_latency_us = 11.72, 305 .sr_exit_time_us = 10.12, 306 .sr_enter_plus_exit_time_us = 11.48, 307 .valid = true, 308 }, 309 } 310 }; 311 312 static struct wm_table lpddr5_wm_table = { 313 .entries = { 314 { 315 .wm_inst = WM_A, 316 .wm_type = WM_TYPE_PSTATE_CHG, 317 .pstate_latency_us = 11.65333, 318 .sr_exit_time_us = 11.5, 319 .sr_enter_plus_exit_time_us = 14.5, 320 .valid = true, 321 }, 322 { 323 .wm_inst = WM_B, 324 .wm_type = WM_TYPE_PSTATE_CHG, 325 .pstate_latency_us = 11.65333, 326 .sr_exit_time_us = 11.5, 327 .sr_enter_plus_exit_time_us = 14.5, 328 .valid = true, 329 }, 330 { 331 .wm_inst = WM_C, 332 .wm_type = WM_TYPE_PSTATE_CHG, 333 .pstate_latency_us = 11.65333, 334 .sr_exit_time_us = 11.5, 335 .sr_enter_plus_exit_time_us = 14.5, 336 .valid = true, 337 }, 338 { 339 .wm_inst = WM_D, 340 .wm_type = WM_TYPE_PSTATE_CHG, 341 .pstate_latency_us = 11.65333, 342 .sr_exit_time_us = 11.5, 343 .sr_enter_plus_exit_time_us = 14.5, 344 .valid = true, 345 }, 346 } 347 }; 348 349 static DpmClocks_316_t dummy_clocks; 350 351 static struct dcn316_watermarks dummy_wms = { 0 }; 352 353 static void dcn316_build_watermark_ranges(struct clk_bw_params *bw_params, struct dcn316_watermarks *table) 354 { 355 int i, num_valid_sets; 356 357 num_valid_sets = 0; 358 359 for (i = 0; i < WM_SET_COUNT; i++) { 360 /* skip empty entries, the smu array has no holes*/ 361 if (!bw_params->wm_table.entries[i].valid) 362 continue; 363 364 table->WatermarkRow[WM_DCFCLK][num_valid_sets].WmSetting = bw_params->wm_table.entries[i].wm_inst; 365 table->WatermarkRow[WM_DCFCLK][num_valid_sets].WmType = bw_params->wm_table.entries[i].wm_type; 366 /* We will not select WM based on fclk, so leave it as unconstrained */ 367 table->WatermarkRow[WM_DCFCLK][num_valid_sets].MinClock = 0; 368 table->WatermarkRow[WM_DCFCLK][num_valid_sets].MaxClock = 0xFFFF; 369 370 if (table->WatermarkRow[WM_DCFCLK][num_valid_sets].WmType == WM_TYPE_PSTATE_CHG) { 371 if (i == 0) 372 table->WatermarkRow[WM_DCFCLK][num_valid_sets].MinMclk = 0; 373 else { 374 /* add 1 to make it non-overlapping with next lvl */ 375 table->WatermarkRow[WM_DCFCLK][num_valid_sets].MinMclk = 376 bw_params->clk_table.entries[i - 1].dcfclk_mhz + 1; 377 } 378 table->WatermarkRow[WM_DCFCLK][num_valid_sets].MaxMclk = 379 bw_params->clk_table.entries[i].dcfclk_mhz; 380 381 } else { 382 /* unconstrained for memory retraining */ 383 table->WatermarkRow[WM_DCFCLK][num_valid_sets].MinClock = 0; 384 table->WatermarkRow[WM_DCFCLK][num_valid_sets].MaxClock = 0xFFFF; 385 386 /* Modify previous watermark range to cover up to max */ 387 table->WatermarkRow[WM_DCFCLK][num_valid_sets - 1].MaxClock = 0xFFFF; 388 } 389 num_valid_sets++; 390 } 391 392 ASSERT(num_valid_sets != 0); /* Must have at least one set of valid watermarks */ 393 394 /* modify the min and max to make sure we cover the whole range*/ 395 table->WatermarkRow[WM_DCFCLK][0].MinMclk = 0; 396 table->WatermarkRow[WM_DCFCLK][0].MinClock = 0; 397 table->WatermarkRow[WM_DCFCLK][num_valid_sets - 1].MaxMclk = 0xFFFF; 398 table->WatermarkRow[WM_DCFCLK][num_valid_sets - 1].MaxClock = 0xFFFF; 399 400 /* This is for writeback only, does not matter currently as no writeback support*/ 401 table->WatermarkRow[WM_SOCCLK][0].WmSetting = WM_A; 402 table->WatermarkRow[WM_SOCCLK][0].MinClock = 0; 403 table->WatermarkRow[WM_SOCCLK][0].MaxClock = 0xFFFF; 404 table->WatermarkRow[WM_SOCCLK][0].MinMclk = 0; 405 table->WatermarkRow[WM_SOCCLK][0].MaxMclk = 0xFFFF; 406 } 407 408 static void dcn316_notify_wm_ranges(struct clk_mgr *clk_mgr_base) 409 { 410 struct clk_mgr_internal *clk_mgr = TO_CLK_MGR_INTERNAL(clk_mgr_base); 411 struct clk_mgr_dcn316 *clk_mgr_dcn316 = TO_CLK_MGR_DCN316(clk_mgr); 412 struct dcn316_watermarks *table = clk_mgr_dcn316->smu_wm_set.wm_set; 413 414 if (!clk_mgr->smu_ver) 415 return; 416 417 if (!table || clk_mgr_dcn316->smu_wm_set.mc_address.quad_part == 0) 418 return; 419 420 memset(table, 0, sizeof(*table)); 421 422 dcn316_build_watermark_ranges(clk_mgr_base->bw_params, table); 423 424 dcn316_smu_set_dram_addr_high(clk_mgr, 425 clk_mgr_dcn316->smu_wm_set.mc_address.high_part); 426 dcn316_smu_set_dram_addr_low(clk_mgr, 427 clk_mgr_dcn316->smu_wm_set.mc_address.low_part); 428 dcn316_smu_transfer_wm_table_dram_2_smu(clk_mgr); 429 } 430 431 static void dcn316_get_dpm_table_from_smu(struct clk_mgr_internal *clk_mgr, 432 struct dcn316_smu_dpm_clks *smu_dpm_clks) 433 { 434 DpmClocks_316_t *table = smu_dpm_clks->dpm_clks; 435 436 if (!clk_mgr->smu_ver) 437 return; 438 439 if (!table || smu_dpm_clks->mc_address.quad_part == 0) 440 return; 441 442 memset(table, 0, sizeof(*table)); 443 444 dcn316_smu_set_dram_addr_high(clk_mgr, 445 smu_dpm_clks->mc_address.high_part); 446 dcn316_smu_set_dram_addr_low(clk_mgr, 447 smu_dpm_clks->mc_address.low_part); 448 dcn316_smu_transfer_dpm_table_smu_2_dram(clk_mgr); 449 } 450 451 static uint32_t find_max_clk_value(const uint32_t clocks[], uint32_t num_clocks) 452 { 453 uint32_t max = 0; 454 int i; 455 456 for (i = 0; i < num_clocks; ++i) { 457 if (clocks[i] > max) 458 max = clocks[i]; 459 } 460 461 return max; 462 } 463 464 static unsigned int find_clk_for_voltage( 465 const DpmClocks_316_t *clock_table, 466 const uint32_t clocks[], 467 unsigned int voltage) 468 { 469 int i; 470 int max_voltage = 0; 471 int clock = 0; 472 473 for (i = 0; i < NUM_SOC_VOLTAGE_LEVELS; i++) { 474 if (clock_table->SocVoltage[i] == voltage) { 475 return clocks[i]; 476 } else if (clock_table->SocVoltage[i] >= max_voltage && 477 clock_table->SocVoltage[i] < voltage) { 478 max_voltage = clock_table->SocVoltage[i]; 479 clock = clocks[i]; 480 } 481 } 482 483 ASSERT(clock); 484 return clock; 485 } 486 487 static void dcn316_clk_mgr_helper_populate_bw_params( 488 struct clk_mgr_internal *clk_mgr, 489 struct integrated_info *bios_info, 490 const DpmClocks_316_t *clock_table) 491 { 492 int i, j; 493 struct clk_bw_params *bw_params = clk_mgr->base.bw_params; 494 uint32_t max_dispclk = 0, max_dppclk = 0; 495 496 j = -1; 497 498 ASSERT(NUM_DF_PSTATE_LEVELS <= MAX_NUM_DPM_LVL); 499 500 /* Find lowest DPM, FCLK is filled in reverse order*/ 501 502 for (i = NUM_DF_PSTATE_LEVELS - 1; i >= 0; i--) { 503 if (clock_table->DfPstateTable[i].FClk != 0) { 504 j = i; 505 break; 506 } 507 } 508 509 if (j == -1) { 510 /* clock table is all 0s, just use our own hardcode */ 511 ASSERT(0); 512 return; 513 } 514 515 bw_params->clk_table.num_entries = j + 1; 516 517 /* dispclk and dppclk can be max at any voltage, same number of levels for both */ 518 if (clock_table->NumDispClkLevelsEnabled <= NUM_DISPCLK_DPM_LEVELS && 519 clock_table->NumDispClkLevelsEnabled <= NUM_DPPCLK_DPM_LEVELS) { 520 max_dispclk = find_max_clk_value(clock_table->DispClocks, clock_table->NumDispClkLevelsEnabled); 521 max_dppclk = find_max_clk_value(clock_table->DppClocks, clock_table->NumDispClkLevelsEnabled); 522 } else { 523 ASSERT(0); 524 } 525 526 for (i = 0; i < bw_params->clk_table.num_entries; i++, j--) { 527 int temp; 528 529 bw_params->clk_table.entries[i].fclk_mhz = clock_table->DfPstateTable[j].FClk; 530 bw_params->clk_table.entries[i].memclk_mhz = clock_table->DfPstateTable[j].MemClk; 531 bw_params->clk_table.entries[i].voltage = clock_table->DfPstateTable[j].Voltage; 532 switch (clock_table->DfPstateTable[j].WckRatio) { 533 case WCK_RATIO_1_2: 534 bw_params->clk_table.entries[i].wck_ratio = 2; 535 break; 536 case WCK_RATIO_1_4: 537 bw_params->clk_table.entries[i].wck_ratio = 4; 538 break; 539 default: 540 bw_params->clk_table.entries[i].wck_ratio = 1; 541 } 542 temp = find_clk_for_voltage(clock_table, clock_table->DcfClocks, clock_table->DfPstateTable[j].Voltage); 543 if (temp) 544 bw_params->clk_table.entries[i].dcfclk_mhz = temp; 545 temp = find_clk_for_voltage(clock_table, clock_table->SocClocks, clock_table->DfPstateTable[j].Voltage); 546 if (temp) 547 bw_params->clk_table.entries[i].socclk_mhz = temp; 548 bw_params->clk_table.entries[i].dispclk_mhz = max_dispclk; 549 bw_params->clk_table.entries[i].dppclk_mhz = max_dppclk; 550 } 551 552 bw_params->vram_type = bios_info->memory_type; 553 bw_params->num_channels = bios_info->ma_channel_number; 554 555 for (i = 0; i < WM_SET_COUNT; i++) { 556 bw_params->wm_table.entries[i].wm_inst = i; 557 558 if (i >= bw_params->clk_table.num_entries) { 559 bw_params->wm_table.entries[i].valid = false; 560 continue; 561 } 562 563 bw_params->wm_table.entries[i].wm_type = WM_TYPE_PSTATE_CHG; 564 bw_params->wm_table.entries[i].valid = true; 565 } 566 } 567 568 569 570 static struct clk_mgr_funcs dcn316_funcs = { 571 .enable_pme_wa = dcn316_enable_pme_wa, 572 .get_dp_ref_clk_frequency = dce12_get_dp_ref_freq_khz, 573 .update_clocks = dcn316_update_clocks, 574 .init_clocks = dcn31_init_clocks, 575 .are_clock_states_equal = dcn31_are_clock_states_equal, 576 .notify_wm_ranges = dcn316_notify_wm_ranges 577 }; 578 extern struct clk_mgr_funcs dcn3_fpga_funcs; 579 580 static int get_vco_frequency_from_reg(struct clk_mgr_internal *clk_mgr) 581 { 582 /* get FbMult value */ 583 struct fixed31_32 pll_req; 584 unsigned int fbmult_frac_val = 0; 585 unsigned int fbmult_int_val = 0; 586 587 /* 588 * Register value of fbmult is in 8.16 format, we are converting to 31.32 589 * to leverage the fix point operations available in driver 590 */ 591 592 REG_GET(CLK1_CLK_PLL_REQ, FbMult_frac, &fbmult_frac_val); /* 16 bit fractional part*/ 593 REG_GET(CLK1_CLK_PLL_REQ, FbMult_int, &fbmult_int_val); /* 8 bit integer part */ 594 595 pll_req = dc_fixpt_from_int(fbmult_int_val); 596 597 /* 598 * since fractional part is only 16 bit in register definition but is 32 bit 599 * in our fix point definiton, need to shift left by 16 to obtain correct value 600 */ 601 pll_req.value |= fbmult_frac_val << 16; 602 603 /* multiply by REFCLK period */ 604 pll_req = dc_fixpt_mul_int(pll_req, clk_mgr->dfs_ref_freq_khz); 605 606 /* integer part is now VCO frequency in kHz */ 607 return dc_fixpt_floor(pll_req); 608 } 609 610 void dcn316_clk_mgr_construct( 611 struct dc_context *ctx, 612 struct clk_mgr_dcn316 *clk_mgr, 613 struct pp_smu_funcs *pp_smu, 614 struct dccg *dccg) 615 { 616 struct dcn316_smu_dpm_clks smu_dpm_clks = { 0 }; 617 618 clk_mgr->base.base.ctx = ctx; 619 clk_mgr->base.base.funcs = &dcn316_funcs; 620 621 clk_mgr->base.pp_smu = pp_smu; 622 623 clk_mgr->base.dccg = dccg; 624 clk_mgr->base.dfs_bypass_disp_clk = 0; 625 626 clk_mgr->base.dprefclk_ss_percentage = 0; 627 clk_mgr->base.dprefclk_ss_divider = 1000; 628 clk_mgr->base.ss_on_dprefclk = false; 629 clk_mgr->base.dfs_ref_freq_khz = 48000; 630 631 clk_mgr->smu_wm_set.wm_set = (struct dcn316_watermarks *)dm_helpers_allocate_gpu_mem( 632 clk_mgr->base.base.ctx, 633 DC_MEM_ALLOC_TYPE_FRAME_BUFFER, 634 sizeof(struct dcn316_watermarks), 635 &clk_mgr->smu_wm_set.mc_address.quad_part); 636 637 if (!clk_mgr->smu_wm_set.wm_set) { 638 clk_mgr->smu_wm_set.wm_set = &dummy_wms; 639 clk_mgr->smu_wm_set.mc_address.quad_part = 0; 640 } 641 ASSERT(clk_mgr->smu_wm_set.wm_set); 642 643 smu_dpm_clks.dpm_clks = (DpmClocks_316_t *)dm_helpers_allocate_gpu_mem( 644 clk_mgr->base.base.ctx, 645 DC_MEM_ALLOC_TYPE_FRAME_BUFFER, 646 sizeof(DpmClocks_316_t), 647 &smu_dpm_clks.mc_address.quad_part); 648 649 if (smu_dpm_clks.dpm_clks == NULL) { 650 smu_dpm_clks.dpm_clks = &dummy_clocks; 651 smu_dpm_clks.mc_address.quad_part = 0; 652 } 653 654 ASSERT(smu_dpm_clks.dpm_clks); 655 656 if (IS_FPGA_MAXIMUS_DC(ctx->dce_environment)) { 657 clk_mgr->base.base.funcs = &dcn3_fpga_funcs; 658 clk_mgr->base.base.dentist_vco_freq_khz = 2500000; 659 } else { 660 struct clk_log_info log_info = {0}; 661 662 clk_mgr->base.smu_ver = dcn316_smu_get_smu_version(&clk_mgr->base); 663 664 if (clk_mgr->base.smu_ver > 0) 665 clk_mgr->base.smu_present = true; 666 667 // Skip this for now as it did not work on DCN315, renable during bring up 668 clk_mgr->base.base.dentist_vco_freq_khz = get_vco_frequency_from_reg(&clk_mgr->base); 669 670 /* in case we don't get a value from the register, use default */ 671 if (clk_mgr->base.base.dentist_vco_freq_khz == 0) 672 clk_mgr->base.base.dentist_vco_freq_khz = 2500000; /* 2400MHz */ 673 674 675 if (ctx->dc_bios->integrated_info->memory_type == LpDdr5MemType) { 676 dcn316_bw_params.wm_table = lpddr5_wm_table; 677 } else { 678 dcn316_bw_params.wm_table = ddr4_wm_table; 679 } 680 /* Saved clocks configured at boot for debug purposes */ 681 dcn316_dump_clk_registers(&clk_mgr->base.base.boot_snapshot, &clk_mgr->base.base, &log_info); 682 683 } 684 685 clk_mgr->base.base.dprefclk_khz = 600000; 686 clk_mgr->base.base.dprefclk_khz = dcn316_smu_get_dpref_clk(&clk_mgr->base); 687 clk_mgr->base.dccg->ref_dtbclk_khz = clk_mgr->base.base.dprefclk_khz; 688 dce_clock_read_ss_info(&clk_mgr->base); 689 clk_mgr->base.dccg->ref_dtbclk_khz = 690 dce_adjust_dp_ref_freq_for_ss(&clk_mgr->base, clk_mgr->base.base.dprefclk_khz); 691 692 clk_mgr->base.base.bw_params = &dcn316_bw_params; 693 694 if (clk_mgr->base.base.ctx->dc->debug.pstate_enabled) { 695 dcn316_get_dpm_table_from_smu(&clk_mgr->base, &smu_dpm_clks); 696 697 if (ctx->dc_bios && ctx->dc_bios->integrated_info) { 698 dcn316_clk_mgr_helper_populate_bw_params( 699 &clk_mgr->base, 700 ctx->dc_bios->integrated_info, 701 smu_dpm_clks.dpm_clks); 702 } 703 } 704 705 if (smu_dpm_clks.dpm_clks && smu_dpm_clks.mc_address.quad_part != 0) 706 dm_helpers_free_gpu_mem(clk_mgr->base.base.ctx, DC_MEM_ALLOC_TYPE_FRAME_BUFFER, 707 smu_dpm_clks.dpm_clks); 708 } 709 710 void dcn316_clk_mgr_destroy(struct clk_mgr_internal *clk_mgr_int) 711 { 712 struct clk_mgr_dcn316 *clk_mgr = TO_CLK_MGR_DCN316(clk_mgr_int); 713 714 if (clk_mgr->smu_wm_set.wm_set && clk_mgr->smu_wm_set.mc_address.quad_part != 0) 715 dm_helpers_free_gpu_mem(clk_mgr_int->base.ctx, DC_MEM_ALLOC_TYPE_FRAME_BUFFER, 716 clk_mgr->smu_wm_set.wm_set); 717 } 718