1 /* SPDX-License-Identifier: MIT */ 2 /* 3 * Copyright 2022 Advanced Micro Devices, Inc. 4 * 5 * Permission is hereby granted, free of charge, to any person obtaining a 6 * copy of this software and associated documentation files (the "Software"), 7 * to deal in the Software without restriction, including without limitation 8 * the rights to use, copy, modify, merge, publish, distribute, sublicense, 9 * and/or sell copies of the Software, and to permit persons to whom the 10 * Software is furnished to do so, subject to the following conditions: 11 * 12 * The above copyright notice and this permission notice shall be included in 13 * all copies or substantial portions of the Software. 14 * 15 * THE SOFTWARE IS PROVIDED "AS IS", WITHOUT WARRANTY OF ANY KIND, EXPRESS OR 16 * IMPLIED, INCLUDING BUT NOT LIMITED TO THE WARRANTIES OF MERCHANTABILITY, 17 * FITNESS FOR A PARTICULAR PURPOSE AND NONINFRINGEMENT. IN NO EVENT SHALL 18 * THE COPYRIGHT HOLDER(S) OR AUTHOR(S) BE LIABLE FOR ANY CLAIM, DAMAGES OR 19 * OTHER LIABILITY, WHETHER IN AN ACTION OF CONTRACT, TORT OR OTHERWISE, 20 * ARISING FROM, OUT OF OR IN CONNECTION WITH THE SOFTWARE OR THE USE OR 21 * OTHER DEALINGS IN THE SOFTWARE. 22 * 23 * Authors: AMD 24 * 25 */ 26 27 #ifndef DAL_DC_314_SMU_H_ 28 #define DAL_DC_314_SMU_H_ 29 30 #include "smu13_driver_if_v13_0_4.h" 31 32 typedef enum { 33 WCK_RATIO_1_1 = 0, // DDR5, Wck:ck is always 1:1; 34 WCK_RATIO_1_2, 35 WCK_RATIO_1_4, 36 WCK_RATIO_MAX 37 } WCK_RATIO_e; 38 39 struct dcn314_watermarks { 40 // Watermarks 41 WatermarkRowGeneric_t WatermarkRow[WM_COUNT][NUM_WM_RANGES]; 42 uint32_t MmHubPadding[7]; // SMU internal use 43 }; 44 45 struct dcn314_smu_dpm_clks { 46 DpmClocks_t *dpm_clks; 47 union large_integer mc_address; 48 }; 49 50 struct display_idle_optimization { 51 unsigned int df_request_disabled : 1; 52 unsigned int phy_ref_clk_off : 1; 53 unsigned int s0i2_rdy : 1; 54 unsigned int reserved : 29; 55 }; 56 57 union display_idle_optimization_u { 58 struct display_idle_optimization idle_info; 59 uint32_t data; 60 }; 61 62 int dcn314_smu_get_smu_version(struct clk_mgr_internal *clk_mgr); 63 int dcn314_smu_set_dispclk(struct clk_mgr_internal *clk_mgr, int requested_dispclk_khz); 64 int dcn314_smu_set_dprefclk(struct clk_mgr_internal *clk_mgr); 65 int dcn314_smu_set_hard_min_dcfclk(struct clk_mgr_internal *clk_mgr, int requested_dcfclk_khz); 66 int dcn314_smu_set_min_deep_sleep_dcfclk(struct clk_mgr_internal *clk_mgr, int requested_min_ds_dcfclk_khz); 67 int dcn314_smu_set_dppclk(struct clk_mgr_internal *clk_mgr, int requested_dpp_khz); 68 void dcn314_smu_set_display_idle_optimization(struct clk_mgr_internal *clk_mgr, uint32_t idle_info); 69 void dcn314_smu_enable_phy_refclk_pwrdwn(struct clk_mgr_internal *clk_mgr, bool enable); 70 void dcn314_smu_enable_pme_wa(struct clk_mgr_internal *clk_mgr); 71 void dcn314_smu_set_dram_addr_high(struct clk_mgr_internal *clk_mgr, uint32_t addr_high); 72 void dcn314_smu_set_dram_addr_low(struct clk_mgr_internal *clk_mgr, uint32_t addr_low); 73 void dcn314_smu_transfer_dpm_table_smu_2_dram(struct clk_mgr_internal *clk_mgr); 74 void dcn314_smu_transfer_wm_table_dram_2_smu(struct clk_mgr_internal *clk_mgr); 75 76 void dcn314_smu_set_zstate_support(struct clk_mgr_internal *clk_mgr, enum dcn_zstate_support_state support); 77 void dcn314_smu_set_dtbclk(struct clk_mgr_internal *clk_mgr, bool enable); 78 79 #endif /* DAL_DC_314_SMU_H_ */ 80