1*d5c6909eSRoman Li /* SPDX-License-Identifier: MIT */ 2*d5c6909eSRoman Li /* 3*d5c6909eSRoman Li * Copyright 2022 Advanced Micro Devices, Inc. 4*d5c6909eSRoman Li * 5*d5c6909eSRoman Li * Permission is hereby granted, free of charge, to any person obtaining a 6*d5c6909eSRoman Li * copy of this software and associated documentation files (the "Software"), 7*d5c6909eSRoman Li * to deal in the Software without restriction, including without limitation 8*d5c6909eSRoman Li * the rights to use, copy, modify, merge, publish, distribute, sublicense, 9*d5c6909eSRoman Li * and/or sell copies of the Software, and to permit persons to whom the 10*d5c6909eSRoman Li * Software is furnished to do so, subject to the following conditions: 11*d5c6909eSRoman Li * 12*d5c6909eSRoman Li * The above copyright notice and this permission notice shall be included in 13*d5c6909eSRoman Li * all copies or substantial portions of the Software. 14*d5c6909eSRoman Li * 15*d5c6909eSRoman Li * THE SOFTWARE IS PROVIDED "AS IS", WITHOUT WARRANTY OF ANY KIND, EXPRESS OR 16*d5c6909eSRoman Li * IMPLIED, INCLUDING BUT NOT LIMITED TO THE WARRANTIES OF MERCHANTABILITY, 17*d5c6909eSRoman Li * FITNESS FOR A PARTICULAR PURPOSE AND NONINFRINGEMENT. IN NO EVENT SHALL 18*d5c6909eSRoman Li * THE COPYRIGHT HOLDER(S) OR AUTHOR(S) BE LIABLE FOR ANY CLAIM, DAMAGES OR 19*d5c6909eSRoman Li * OTHER LIABILITY, WHETHER IN AN ACTION OF CONTRACT, TORT OR OTHERWISE, 20*d5c6909eSRoman Li * ARISING FROM, OUT OF OR IN CONNECTION WITH THE SOFTWARE OR THE USE OR 21*d5c6909eSRoman Li * OTHER DEALINGS IN THE SOFTWARE. 22*d5c6909eSRoman Li * 23*d5c6909eSRoman Li * Authors: AMD 24*d5c6909eSRoman Li * 25*d5c6909eSRoman Li */ 26*d5c6909eSRoman Li 27*d5c6909eSRoman Li #ifndef __DCN314_CLK_MGR_H__ 28*d5c6909eSRoman Li #define __DCN314_CLK_MGR_H__ 29*d5c6909eSRoman Li #include "clk_mgr_internal.h" 30*d5c6909eSRoman Li 31*d5c6909eSRoman Li struct dcn314_watermarks; 32*d5c6909eSRoman Li 33*d5c6909eSRoman Li struct dcn314_smu_watermark_set { 34*d5c6909eSRoman Li struct dcn314_watermarks *wm_set; 35*d5c6909eSRoman Li union large_integer mc_address; 36*d5c6909eSRoman Li }; 37*d5c6909eSRoman Li 38*d5c6909eSRoman Li struct clk_mgr_dcn314 { 39*d5c6909eSRoman Li struct clk_mgr_internal base; 40*d5c6909eSRoman Li struct dcn314_smu_watermark_set smu_wm_set; 41*d5c6909eSRoman Li }; 42*d5c6909eSRoman Li 43*d5c6909eSRoman Li bool dcn314_are_clock_states_equal(struct dc_clocks *a, 44*d5c6909eSRoman Li struct dc_clocks *b); 45*d5c6909eSRoman Li void dcn314_init_clocks(struct clk_mgr *clk_mgr); 46*d5c6909eSRoman Li void dcn314_update_clocks(struct clk_mgr *clk_mgr_base, 47*d5c6909eSRoman Li struct dc_state *context, 48*d5c6909eSRoman Li bool safe_to_lower); 49*d5c6909eSRoman Li 50*d5c6909eSRoman Li void dcn314_clk_mgr_construct(struct dc_context *ctx, 51*d5c6909eSRoman Li struct clk_mgr_dcn314 *clk_mgr, 52*d5c6909eSRoman Li struct pp_smu_funcs *pp_smu, 53*d5c6909eSRoman Li struct dccg *dccg); 54*d5c6909eSRoman Li 55*d5c6909eSRoman Li void dcn314_clk_mgr_destroy(struct clk_mgr_internal *clk_mgr_int); 56*d5c6909eSRoman Li 57*d5c6909eSRoman Li #endif //__DCN314_CLK_MGR_H__ 58