1 // SPDX-License-Identifier: MIT 2 /* 3 * Copyright 2022 Advanced Micro Devices, Inc. 4 * 5 * Permission is hereby granted, free of charge, to any person obtaining a 6 * copy of this software and associated documentation files (the "Software"), 7 * to deal in the Software without restriction, including without limitation 8 * the rights to use, copy, modify, merge, publish, distribute, sublicense, 9 * and/or sell copies of the Software, and to permit persons to whom the 10 * Software is furnished to do so, subject to the following conditions: 11 * 12 * The above copyright notice and this permission notice shall be included in 13 * all copies or substantial portions of the Software. 14 * 15 * THE SOFTWARE IS PROVIDED "AS IS", WITHOUT WARRANTY OF ANY KIND, EXPRESS OR 16 * IMPLIED, INCLUDING BUT NOT LIMITED TO THE WARRANTIES OF MERCHANTABILITY, 17 * FITNESS FOR A PARTICULAR PURPOSE AND NONINFRINGEMENT. IN NO EVENT SHALL 18 * THE COPYRIGHT HOLDER(S) OR AUTHOR(S) BE LIABLE FOR ANY CLAIM, DAMAGES OR 19 * OTHER LIABILITY, WHETHER IN AN ACTION OF CONTRACT, TORT OR OTHERWISE, 20 * ARISING FROM, OUT OF OR IN CONNECTION WITH THE SOFTWARE OR THE USE OR 21 * OTHER DEALINGS IN THE SOFTWARE. 22 * 23 * Authors: AMD 24 * 25 */ 26 27 28 29 #include "dcn314_clk_mgr.h" 30 31 #include "dccg.h" 32 #include "clk_mgr_internal.h" 33 34 // For dce12_get_dp_ref_freq_khz 35 #include "dce100/dce_clk_mgr.h" 36 37 // For dcn20_update_clocks_update_dpp_dto 38 #include "dcn20/dcn20_clk_mgr.h" 39 40 41 42 #include "reg_helper.h" 43 #include "core_types.h" 44 #include "dm_helpers.h" 45 46 /* TODO: remove this include once we ported over remaining clk mgr functions*/ 47 #include "dcn30/dcn30_clk_mgr.h" 48 #include "dcn31/dcn31_clk_mgr.h" 49 50 #include "dc_dmub_srv.h" 51 #include "dc_link_dp.h" 52 #include "dcn314_smu.h" 53 54 #define MAX_INSTANCE 7 55 #define MAX_SEGMENT 8 56 57 struct IP_BASE_INSTANCE { 58 unsigned int segment[MAX_SEGMENT]; 59 }; 60 61 struct IP_BASE { 62 struct IP_BASE_INSTANCE instance[MAX_INSTANCE]; 63 }; 64 65 static const struct IP_BASE CLK_BASE = { { { { 0x00016C00, 0x02401800, 0, 0, 0, 0, 0, 0 } }, 66 { { 0x00016E00, 0x02401C00, 0, 0, 0, 0, 0, 0 } }, 67 { { 0x00017000, 0x02402000, 0, 0, 0, 0, 0, 0 } }, 68 { { 0x00017200, 0x02402400, 0, 0, 0, 0, 0, 0 } }, 69 { { 0x0001B000, 0x0242D800, 0, 0, 0, 0, 0, 0 } }, 70 { { 0x0001B200, 0x0242DC00, 0, 0, 0, 0, 0, 0 } }, 71 { { 0x0001B400, 0x0242E000, 0, 0, 0, 0, 0, 0 } } } }; 72 73 #define regCLK1_CLK_PLL_REQ 0x0237 74 #define regCLK1_CLK_PLL_REQ_BASE_IDX 0 75 76 #define CLK1_CLK_PLL_REQ__FbMult_int__SHIFT 0x0 77 #define CLK1_CLK_PLL_REQ__PllSpineDiv__SHIFT 0xc 78 #define CLK1_CLK_PLL_REQ__FbMult_frac__SHIFT 0x10 79 #define CLK1_CLK_PLL_REQ__FbMult_int_MASK 0x000001FFL 80 #define CLK1_CLK_PLL_REQ__PllSpineDiv_MASK 0x0000F000L 81 #define CLK1_CLK_PLL_REQ__FbMult_frac_MASK 0xFFFF0000L 82 83 #define REG(reg_name) \ 84 (CLK_BASE.instance[0].segment[reg ## reg_name ## _BASE_IDX] + reg ## reg_name) 85 86 #define TO_CLK_MGR_DCN314(clk_mgr)\ 87 container_of(clk_mgr, struct clk_mgr_dcn314, base) 88 89 static int dcn314_get_active_display_cnt_wa( 90 struct dc *dc, 91 struct dc_state *context) 92 { 93 int i, display_count; 94 bool tmds_present = false; 95 96 display_count = 0; 97 for (i = 0; i < context->stream_count; i++) { 98 const struct dc_stream_state *stream = context->streams[i]; 99 100 if (stream->signal == SIGNAL_TYPE_HDMI_TYPE_A || 101 stream->signal == SIGNAL_TYPE_DVI_SINGLE_LINK || 102 stream->signal == SIGNAL_TYPE_DVI_DUAL_LINK) 103 tmds_present = true; 104 } 105 106 for (i = 0; i < dc->link_count; i++) { 107 const struct dc_link *link = dc->links[i]; 108 109 /* abusing the fact that the dig and phy are coupled to see if the phy is enabled */ 110 if (link->link_enc && link->link_enc->funcs->is_dig_enabled && 111 link->link_enc->funcs->is_dig_enabled(link->link_enc)) 112 display_count++; 113 } 114 115 /* WA for hang on HDMI after display off back on*/ 116 if (display_count == 0 && tmds_present) 117 display_count = 1; 118 119 return display_count; 120 } 121 122 static void dcn314_disable_otg_wa(struct clk_mgr *clk_mgr_base, bool disable) 123 { 124 struct dc *dc = clk_mgr_base->ctx->dc; 125 int i; 126 127 for (i = 0; i < dc->res_pool->pipe_count; ++i) { 128 struct pipe_ctx *pipe = &dc->current_state->res_ctx.pipe_ctx[i]; 129 130 if (pipe->top_pipe || pipe->prev_odm_pipe) 131 continue; 132 if (pipe->stream && (pipe->stream->dpms_off || pipe->plane_state == NULL || 133 dc_is_virtual_signal(pipe->stream->signal))) { 134 if (disable) 135 pipe->stream_res.tg->funcs->immediate_disable_crtc(pipe->stream_res.tg); 136 else 137 pipe->stream_res.tg->funcs->enable_crtc(pipe->stream_res.tg); 138 } 139 } 140 } 141 142 void dcn314_update_clocks(struct clk_mgr *clk_mgr_base, 143 struct dc_state *context, 144 bool safe_to_lower) 145 { 146 union dmub_rb_cmd cmd; 147 struct clk_mgr_internal *clk_mgr = TO_CLK_MGR_INTERNAL(clk_mgr_base); 148 struct dc_clocks *new_clocks = &context->bw_ctx.bw.dcn.clk; 149 struct dc *dc = clk_mgr_base->ctx->dc; 150 int display_count; 151 bool update_dppclk = false; 152 bool update_dispclk = false; 153 bool dpp_clock_lowered = false; 154 155 if (dc->work_arounds.skip_clock_update) 156 return; 157 158 /* 159 * if it is safe to lower, but we are already in the lower state, we don't have to do anything 160 * also if safe to lower is false, we just go in the higher state 161 */ 162 if (safe_to_lower) { 163 if (new_clocks->zstate_support != DCN_ZSTATE_SUPPORT_DISALLOW && 164 new_clocks->zstate_support != clk_mgr_base->clks.zstate_support) { 165 dcn314_smu_set_zstate_support(clk_mgr, new_clocks->zstate_support); 166 dm_helpers_enable_periodic_detection(clk_mgr_base->ctx, true); 167 clk_mgr_base->clks.zstate_support = new_clocks->zstate_support; 168 } 169 170 if (clk_mgr_base->clks.dtbclk_en && !new_clocks->dtbclk_en) { 171 dcn314_smu_set_dtbclk(clk_mgr, false); 172 clk_mgr_base->clks.dtbclk_en = new_clocks->dtbclk_en; 173 } 174 /* check that we're not already in lower */ 175 if (clk_mgr_base->clks.pwr_state != DCN_PWR_STATE_LOW_POWER) { 176 display_count = dcn314_get_active_display_cnt_wa(dc, context); 177 /* if we can go lower, go lower */ 178 if (display_count == 0) { 179 union display_idle_optimization_u idle_info = { 0 }; 180 idle_info.idle_info.df_request_disabled = 1; 181 idle_info.idle_info.phy_ref_clk_off = 1; 182 idle_info.idle_info.s0i2_rdy = 1; 183 dcn314_smu_set_display_idle_optimization(clk_mgr, idle_info.data); 184 /* update power state */ 185 clk_mgr_base->clks.pwr_state = DCN_PWR_STATE_LOW_POWER; 186 } 187 } 188 } else { 189 if (new_clocks->zstate_support == DCN_ZSTATE_SUPPORT_DISALLOW && 190 new_clocks->zstate_support != clk_mgr_base->clks.zstate_support) { 191 dcn314_smu_set_zstate_support(clk_mgr, DCN_ZSTATE_SUPPORT_DISALLOW); 192 dm_helpers_enable_periodic_detection(clk_mgr_base->ctx, false); 193 clk_mgr_base->clks.zstate_support = new_clocks->zstate_support; 194 } 195 196 if (!clk_mgr_base->clks.dtbclk_en && new_clocks->dtbclk_en) { 197 dcn314_smu_set_dtbclk(clk_mgr, true); 198 clk_mgr_base->clks.dtbclk_en = new_clocks->dtbclk_en; 199 } 200 201 /* check that we're not already in D0 */ 202 if (clk_mgr_base->clks.pwr_state != DCN_PWR_STATE_MISSION_MODE) { 203 union display_idle_optimization_u idle_info = { 0 }; 204 205 dcn314_smu_set_display_idle_optimization(clk_mgr, idle_info.data); 206 /* update power state */ 207 clk_mgr_base->clks.pwr_state = DCN_PWR_STATE_MISSION_MODE; 208 } 209 } 210 211 if (should_set_clock(safe_to_lower, new_clocks->dcfclk_khz, clk_mgr_base->clks.dcfclk_khz)) { 212 clk_mgr_base->clks.dcfclk_khz = new_clocks->dcfclk_khz; 213 dcn314_smu_set_hard_min_dcfclk(clk_mgr, clk_mgr_base->clks.dcfclk_khz); 214 } 215 216 if (should_set_clock(safe_to_lower, 217 new_clocks->dcfclk_deep_sleep_khz, clk_mgr_base->clks.dcfclk_deep_sleep_khz)) { 218 clk_mgr_base->clks.dcfclk_deep_sleep_khz = new_clocks->dcfclk_deep_sleep_khz; 219 dcn314_smu_set_min_deep_sleep_dcfclk(clk_mgr, clk_mgr_base->clks.dcfclk_deep_sleep_khz); 220 } 221 222 // workaround: Limit dppclk to 100Mhz to avoid lower eDP panel switch to plus 4K monitor underflow. 223 if (!IS_DIAG_DC(dc->ctx->dce_environment)) { 224 if (new_clocks->dppclk_khz < 100000) 225 new_clocks->dppclk_khz = 100000; 226 } 227 228 if (should_set_clock(safe_to_lower, new_clocks->dppclk_khz, clk_mgr->base.clks.dppclk_khz)) { 229 if (clk_mgr->base.clks.dppclk_khz > new_clocks->dppclk_khz) 230 dpp_clock_lowered = true; 231 clk_mgr_base->clks.dppclk_khz = new_clocks->dppclk_khz; 232 update_dppclk = true; 233 } 234 235 if (should_set_clock(safe_to_lower, new_clocks->dispclk_khz, clk_mgr_base->clks.dispclk_khz)) { 236 dcn314_disable_otg_wa(clk_mgr_base, true); 237 238 clk_mgr_base->clks.dispclk_khz = new_clocks->dispclk_khz; 239 dcn314_smu_set_dispclk(clk_mgr, clk_mgr_base->clks.dispclk_khz); 240 dcn314_disable_otg_wa(clk_mgr_base, false); 241 242 update_dispclk = true; 243 } 244 245 if (dpp_clock_lowered) { 246 // increase per DPP DTO before lowering global dppclk 247 dcn20_update_clocks_update_dpp_dto(clk_mgr, context, safe_to_lower); 248 dcn314_smu_set_dppclk(clk_mgr, clk_mgr_base->clks.dppclk_khz); 249 } else { 250 // increase global DPPCLK before lowering per DPP DTO 251 if (update_dppclk || update_dispclk) 252 dcn314_smu_set_dppclk(clk_mgr, clk_mgr_base->clks.dppclk_khz); 253 // always update dtos unless clock is lowered and not safe to lower 254 if (new_clocks->dppclk_khz >= dc->current_state->bw_ctx.bw.dcn.clk.dppclk_khz) 255 dcn20_update_clocks_update_dpp_dto(clk_mgr, context, safe_to_lower); 256 } 257 258 // notify DMCUB of latest clocks 259 memset(&cmd, 0, sizeof(cmd)); 260 cmd.notify_clocks.header.type = DMUB_CMD__CLK_MGR; 261 cmd.notify_clocks.header.sub_type = DMUB_CMD__CLK_MGR_NOTIFY_CLOCKS; 262 cmd.notify_clocks.clocks.dcfclk_khz = clk_mgr_base->clks.dcfclk_khz; 263 cmd.notify_clocks.clocks.dcfclk_deep_sleep_khz = 264 clk_mgr_base->clks.dcfclk_deep_sleep_khz; 265 cmd.notify_clocks.clocks.dispclk_khz = clk_mgr_base->clks.dispclk_khz; 266 cmd.notify_clocks.clocks.dppclk_khz = clk_mgr_base->clks.dppclk_khz; 267 268 dc_dmub_srv_cmd_queue(dc->ctx->dmub_srv, &cmd); 269 dc_dmub_srv_cmd_execute(dc->ctx->dmub_srv); 270 dc_dmub_srv_wait_idle(dc->ctx->dmub_srv); 271 } 272 273 static int get_vco_frequency_from_reg(struct clk_mgr_internal *clk_mgr) 274 { 275 /* get FbMult value */ 276 struct fixed31_32 pll_req; 277 unsigned int fbmult_frac_val = 0; 278 unsigned int fbmult_int_val = 0; 279 280 /* 281 * Register value of fbmult is in 8.16 format, we are converting to 314.32 282 * to leverage the fix point operations available in driver 283 */ 284 285 REG_GET(CLK1_CLK_PLL_REQ, FbMult_frac, &fbmult_frac_val); /* 16 bit fractional part*/ 286 REG_GET(CLK1_CLK_PLL_REQ, FbMult_int, &fbmult_int_val); /* 8 bit integer part */ 287 288 pll_req = dc_fixpt_from_int(fbmult_int_val); 289 290 /* 291 * since fractional part is only 16 bit in register definition but is 32 bit 292 * in our fix point definiton, need to shift left by 16 to obtain correct value 293 */ 294 pll_req.value |= fbmult_frac_val << 16; 295 296 /* multiply by REFCLK period */ 297 pll_req = dc_fixpt_mul_int(pll_req, clk_mgr->dfs_ref_freq_khz); 298 299 /* integer part is now VCO frequency in kHz */ 300 return dc_fixpt_floor(pll_req); 301 } 302 303 static void dcn314_enable_pme_wa(struct clk_mgr *clk_mgr_base) 304 { 305 struct clk_mgr_internal *clk_mgr = TO_CLK_MGR_INTERNAL(clk_mgr_base); 306 307 dcn314_smu_enable_pme_wa(clk_mgr); 308 } 309 310 bool dcn314_are_clock_states_equal(struct dc_clocks *a, 311 struct dc_clocks *b) 312 { 313 if (a->dispclk_khz != b->dispclk_khz) 314 return false; 315 else if (a->dppclk_khz != b->dppclk_khz) 316 return false; 317 else if (a->dcfclk_khz != b->dcfclk_khz) 318 return false; 319 else if (a->dcfclk_deep_sleep_khz != b->dcfclk_deep_sleep_khz) 320 return false; 321 else if (a->zstate_support != b->zstate_support) 322 return false; 323 else if (a->dtbclk_en != b->dtbclk_en) 324 return false; 325 326 return true; 327 } 328 329 static void dcn314_dump_clk_registers(struct clk_state_registers_and_bypass *regs_and_bypass, 330 struct clk_mgr *clk_mgr_base, struct clk_log_info *log_info) 331 { 332 return; 333 } 334 335 static struct clk_bw_params dcn314_bw_params = { 336 .vram_type = Ddr4MemType, 337 .num_channels = 1, 338 .clk_table = { 339 .num_entries = 4, 340 }, 341 342 }; 343 344 static struct wm_table ddr5_wm_table = { 345 .entries = { 346 { 347 .wm_inst = WM_A, 348 .wm_type = WM_TYPE_PSTATE_CHG, 349 .pstate_latency_us = 11.72, 350 .sr_exit_time_us = 9, 351 .sr_enter_plus_exit_time_us = 11, 352 .valid = true, 353 }, 354 { 355 .wm_inst = WM_B, 356 .wm_type = WM_TYPE_PSTATE_CHG, 357 .pstate_latency_us = 11.72, 358 .sr_exit_time_us = 9, 359 .sr_enter_plus_exit_time_us = 11, 360 .valid = true, 361 }, 362 { 363 .wm_inst = WM_C, 364 .wm_type = WM_TYPE_PSTATE_CHG, 365 .pstate_latency_us = 11.72, 366 .sr_exit_time_us = 9, 367 .sr_enter_plus_exit_time_us = 11, 368 .valid = true, 369 }, 370 { 371 .wm_inst = WM_D, 372 .wm_type = WM_TYPE_PSTATE_CHG, 373 .pstate_latency_us = 11.72, 374 .sr_exit_time_us = 9, 375 .sr_enter_plus_exit_time_us = 11, 376 .valid = true, 377 }, 378 } 379 }; 380 381 static struct wm_table lpddr5_wm_table = { 382 .entries = { 383 { 384 .wm_inst = WM_A, 385 .wm_type = WM_TYPE_PSTATE_CHG, 386 .pstate_latency_us = 11.65333, 387 .sr_exit_time_us = 11.5, 388 .sr_enter_plus_exit_time_us = 14.5, 389 .valid = true, 390 }, 391 { 392 .wm_inst = WM_B, 393 .wm_type = WM_TYPE_PSTATE_CHG, 394 .pstate_latency_us = 11.65333, 395 .sr_exit_time_us = 11.5, 396 .sr_enter_plus_exit_time_us = 14.5, 397 .valid = true, 398 }, 399 { 400 .wm_inst = WM_C, 401 .wm_type = WM_TYPE_PSTATE_CHG, 402 .pstate_latency_us = 11.65333, 403 .sr_exit_time_us = 11.5, 404 .sr_enter_plus_exit_time_us = 14.5, 405 .valid = true, 406 }, 407 { 408 .wm_inst = WM_D, 409 .wm_type = WM_TYPE_PSTATE_CHG, 410 .pstate_latency_us = 11.65333, 411 .sr_exit_time_us = 11.5, 412 .sr_enter_plus_exit_time_us = 14.5, 413 .valid = true, 414 }, 415 } 416 }; 417 418 static DpmClocks314_t dummy_clocks; 419 420 static struct dcn314_watermarks dummy_wms = { 0 }; 421 422 static void dcn314_build_watermark_ranges(struct clk_bw_params *bw_params, struct dcn314_watermarks *table) 423 { 424 int i, num_valid_sets; 425 426 num_valid_sets = 0; 427 428 for (i = 0; i < WM_SET_COUNT; i++) { 429 /* skip empty entries, the smu array has no holes*/ 430 if (!bw_params->wm_table.entries[i].valid) 431 continue; 432 433 table->WatermarkRow[WM_DCFCLK][num_valid_sets].WmSetting = bw_params->wm_table.entries[i].wm_inst; 434 table->WatermarkRow[WM_DCFCLK][num_valid_sets].WmType = bw_params->wm_table.entries[i].wm_type; 435 /* We will not select WM based on fclk, so leave it as unconstrained */ 436 table->WatermarkRow[WM_DCFCLK][num_valid_sets].MinClock = 0; 437 table->WatermarkRow[WM_DCFCLK][num_valid_sets].MaxClock = 0xFFFF; 438 439 if (table->WatermarkRow[WM_DCFCLK][num_valid_sets].WmType == WM_TYPE_PSTATE_CHG) { 440 if (i == 0) 441 table->WatermarkRow[WM_DCFCLK][num_valid_sets].MinMclk = 0; 442 else { 443 /* add 1 to make it non-overlapping with next lvl */ 444 table->WatermarkRow[WM_DCFCLK][num_valid_sets].MinMclk = 445 bw_params->clk_table.entries[i - 1].dcfclk_mhz + 1; 446 } 447 table->WatermarkRow[WM_DCFCLK][num_valid_sets].MaxMclk = 448 bw_params->clk_table.entries[i].dcfclk_mhz; 449 450 } else { 451 /* unconstrained for memory retraining */ 452 table->WatermarkRow[WM_DCFCLK][num_valid_sets].MinClock = 0; 453 table->WatermarkRow[WM_DCFCLK][num_valid_sets].MaxClock = 0xFFFF; 454 455 /* Modify previous watermark range to cover up to max */ 456 table->WatermarkRow[WM_DCFCLK][num_valid_sets - 1].MaxClock = 0xFFFF; 457 } 458 num_valid_sets++; 459 } 460 461 ASSERT(num_valid_sets != 0); /* Must have at least one set of valid watermarks */ 462 463 /* modify the min and max to make sure we cover the whole range*/ 464 table->WatermarkRow[WM_DCFCLK][0].MinMclk = 0; 465 table->WatermarkRow[WM_DCFCLK][0].MinClock = 0; 466 table->WatermarkRow[WM_DCFCLK][num_valid_sets - 1].MaxMclk = 0xFFFF; 467 table->WatermarkRow[WM_DCFCLK][num_valid_sets - 1].MaxClock = 0xFFFF; 468 469 /* This is for writeback only, does not matter currently as no writeback support*/ 470 table->WatermarkRow[WM_SOCCLK][0].WmSetting = WM_A; 471 table->WatermarkRow[WM_SOCCLK][0].MinClock = 0; 472 table->WatermarkRow[WM_SOCCLK][0].MaxClock = 0xFFFF; 473 table->WatermarkRow[WM_SOCCLK][0].MinMclk = 0; 474 table->WatermarkRow[WM_SOCCLK][0].MaxMclk = 0xFFFF; 475 } 476 477 static void dcn314_notify_wm_ranges(struct clk_mgr *clk_mgr_base) 478 { 479 struct clk_mgr_internal *clk_mgr = TO_CLK_MGR_INTERNAL(clk_mgr_base); 480 struct clk_mgr_dcn314 *clk_mgr_dcn314 = TO_CLK_MGR_DCN314(clk_mgr); 481 struct dcn314_watermarks *table = clk_mgr_dcn314->smu_wm_set.wm_set; 482 483 if (!clk_mgr->smu_ver) 484 return; 485 486 if (!table || clk_mgr_dcn314->smu_wm_set.mc_address.quad_part == 0) 487 return; 488 489 memset(table, 0, sizeof(*table)); 490 491 dcn314_build_watermark_ranges(clk_mgr_base->bw_params, table); 492 493 dcn314_smu_set_dram_addr_high(clk_mgr, 494 clk_mgr_dcn314->smu_wm_set.mc_address.high_part); 495 dcn314_smu_set_dram_addr_low(clk_mgr, 496 clk_mgr_dcn314->smu_wm_set.mc_address.low_part); 497 dcn314_smu_transfer_wm_table_dram_2_smu(clk_mgr); 498 } 499 500 static void dcn314_get_dpm_table_from_smu(struct clk_mgr_internal *clk_mgr, 501 struct dcn314_smu_dpm_clks *smu_dpm_clks) 502 { 503 DpmClocks314_t *table = smu_dpm_clks->dpm_clks; 504 505 if (!clk_mgr->smu_ver) 506 return; 507 508 if (!table || smu_dpm_clks->mc_address.quad_part == 0) 509 return; 510 511 memset(table, 0, sizeof(*table)); 512 513 dcn314_smu_set_dram_addr_high(clk_mgr, 514 smu_dpm_clks->mc_address.high_part); 515 dcn314_smu_set_dram_addr_low(clk_mgr, 516 smu_dpm_clks->mc_address.low_part); 517 dcn314_smu_transfer_dpm_table_smu_2_dram(clk_mgr); 518 } 519 520 static inline bool is_valid_clock_value(uint32_t clock_value) 521 { 522 return clock_value > 1 && clock_value < 100000; 523 } 524 525 static unsigned int convert_wck_ratio(uint8_t wck_ratio) 526 { 527 switch (wck_ratio) { 528 case WCK_RATIO_1_2: 529 return 2; 530 531 case WCK_RATIO_1_4: 532 return 4; 533 534 default: 535 break; 536 } 537 return 1; 538 } 539 540 static uint32_t find_max_clk_value(const uint32_t clocks[], uint32_t num_clocks) 541 { 542 uint32_t max = 0; 543 int i; 544 545 for (i = 0; i < num_clocks; ++i) { 546 if (clocks[i] > max) 547 max = clocks[i]; 548 } 549 550 return max; 551 } 552 553 static void dcn314_clk_mgr_helper_populate_bw_params(struct clk_mgr_internal *clk_mgr, 554 struct integrated_info *bios_info, 555 const DpmClocks314_t *clock_table) 556 { 557 struct clk_bw_params *bw_params = clk_mgr->base.bw_params; 558 struct clk_limit_table_entry def_max = bw_params->clk_table.entries[bw_params->clk_table.num_entries - 1]; 559 uint32_t max_pstate = 0, max_fclk = 0, min_pstate = 0, max_dispclk = 0, max_dppclk = 0; 560 int i; 561 562 /* Find highest valid fclk pstate */ 563 for (i = 0; i < clock_table->NumDfPstatesEnabled; i++) { 564 if (is_valid_clock_value(clock_table->DfPstateTable[i].FClk) && 565 clock_table->DfPstateTable[i].FClk > max_fclk) { 566 max_fclk = clock_table->DfPstateTable[i].FClk; 567 max_pstate = i; 568 } 569 } 570 571 /* We expect the table to contain at least one valid fclk entry. */ 572 ASSERT(is_valid_clock_value(max_fclk)); 573 574 /* Dispclk and dppclk can be max at any voltage, same number of levels for both */ 575 if (clock_table->NumDispClkLevelsEnabled <= NUM_DISPCLK_DPM_LEVELS && 576 clock_table->NumDispClkLevelsEnabled <= NUM_DPPCLK_DPM_LEVELS) { 577 max_dispclk = find_max_clk_value(clock_table->DispClocks, clock_table->NumDispClkLevelsEnabled); 578 max_dppclk = find_max_clk_value(clock_table->DppClocks, clock_table->NumDispClkLevelsEnabled); 579 } else { 580 /* Invalid number of entries in the table from PMFW. */ 581 ASSERT(0); 582 } 583 584 /* Base the clock table on dcfclk, need at least one entry regardless of pmfw table */ 585 for (i = 0; i < clock_table->NumDcfClkLevelsEnabled; i++) { 586 uint32_t min_fclk = clock_table->DfPstateTable[0].FClk; 587 int j; 588 589 for (j = 1; j < clock_table->NumDfPstatesEnabled; j++) { 590 if (is_valid_clock_value(clock_table->DfPstateTable[j].FClk) && 591 clock_table->DfPstateTable[j].FClk < min_fclk && 592 clock_table->DfPstateTable[j].Voltage <= clock_table->SocVoltage[i]) { 593 min_fclk = clock_table->DfPstateTable[j].FClk; 594 min_pstate = j; 595 } 596 } 597 598 /* First search defaults for the clocks we don't read using closest lower or equal default dcfclk */ 599 for (j = bw_params->clk_table.num_entries - 1; j > 0; j--) 600 if (bw_params->clk_table.entries[j].dcfclk_mhz <= clock_table->DcfClocks[i]) 601 break; 602 603 bw_params->clk_table.entries[i].phyclk_mhz = bw_params->clk_table.entries[j].phyclk_mhz; 604 bw_params->clk_table.entries[i].phyclk_d18_mhz = bw_params->clk_table.entries[j].phyclk_d18_mhz; 605 bw_params->clk_table.entries[i].dtbclk_mhz = bw_params->clk_table.entries[j].dtbclk_mhz; 606 607 /* Now update clocks we do read */ 608 bw_params->clk_table.entries[i].fclk_mhz = min_fclk; 609 bw_params->clk_table.entries[i].memclk_mhz = clock_table->DfPstateTable[min_pstate].MemClk; 610 bw_params->clk_table.entries[i].voltage = clock_table->DfPstateTable[min_pstate].Voltage; 611 bw_params->clk_table.entries[i].dcfclk_mhz = clock_table->DcfClocks[i]; 612 bw_params->clk_table.entries[i].socclk_mhz = clock_table->SocClocks[i]; 613 bw_params->clk_table.entries[i].dispclk_mhz = max_dispclk; 614 bw_params->clk_table.entries[i].dppclk_mhz = max_dppclk; 615 bw_params->clk_table.entries[i].wck_ratio = convert_wck_ratio( 616 clock_table->DfPstateTable[min_pstate].WckRatio); 617 }; 618 619 /* Make sure to include at least one entry at highest pstate */ 620 if (max_pstate != min_pstate || i == 0) { 621 if (i > MAX_NUM_DPM_LVL - 1) 622 i = MAX_NUM_DPM_LVL - 1; 623 624 bw_params->clk_table.entries[i].fclk_mhz = max_fclk; 625 bw_params->clk_table.entries[i].memclk_mhz = clock_table->DfPstateTable[max_pstate].MemClk; 626 bw_params->clk_table.entries[i].voltage = clock_table->DfPstateTable[max_pstate].Voltage; 627 bw_params->clk_table.entries[i].dcfclk_mhz = find_max_clk_value(clock_table->DcfClocks, NUM_DCFCLK_DPM_LEVELS); 628 bw_params->clk_table.entries[i].socclk_mhz = find_max_clk_value(clock_table->SocClocks, NUM_SOCCLK_DPM_LEVELS); 629 bw_params->clk_table.entries[i].dispclk_mhz = max_dispclk; 630 bw_params->clk_table.entries[i].dppclk_mhz = max_dppclk; 631 bw_params->clk_table.entries[i].wck_ratio = convert_wck_ratio( 632 clock_table->DfPstateTable[max_pstate].WckRatio); 633 i++; 634 } 635 bw_params->clk_table.num_entries = i--; 636 637 /* Make sure all highest clocks are included*/ 638 bw_params->clk_table.entries[i].socclk_mhz = find_max_clk_value(clock_table->SocClocks, NUM_SOCCLK_DPM_LEVELS); 639 bw_params->clk_table.entries[i].dispclk_mhz = find_max_clk_value(clock_table->DispClocks, NUM_DISPCLK_DPM_LEVELS); 640 bw_params->clk_table.entries[i].dppclk_mhz = find_max_clk_value(clock_table->DppClocks, NUM_DPPCLK_DPM_LEVELS); 641 ASSERT(clock_table->DcfClocks[i] == find_max_clk_value(clock_table->DcfClocks, NUM_DCFCLK_DPM_LEVELS)); 642 bw_params->clk_table.entries[i].phyclk_mhz = def_max.phyclk_mhz; 643 bw_params->clk_table.entries[i].phyclk_d18_mhz = def_max.phyclk_d18_mhz; 644 bw_params->clk_table.entries[i].dtbclk_mhz = def_max.dtbclk_mhz; 645 646 /* 647 * Set any 0 clocks to max default setting. Not an issue for 648 * power since we aren't doing switching in such case anyway 649 */ 650 for (i = 0; i < bw_params->clk_table.num_entries; i++) { 651 if (!bw_params->clk_table.entries[i].fclk_mhz) { 652 bw_params->clk_table.entries[i].fclk_mhz = def_max.fclk_mhz; 653 bw_params->clk_table.entries[i].memclk_mhz = def_max.memclk_mhz; 654 bw_params->clk_table.entries[i].voltage = def_max.voltage; 655 } 656 if (!bw_params->clk_table.entries[i].dcfclk_mhz) 657 bw_params->clk_table.entries[i].dcfclk_mhz = def_max.dcfclk_mhz; 658 if (!bw_params->clk_table.entries[i].socclk_mhz) 659 bw_params->clk_table.entries[i].socclk_mhz = def_max.socclk_mhz; 660 if (!bw_params->clk_table.entries[i].dispclk_mhz) 661 bw_params->clk_table.entries[i].dispclk_mhz = def_max.dispclk_mhz; 662 if (!bw_params->clk_table.entries[i].dppclk_mhz) 663 bw_params->clk_table.entries[i].dppclk_mhz = def_max.dppclk_mhz; 664 if (!bw_params->clk_table.entries[i].phyclk_mhz) 665 bw_params->clk_table.entries[i].phyclk_mhz = def_max.phyclk_mhz; 666 if (!bw_params->clk_table.entries[i].phyclk_d18_mhz) 667 bw_params->clk_table.entries[i].phyclk_d18_mhz = def_max.phyclk_d18_mhz; 668 if (!bw_params->clk_table.entries[i].dtbclk_mhz) 669 bw_params->clk_table.entries[i].dtbclk_mhz = def_max.dtbclk_mhz; 670 } 671 ASSERT(bw_params->clk_table.entries[i-1].dcfclk_mhz); 672 bw_params->vram_type = bios_info->memory_type; 673 bw_params->num_channels = bios_info->ma_channel_number ? bios_info->ma_channel_number : 4; 674 675 for (i = 0; i < WM_SET_COUNT; i++) { 676 bw_params->wm_table.entries[i].wm_inst = i; 677 678 if (i >= bw_params->clk_table.num_entries) { 679 bw_params->wm_table.entries[i].valid = false; 680 continue; 681 } 682 683 bw_params->wm_table.entries[i].wm_type = WM_TYPE_PSTATE_CHG; 684 bw_params->wm_table.entries[i].valid = true; 685 } 686 } 687 688 static struct clk_mgr_funcs dcn314_funcs = { 689 .get_dp_ref_clk_frequency = dce12_get_dp_ref_freq_khz, 690 .get_dtb_ref_clk_frequency = dcn31_get_dtb_ref_freq_khz, 691 .update_clocks = dcn314_update_clocks, 692 .init_clocks = dcn31_init_clocks, 693 .enable_pme_wa = dcn314_enable_pme_wa, 694 .are_clock_states_equal = dcn314_are_clock_states_equal, 695 .notify_wm_ranges = dcn314_notify_wm_ranges 696 }; 697 extern struct clk_mgr_funcs dcn3_fpga_funcs; 698 699 void dcn314_clk_mgr_construct( 700 struct dc_context *ctx, 701 struct clk_mgr_dcn314 *clk_mgr, 702 struct pp_smu_funcs *pp_smu, 703 struct dccg *dccg) 704 { 705 struct dcn314_smu_dpm_clks smu_dpm_clks = { 0 }; 706 707 clk_mgr->base.base.ctx = ctx; 708 clk_mgr->base.base.funcs = &dcn314_funcs; 709 710 clk_mgr->base.pp_smu = pp_smu; 711 712 clk_mgr->base.dccg = dccg; 713 clk_mgr->base.dfs_bypass_disp_clk = 0; 714 715 clk_mgr->base.dprefclk_ss_percentage = 0; 716 clk_mgr->base.dprefclk_ss_divider = 1000; 717 clk_mgr->base.ss_on_dprefclk = false; 718 clk_mgr->base.dfs_ref_freq_khz = 48000; 719 720 clk_mgr->smu_wm_set.wm_set = (struct dcn314_watermarks *)dm_helpers_allocate_gpu_mem( 721 clk_mgr->base.base.ctx, 722 DC_MEM_ALLOC_TYPE_FRAME_BUFFER, 723 sizeof(struct dcn314_watermarks), 724 &clk_mgr->smu_wm_set.mc_address.quad_part); 725 726 if (!clk_mgr->smu_wm_set.wm_set) { 727 clk_mgr->smu_wm_set.wm_set = &dummy_wms; 728 clk_mgr->smu_wm_set.mc_address.quad_part = 0; 729 } 730 ASSERT(clk_mgr->smu_wm_set.wm_set); 731 732 smu_dpm_clks.dpm_clks = (DpmClocks314_t *)dm_helpers_allocate_gpu_mem( 733 clk_mgr->base.base.ctx, 734 DC_MEM_ALLOC_TYPE_FRAME_BUFFER, 735 sizeof(DpmClocks314_t), 736 &smu_dpm_clks.mc_address.quad_part); 737 738 if (smu_dpm_clks.dpm_clks == NULL) { 739 smu_dpm_clks.dpm_clks = &dummy_clocks; 740 smu_dpm_clks.mc_address.quad_part = 0; 741 } 742 743 ASSERT(smu_dpm_clks.dpm_clks); 744 745 if (IS_FPGA_MAXIMUS_DC(ctx->dce_environment)) { 746 clk_mgr->base.base.funcs = &dcn3_fpga_funcs; 747 } else { 748 struct clk_log_info log_info = {0}; 749 750 clk_mgr->base.smu_ver = dcn314_smu_get_smu_version(&clk_mgr->base); 751 752 if (clk_mgr->base.smu_ver) 753 clk_mgr->base.smu_present = true; 754 755 /* TODO: Check we get what we expect during bringup */ 756 clk_mgr->base.base.dentist_vco_freq_khz = get_vco_frequency_from_reg(&clk_mgr->base); 757 758 if (ctx->dc_bios->integrated_info->memory_type == LpDdr5MemType) 759 dcn314_bw_params.wm_table = lpddr5_wm_table; 760 else 761 dcn314_bw_params.wm_table = ddr5_wm_table; 762 763 /* Saved clocks configured at boot for debug purposes */ 764 dcn314_dump_clk_registers(&clk_mgr->base.base.boot_snapshot, 765 &clk_mgr->base.base, &log_info); 766 767 } 768 769 clk_mgr->base.base.dprefclk_khz = 600000; 770 clk_mgr->base.base.clks.ref_dtbclk_khz = 600000; 771 dce_clock_read_ss_info(&clk_mgr->base); 772 /*if bios enabled SS, driver needs to adjust dtb clock, only enable with correct bios*/ 773 //clk_mgr->base.dccg->ref_dtbclk_khz = dce_adjust_dp_ref_freq_for_ss(clk_mgr_internal, clk_mgr->base.base.dprefclk_khz); 774 775 clk_mgr->base.base.bw_params = &dcn314_bw_params; 776 777 if (clk_mgr->base.base.ctx->dc->debug.pstate_enabled) { 778 dcn314_get_dpm_table_from_smu(&clk_mgr->base, &smu_dpm_clks); 779 780 if (ctx->dc_bios && ctx->dc_bios->integrated_info && ctx->dc->config.use_default_clock_table == false) { 781 dcn314_clk_mgr_helper_populate_bw_params( 782 &clk_mgr->base, 783 ctx->dc_bios->integrated_info, 784 smu_dpm_clks.dpm_clks); 785 } 786 } 787 788 if (smu_dpm_clks.dpm_clks && smu_dpm_clks.mc_address.quad_part != 0) 789 dm_helpers_free_gpu_mem(clk_mgr->base.base.ctx, DC_MEM_ALLOC_TYPE_FRAME_BUFFER, 790 smu_dpm_clks.dpm_clks); 791 } 792 793 void dcn314_clk_mgr_destroy(struct clk_mgr_internal *clk_mgr_int) 794 { 795 struct clk_mgr_dcn314 *clk_mgr = TO_CLK_MGR_DCN314(clk_mgr_int); 796 797 if (clk_mgr->smu_wm_set.wm_set && clk_mgr->smu_wm_set.mc_address.quad_part != 0) 798 dm_helpers_free_gpu_mem(clk_mgr_int->base.ctx, DC_MEM_ALLOC_TYPE_FRAME_BUFFER, 799 clk_mgr->smu_wm_set.wm_set); 800 } 801