1 // SPDX-License-Identifier: MIT 2 /* 3 * Copyright 2022 Advanced Micro Devices, Inc. 4 * 5 * Permission is hereby granted, free of charge, to any person obtaining a 6 * copy of this software and associated documentation files (the "Software"), 7 * to deal in the Software without restriction, including without limitation 8 * the rights to use, copy, modify, merge, publish, distribute, sublicense, 9 * and/or sell copies of the Software, and to permit persons to whom the 10 * Software is furnished to do so, subject to the following conditions: 11 * 12 * The above copyright notice and this permission notice shall be included in 13 * all copies or substantial portions of the Software. 14 * 15 * THE SOFTWARE IS PROVIDED "AS IS", WITHOUT WARRANTY OF ANY KIND, EXPRESS OR 16 * IMPLIED, INCLUDING BUT NOT LIMITED TO THE WARRANTIES OF MERCHANTABILITY, 17 * FITNESS FOR A PARTICULAR PURPOSE AND NONINFRINGEMENT. IN NO EVENT SHALL 18 * THE COPYRIGHT HOLDER(S) OR AUTHOR(S) BE LIABLE FOR ANY CLAIM, DAMAGES OR 19 * OTHER LIABILITY, WHETHER IN AN ACTION OF CONTRACT, TORT OR OTHERWISE, 20 * ARISING FROM, OUT OF OR IN CONNECTION WITH THE SOFTWARE OR THE USE OR 21 * OTHER DEALINGS IN THE SOFTWARE. 22 * 23 * Authors: AMD 24 * 25 */ 26 27 28 29 #include "dcn314_clk_mgr.h" 30 31 #include "dccg.h" 32 #include "clk_mgr_internal.h" 33 34 // For dce12_get_dp_ref_freq_khz 35 #include "dce100/dce_clk_mgr.h" 36 37 // For dcn20_update_clocks_update_dpp_dto 38 #include "dcn20/dcn20_clk_mgr.h" 39 40 41 42 #include "reg_helper.h" 43 #include "core_types.h" 44 #include "dm_helpers.h" 45 46 /* TODO: remove this include once we ported over remaining clk mgr functions*/ 47 #include "dcn30/dcn30_clk_mgr.h" 48 #include "dcn31/dcn31_clk_mgr.h" 49 50 #include "dc_dmub_srv.h" 51 #include "dc_link_dp.h" 52 #include "dcn314_smu.h" 53 54 55 #include "logger_types.h" 56 #undef DC_LOGGER 57 #define DC_LOGGER \ 58 clk_mgr->base.base.ctx->logger 59 60 61 #define MAX_INSTANCE 7 62 #define MAX_SEGMENT 8 63 64 struct IP_BASE_INSTANCE { 65 unsigned int segment[MAX_SEGMENT]; 66 }; 67 68 struct IP_BASE { 69 struct IP_BASE_INSTANCE instance[MAX_INSTANCE]; 70 }; 71 72 static const struct IP_BASE CLK_BASE = { { { { 0x00016C00, 0x02401800, 0, 0, 0, 0, 0, 0 } }, 73 { { 0x00016E00, 0x02401C00, 0, 0, 0, 0, 0, 0 } }, 74 { { 0x00017000, 0x02402000, 0, 0, 0, 0, 0, 0 } }, 75 { { 0x00017200, 0x02402400, 0, 0, 0, 0, 0, 0 } }, 76 { { 0x0001B000, 0x0242D800, 0, 0, 0, 0, 0, 0 } }, 77 { { 0x0001B200, 0x0242DC00, 0, 0, 0, 0, 0, 0 } }, 78 { { 0x0001B400, 0x0242E000, 0, 0, 0, 0, 0, 0 } } } }; 79 80 #define regCLK1_CLK_PLL_REQ 0x0237 81 #define regCLK1_CLK_PLL_REQ_BASE_IDX 0 82 83 #define CLK1_CLK_PLL_REQ__FbMult_int__SHIFT 0x0 84 #define CLK1_CLK_PLL_REQ__PllSpineDiv__SHIFT 0xc 85 #define CLK1_CLK_PLL_REQ__FbMult_frac__SHIFT 0x10 86 #define CLK1_CLK_PLL_REQ__FbMult_int_MASK 0x000001FFL 87 #define CLK1_CLK_PLL_REQ__PllSpineDiv_MASK 0x0000F000L 88 #define CLK1_CLK_PLL_REQ__FbMult_frac_MASK 0xFFFF0000L 89 90 #define REG(reg_name) \ 91 (CLK_BASE.instance[0].segment[reg ## reg_name ## _BASE_IDX] + reg ## reg_name) 92 93 #define TO_CLK_MGR_DCN314(clk_mgr)\ 94 container_of(clk_mgr, struct clk_mgr_dcn314, base) 95 96 static int dcn314_get_active_display_cnt_wa( 97 struct dc *dc, 98 struct dc_state *context) 99 { 100 int i, display_count; 101 bool tmds_present = false; 102 103 display_count = 0; 104 for (i = 0; i < context->stream_count; i++) { 105 const struct dc_stream_state *stream = context->streams[i]; 106 107 if (stream->signal == SIGNAL_TYPE_HDMI_TYPE_A || 108 stream->signal == SIGNAL_TYPE_DVI_SINGLE_LINK || 109 stream->signal == SIGNAL_TYPE_DVI_DUAL_LINK) 110 tmds_present = true; 111 } 112 113 for (i = 0; i < dc->link_count; i++) { 114 const struct dc_link *link = dc->links[i]; 115 116 /* abusing the fact that the dig and phy are coupled to see if the phy is enabled */ 117 if (link->link_enc && link->link_enc->funcs->is_dig_enabled && 118 link->link_enc->funcs->is_dig_enabled(link->link_enc)) 119 display_count++; 120 } 121 122 /* WA for hang on HDMI after display off back on*/ 123 if (display_count == 0 && tmds_present) 124 display_count = 1; 125 126 return display_count; 127 } 128 129 static void dcn314_disable_otg_wa(struct clk_mgr *clk_mgr_base, struct dc_state *context, bool disable) 130 { 131 struct dc *dc = clk_mgr_base->ctx->dc; 132 int i; 133 134 for (i = 0; i < dc->res_pool->pipe_count; ++i) { 135 struct pipe_ctx *pipe = &dc->current_state->res_ctx.pipe_ctx[i]; 136 137 if (pipe->top_pipe || pipe->prev_odm_pipe) 138 continue; 139 if (pipe->stream && (pipe->stream->dpms_off || dc_is_virtual_signal(pipe->stream->signal))) { 140 struct stream_encoder *stream_enc = pipe->stream_res.stream_enc; 141 142 if (disable) { 143 if (stream_enc && stream_enc->funcs->disable_fifo) 144 pipe->stream_res.stream_enc->funcs->disable_fifo(stream_enc); 145 146 pipe->stream_res.tg->funcs->immediate_disable_crtc(pipe->stream_res.tg); 147 reset_sync_context_for_pipe(dc, context, i); 148 } else { 149 pipe->stream_res.tg->funcs->enable_crtc(pipe->stream_res.tg); 150 151 if (stream_enc && stream_enc->funcs->enable_fifo) 152 pipe->stream_res.stream_enc->funcs->enable_fifo(stream_enc); 153 } 154 } 155 } 156 } 157 158 void dcn314_update_clocks(struct clk_mgr *clk_mgr_base, 159 struct dc_state *context, 160 bool safe_to_lower) 161 { 162 union dmub_rb_cmd cmd; 163 struct clk_mgr_internal *clk_mgr = TO_CLK_MGR_INTERNAL(clk_mgr_base); 164 struct dc_clocks *new_clocks = &context->bw_ctx.bw.dcn.clk; 165 struct dc *dc = clk_mgr_base->ctx->dc; 166 int display_count; 167 bool update_dppclk = false; 168 bool update_dispclk = false; 169 bool dpp_clock_lowered = false; 170 171 if (dc->work_arounds.skip_clock_update) 172 return; 173 174 /* 175 * if it is safe to lower, but we are already in the lower state, we don't have to do anything 176 * also if safe to lower is false, we just go in the higher state 177 */ 178 if (safe_to_lower) { 179 if (new_clocks->zstate_support != DCN_ZSTATE_SUPPORT_DISALLOW && 180 new_clocks->zstate_support != clk_mgr_base->clks.zstate_support) { 181 dcn314_smu_set_zstate_support(clk_mgr, new_clocks->zstate_support); 182 dm_helpers_enable_periodic_detection(clk_mgr_base->ctx, true); 183 clk_mgr_base->clks.zstate_support = new_clocks->zstate_support; 184 } 185 186 if (clk_mgr_base->clks.dtbclk_en && !new_clocks->dtbclk_en) { 187 dcn314_smu_set_dtbclk(clk_mgr, false); 188 clk_mgr_base->clks.dtbclk_en = new_clocks->dtbclk_en; 189 } 190 /* check that we're not already in lower */ 191 if (clk_mgr_base->clks.pwr_state != DCN_PWR_STATE_LOW_POWER) { 192 display_count = dcn314_get_active_display_cnt_wa(dc, context); 193 /* if we can go lower, go lower */ 194 if (display_count == 0) { 195 union display_idle_optimization_u idle_info = { 0 }; 196 idle_info.idle_info.df_request_disabled = 1; 197 idle_info.idle_info.phy_ref_clk_off = 1; 198 idle_info.idle_info.s0i2_rdy = 1; 199 dcn314_smu_set_display_idle_optimization(clk_mgr, idle_info.data); 200 /* update power state */ 201 clk_mgr_base->clks.pwr_state = DCN_PWR_STATE_LOW_POWER; 202 } 203 } 204 } else { 205 if (new_clocks->zstate_support == DCN_ZSTATE_SUPPORT_DISALLOW && 206 new_clocks->zstate_support != clk_mgr_base->clks.zstate_support) { 207 dcn314_smu_set_zstate_support(clk_mgr, DCN_ZSTATE_SUPPORT_DISALLOW); 208 dm_helpers_enable_periodic_detection(clk_mgr_base->ctx, false); 209 clk_mgr_base->clks.zstate_support = new_clocks->zstate_support; 210 } 211 212 if (!clk_mgr_base->clks.dtbclk_en && new_clocks->dtbclk_en) { 213 dcn314_smu_set_dtbclk(clk_mgr, true); 214 clk_mgr_base->clks.dtbclk_en = new_clocks->dtbclk_en; 215 } 216 217 /* check that we're not already in D0 */ 218 if (clk_mgr_base->clks.pwr_state != DCN_PWR_STATE_MISSION_MODE) { 219 union display_idle_optimization_u idle_info = { 0 }; 220 221 dcn314_smu_set_display_idle_optimization(clk_mgr, idle_info.data); 222 /* update power state */ 223 clk_mgr_base->clks.pwr_state = DCN_PWR_STATE_MISSION_MODE; 224 } 225 } 226 227 if (should_set_clock(safe_to_lower, new_clocks->dcfclk_khz, clk_mgr_base->clks.dcfclk_khz)) { 228 clk_mgr_base->clks.dcfclk_khz = new_clocks->dcfclk_khz; 229 dcn314_smu_set_hard_min_dcfclk(clk_mgr, clk_mgr_base->clks.dcfclk_khz); 230 } 231 232 if (should_set_clock(safe_to_lower, 233 new_clocks->dcfclk_deep_sleep_khz, clk_mgr_base->clks.dcfclk_deep_sleep_khz)) { 234 clk_mgr_base->clks.dcfclk_deep_sleep_khz = new_clocks->dcfclk_deep_sleep_khz; 235 dcn314_smu_set_min_deep_sleep_dcfclk(clk_mgr, clk_mgr_base->clks.dcfclk_deep_sleep_khz); 236 } 237 238 // workaround: Limit dppclk to 100Mhz to avoid lower eDP panel switch to plus 4K monitor underflow. 239 if (!IS_DIAG_DC(dc->ctx->dce_environment)) { 240 if (new_clocks->dppclk_khz < 100000) 241 new_clocks->dppclk_khz = 100000; 242 } 243 244 if (should_set_clock(safe_to_lower, new_clocks->dppclk_khz, clk_mgr->base.clks.dppclk_khz)) { 245 if (clk_mgr->base.clks.dppclk_khz > new_clocks->dppclk_khz) 246 dpp_clock_lowered = true; 247 clk_mgr_base->clks.dppclk_khz = new_clocks->dppclk_khz; 248 update_dppclk = true; 249 } 250 251 if (should_set_clock(safe_to_lower, new_clocks->dispclk_khz, clk_mgr_base->clks.dispclk_khz)) { 252 dcn314_disable_otg_wa(clk_mgr_base, context, true); 253 254 clk_mgr_base->clks.dispclk_khz = new_clocks->dispclk_khz; 255 dcn314_smu_set_dispclk(clk_mgr, clk_mgr_base->clks.dispclk_khz); 256 dcn314_disable_otg_wa(clk_mgr_base, context, false); 257 258 update_dispclk = true; 259 } 260 261 if (dpp_clock_lowered) { 262 // increase per DPP DTO before lowering global dppclk 263 dcn20_update_clocks_update_dpp_dto(clk_mgr, context, safe_to_lower); 264 dcn314_smu_set_dppclk(clk_mgr, clk_mgr_base->clks.dppclk_khz); 265 } else { 266 // increase global DPPCLK before lowering per DPP DTO 267 if (update_dppclk || update_dispclk) 268 dcn314_smu_set_dppclk(clk_mgr, clk_mgr_base->clks.dppclk_khz); 269 // always update dtos unless clock is lowered and not safe to lower 270 if (new_clocks->dppclk_khz >= dc->current_state->bw_ctx.bw.dcn.clk.dppclk_khz) 271 dcn20_update_clocks_update_dpp_dto(clk_mgr, context, safe_to_lower); 272 } 273 274 // notify DMCUB of latest clocks 275 memset(&cmd, 0, sizeof(cmd)); 276 cmd.notify_clocks.header.type = DMUB_CMD__CLK_MGR; 277 cmd.notify_clocks.header.sub_type = DMUB_CMD__CLK_MGR_NOTIFY_CLOCKS; 278 cmd.notify_clocks.clocks.dcfclk_khz = clk_mgr_base->clks.dcfclk_khz; 279 cmd.notify_clocks.clocks.dcfclk_deep_sleep_khz = 280 clk_mgr_base->clks.dcfclk_deep_sleep_khz; 281 cmd.notify_clocks.clocks.dispclk_khz = clk_mgr_base->clks.dispclk_khz; 282 cmd.notify_clocks.clocks.dppclk_khz = clk_mgr_base->clks.dppclk_khz; 283 284 dc_dmub_srv_cmd_queue(dc->ctx->dmub_srv, &cmd); 285 dc_dmub_srv_cmd_execute(dc->ctx->dmub_srv); 286 dc_dmub_srv_wait_idle(dc->ctx->dmub_srv); 287 } 288 289 static int get_vco_frequency_from_reg(struct clk_mgr_internal *clk_mgr) 290 { 291 /* get FbMult value */ 292 struct fixed31_32 pll_req; 293 unsigned int fbmult_frac_val = 0; 294 unsigned int fbmult_int_val = 0; 295 296 /* 297 * Register value of fbmult is in 8.16 format, we are converting to 314.32 298 * to leverage the fix point operations available in driver 299 */ 300 301 REG_GET(CLK1_CLK_PLL_REQ, FbMult_frac, &fbmult_frac_val); /* 16 bit fractional part*/ 302 REG_GET(CLK1_CLK_PLL_REQ, FbMult_int, &fbmult_int_val); /* 8 bit integer part */ 303 304 pll_req = dc_fixpt_from_int(fbmult_int_val); 305 306 /* 307 * since fractional part is only 16 bit in register definition but is 32 bit 308 * in our fix point definiton, need to shift left by 16 to obtain correct value 309 */ 310 pll_req.value |= fbmult_frac_val << 16; 311 312 /* multiply by REFCLK period */ 313 pll_req = dc_fixpt_mul_int(pll_req, clk_mgr->dfs_ref_freq_khz); 314 315 /* integer part is now VCO frequency in kHz */ 316 return dc_fixpt_floor(pll_req); 317 } 318 319 static void dcn314_enable_pme_wa(struct clk_mgr *clk_mgr_base) 320 { 321 struct clk_mgr_internal *clk_mgr = TO_CLK_MGR_INTERNAL(clk_mgr_base); 322 323 dcn314_smu_enable_pme_wa(clk_mgr); 324 } 325 326 bool dcn314_are_clock_states_equal(struct dc_clocks *a, 327 struct dc_clocks *b) 328 { 329 if (a->dispclk_khz != b->dispclk_khz) 330 return false; 331 else if (a->dppclk_khz != b->dppclk_khz) 332 return false; 333 else if (a->dcfclk_khz != b->dcfclk_khz) 334 return false; 335 else if (a->dcfclk_deep_sleep_khz != b->dcfclk_deep_sleep_khz) 336 return false; 337 else if (a->zstate_support != b->zstate_support) 338 return false; 339 else if (a->dtbclk_en != b->dtbclk_en) 340 return false; 341 342 return true; 343 } 344 345 static void dcn314_dump_clk_registers(struct clk_state_registers_and_bypass *regs_and_bypass, 346 struct clk_mgr *clk_mgr_base, struct clk_log_info *log_info) 347 { 348 return; 349 } 350 351 static struct clk_bw_params dcn314_bw_params = { 352 .vram_type = Ddr4MemType, 353 .num_channels = 1, 354 .clk_table = { 355 .num_entries = 4, 356 }, 357 358 }; 359 360 static struct wm_table ddr5_wm_table = { 361 .entries = { 362 { 363 .wm_inst = WM_A, 364 .wm_type = WM_TYPE_PSTATE_CHG, 365 .pstate_latency_us = 11.72, 366 .sr_exit_time_us = 12.5, 367 .sr_enter_plus_exit_time_us = 14.5, 368 .valid = true, 369 }, 370 { 371 .wm_inst = WM_B, 372 .wm_type = WM_TYPE_PSTATE_CHG, 373 .pstate_latency_us = 11.72, 374 .sr_exit_time_us = 12.5, 375 .sr_enter_plus_exit_time_us = 14.5, 376 .valid = true, 377 }, 378 { 379 .wm_inst = WM_C, 380 .wm_type = WM_TYPE_PSTATE_CHG, 381 .pstate_latency_us = 11.72, 382 .sr_exit_time_us = 12.5, 383 .sr_enter_plus_exit_time_us = 14.5, 384 .valid = true, 385 }, 386 { 387 .wm_inst = WM_D, 388 .wm_type = WM_TYPE_PSTATE_CHG, 389 .pstate_latency_us = 11.72, 390 .sr_exit_time_us = 12.5, 391 .sr_enter_plus_exit_time_us = 14.5, 392 .valid = true, 393 }, 394 } 395 }; 396 397 static struct wm_table lpddr5_wm_table = { 398 .entries = { 399 { 400 .wm_inst = WM_A, 401 .wm_type = WM_TYPE_PSTATE_CHG, 402 .pstate_latency_us = 11.65333, 403 .sr_exit_time_us = 16.5, 404 .sr_enter_plus_exit_time_us = 18.5, 405 .valid = true, 406 }, 407 { 408 .wm_inst = WM_B, 409 .wm_type = WM_TYPE_PSTATE_CHG, 410 .pstate_latency_us = 11.65333, 411 .sr_exit_time_us = 16.5, 412 .sr_enter_plus_exit_time_us = 18.5, 413 .valid = true, 414 }, 415 { 416 .wm_inst = WM_C, 417 .wm_type = WM_TYPE_PSTATE_CHG, 418 .pstate_latency_us = 11.65333, 419 .sr_exit_time_us = 16.5, 420 .sr_enter_plus_exit_time_us = 18.5, 421 .valid = true, 422 }, 423 { 424 .wm_inst = WM_D, 425 .wm_type = WM_TYPE_PSTATE_CHG, 426 .pstate_latency_us = 11.65333, 427 .sr_exit_time_us = 16.5, 428 .sr_enter_plus_exit_time_us = 18.5, 429 .valid = true, 430 }, 431 } 432 }; 433 434 static DpmClocks314_t dummy_clocks; 435 436 static struct dcn314_watermarks dummy_wms = { 0 }; 437 438 static void dcn314_build_watermark_ranges(struct clk_bw_params *bw_params, struct dcn314_watermarks *table) 439 { 440 int i, num_valid_sets; 441 442 num_valid_sets = 0; 443 444 for (i = 0; i < WM_SET_COUNT; i++) { 445 /* skip empty entries, the smu array has no holes*/ 446 if (!bw_params->wm_table.entries[i].valid) 447 continue; 448 449 table->WatermarkRow[WM_DCFCLK][num_valid_sets].WmSetting = bw_params->wm_table.entries[i].wm_inst; 450 table->WatermarkRow[WM_DCFCLK][num_valid_sets].WmType = bw_params->wm_table.entries[i].wm_type; 451 /* We will not select WM based on fclk, so leave it as unconstrained */ 452 table->WatermarkRow[WM_DCFCLK][num_valid_sets].MinClock = 0; 453 table->WatermarkRow[WM_DCFCLK][num_valid_sets].MaxClock = 0xFFFF; 454 455 if (table->WatermarkRow[WM_DCFCLK][num_valid_sets].WmType == WM_TYPE_PSTATE_CHG) { 456 if (i == 0) 457 table->WatermarkRow[WM_DCFCLK][num_valid_sets].MinMclk = 0; 458 else { 459 /* add 1 to make it non-overlapping with next lvl */ 460 table->WatermarkRow[WM_DCFCLK][num_valid_sets].MinMclk = 461 bw_params->clk_table.entries[i - 1].dcfclk_mhz + 1; 462 } 463 table->WatermarkRow[WM_DCFCLK][num_valid_sets].MaxMclk = 464 bw_params->clk_table.entries[i].dcfclk_mhz; 465 466 } else { 467 /* unconstrained for memory retraining */ 468 table->WatermarkRow[WM_DCFCLK][num_valid_sets].MinClock = 0; 469 table->WatermarkRow[WM_DCFCLK][num_valid_sets].MaxClock = 0xFFFF; 470 471 /* Modify previous watermark range to cover up to max */ 472 table->WatermarkRow[WM_DCFCLK][num_valid_sets - 1].MaxClock = 0xFFFF; 473 } 474 num_valid_sets++; 475 } 476 477 ASSERT(num_valid_sets != 0); /* Must have at least one set of valid watermarks */ 478 479 /* modify the min and max to make sure we cover the whole range*/ 480 table->WatermarkRow[WM_DCFCLK][0].MinMclk = 0; 481 table->WatermarkRow[WM_DCFCLK][0].MinClock = 0; 482 table->WatermarkRow[WM_DCFCLK][num_valid_sets - 1].MaxMclk = 0xFFFF; 483 table->WatermarkRow[WM_DCFCLK][num_valid_sets - 1].MaxClock = 0xFFFF; 484 485 /* This is for writeback only, does not matter currently as no writeback support*/ 486 table->WatermarkRow[WM_SOCCLK][0].WmSetting = WM_A; 487 table->WatermarkRow[WM_SOCCLK][0].MinClock = 0; 488 table->WatermarkRow[WM_SOCCLK][0].MaxClock = 0xFFFF; 489 table->WatermarkRow[WM_SOCCLK][0].MinMclk = 0; 490 table->WatermarkRow[WM_SOCCLK][0].MaxMclk = 0xFFFF; 491 } 492 493 static void dcn314_notify_wm_ranges(struct clk_mgr *clk_mgr_base) 494 { 495 struct clk_mgr_internal *clk_mgr = TO_CLK_MGR_INTERNAL(clk_mgr_base); 496 struct clk_mgr_dcn314 *clk_mgr_dcn314 = TO_CLK_MGR_DCN314(clk_mgr); 497 struct dcn314_watermarks *table = clk_mgr_dcn314->smu_wm_set.wm_set; 498 499 if (!clk_mgr->smu_ver) 500 return; 501 502 if (!table || clk_mgr_dcn314->smu_wm_set.mc_address.quad_part == 0) 503 return; 504 505 memset(table, 0, sizeof(*table)); 506 507 dcn314_build_watermark_ranges(clk_mgr_base->bw_params, table); 508 509 dcn314_smu_set_dram_addr_high(clk_mgr, 510 clk_mgr_dcn314->smu_wm_set.mc_address.high_part); 511 dcn314_smu_set_dram_addr_low(clk_mgr, 512 clk_mgr_dcn314->smu_wm_set.mc_address.low_part); 513 dcn314_smu_transfer_wm_table_dram_2_smu(clk_mgr); 514 } 515 516 static void dcn314_get_dpm_table_from_smu(struct clk_mgr_internal *clk_mgr, 517 struct dcn314_smu_dpm_clks *smu_dpm_clks) 518 { 519 DpmClocks314_t *table = smu_dpm_clks->dpm_clks; 520 521 if (!clk_mgr->smu_ver) 522 return; 523 524 if (!table || smu_dpm_clks->mc_address.quad_part == 0) 525 return; 526 527 memset(table, 0, sizeof(*table)); 528 529 dcn314_smu_set_dram_addr_high(clk_mgr, 530 smu_dpm_clks->mc_address.high_part); 531 dcn314_smu_set_dram_addr_low(clk_mgr, 532 smu_dpm_clks->mc_address.low_part); 533 dcn314_smu_transfer_dpm_table_smu_2_dram(clk_mgr); 534 } 535 536 static inline bool is_valid_clock_value(uint32_t clock_value) 537 { 538 return clock_value > 1 && clock_value < 100000; 539 } 540 541 static unsigned int convert_wck_ratio(uint8_t wck_ratio) 542 { 543 switch (wck_ratio) { 544 case WCK_RATIO_1_2: 545 return 2; 546 547 case WCK_RATIO_1_4: 548 return 4; 549 550 default: 551 break; 552 } 553 return 1; 554 } 555 556 static uint32_t find_max_clk_value(const uint32_t clocks[], uint32_t num_clocks) 557 { 558 uint32_t max = 0; 559 int i; 560 561 for (i = 0; i < num_clocks; ++i) { 562 if (clocks[i] > max) 563 max = clocks[i]; 564 } 565 566 return max; 567 } 568 569 static void dcn314_clk_mgr_helper_populate_bw_params(struct clk_mgr_internal *clk_mgr, 570 struct integrated_info *bios_info, 571 const DpmClocks314_t *clock_table) 572 { 573 struct clk_bw_params *bw_params = clk_mgr->base.bw_params; 574 struct clk_limit_table_entry def_max = bw_params->clk_table.entries[bw_params->clk_table.num_entries - 1]; 575 uint32_t max_pstate = 0, max_fclk = 0, min_pstate = 0, max_dispclk = 0, max_dppclk = 0; 576 int i; 577 578 /* Find highest valid fclk pstate */ 579 for (i = 0; i < clock_table->NumDfPstatesEnabled; i++) { 580 if (is_valid_clock_value(clock_table->DfPstateTable[i].FClk) && 581 clock_table->DfPstateTable[i].FClk > max_fclk) { 582 max_fclk = clock_table->DfPstateTable[i].FClk; 583 max_pstate = i; 584 } 585 } 586 587 /* We expect the table to contain at least one valid fclk entry. */ 588 ASSERT(is_valid_clock_value(max_fclk)); 589 590 /* Dispclk and dppclk can be max at any voltage, same number of levels for both */ 591 if (clock_table->NumDispClkLevelsEnabled <= NUM_DISPCLK_DPM_LEVELS && 592 clock_table->NumDispClkLevelsEnabled <= NUM_DPPCLK_DPM_LEVELS) { 593 max_dispclk = find_max_clk_value(clock_table->DispClocks, clock_table->NumDispClkLevelsEnabled); 594 max_dppclk = find_max_clk_value(clock_table->DppClocks, clock_table->NumDispClkLevelsEnabled); 595 } else { 596 /* Invalid number of entries in the table from PMFW. */ 597 ASSERT(0); 598 } 599 600 /* Base the clock table on dcfclk, need at least one entry regardless of pmfw table */ 601 for (i = 0; i < clock_table->NumDcfClkLevelsEnabled; i++) { 602 uint32_t min_fclk = clock_table->DfPstateTable[0].FClk; 603 int j; 604 605 for (j = 1; j < clock_table->NumDfPstatesEnabled; j++) { 606 if (is_valid_clock_value(clock_table->DfPstateTable[j].FClk) && 607 clock_table->DfPstateTable[j].FClk < min_fclk && 608 clock_table->DfPstateTable[j].Voltage <= clock_table->SocVoltage[i]) { 609 min_fclk = clock_table->DfPstateTable[j].FClk; 610 min_pstate = j; 611 } 612 } 613 614 /* First search defaults for the clocks we don't read using closest lower or equal default dcfclk */ 615 for (j = bw_params->clk_table.num_entries - 1; j > 0; j--) 616 if (bw_params->clk_table.entries[j].dcfclk_mhz <= clock_table->DcfClocks[i]) 617 break; 618 619 bw_params->clk_table.entries[i].phyclk_mhz = bw_params->clk_table.entries[j].phyclk_mhz; 620 bw_params->clk_table.entries[i].phyclk_d18_mhz = bw_params->clk_table.entries[j].phyclk_d18_mhz; 621 bw_params->clk_table.entries[i].dtbclk_mhz = bw_params->clk_table.entries[j].dtbclk_mhz; 622 623 /* Now update clocks we do read */ 624 bw_params->clk_table.entries[i].fclk_mhz = min_fclk; 625 bw_params->clk_table.entries[i].memclk_mhz = clock_table->DfPstateTable[min_pstate].MemClk; 626 bw_params->clk_table.entries[i].voltage = clock_table->DfPstateTable[min_pstate].Voltage; 627 bw_params->clk_table.entries[i].dcfclk_mhz = clock_table->DcfClocks[i]; 628 bw_params->clk_table.entries[i].socclk_mhz = clock_table->SocClocks[i]; 629 bw_params->clk_table.entries[i].dispclk_mhz = max_dispclk; 630 bw_params->clk_table.entries[i].dppclk_mhz = max_dppclk; 631 bw_params->clk_table.entries[i].wck_ratio = convert_wck_ratio( 632 clock_table->DfPstateTable[min_pstate].WckRatio); 633 } 634 635 /* Make sure to include at least one entry at highest pstate */ 636 if (max_pstate != min_pstate || i == 0) { 637 if (i > MAX_NUM_DPM_LVL - 1) 638 i = MAX_NUM_DPM_LVL - 1; 639 640 bw_params->clk_table.entries[i].fclk_mhz = max_fclk; 641 bw_params->clk_table.entries[i].memclk_mhz = clock_table->DfPstateTable[max_pstate].MemClk; 642 bw_params->clk_table.entries[i].voltage = clock_table->DfPstateTable[max_pstate].Voltage; 643 bw_params->clk_table.entries[i].dcfclk_mhz = find_max_clk_value(clock_table->DcfClocks, NUM_DCFCLK_DPM_LEVELS); 644 bw_params->clk_table.entries[i].socclk_mhz = find_max_clk_value(clock_table->SocClocks, NUM_SOCCLK_DPM_LEVELS); 645 bw_params->clk_table.entries[i].dispclk_mhz = max_dispclk; 646 bw_params->clk_table.entries[i].dppclk_mhz = max_dppclk; 647 bw_params->clk_table.entries[i].wck_ratio = convert_wck_ratio( 648 clock_table->DfPstateTable[max_pstate].WckRatio); 649 i++; 650 } 651 bw_params->clk_table.num_entries = i--; 652 653 /* Make sure all highest clocks are included*/ 654 bw_params->clk_table.entries[i].socclk_mhz = find_max_clk_value(clock_table->SocClocks, NUM_SOCCLK_DPM_LEVELS); 655 bw_params->clk_table.entries[i].dispclk_mhz = find_max_clk_value(clock_table->DispClocks, NUM_DISPCLK_DPM_LEVELS); 656 bw_params->clk_table.entries[i].dppclk_mhz = find_max_clk_value(clock_table->DppClocks, NUM_DPPCLK_DPM_LEVELS); 657 ASSERT(clock_table->DcfClocks[i] == find_max_clk_value(clock_table->DcfClocks, NUM_DCFCLK_DPM_LEVELS)); 658 bw_params->clk_table.entries[i].phyclk_mhz = def_max.phyclk_mhz; 659 bw_params->clk_table.entries[i].phyclk_d18_mhz = def_max.phyclk_d18_mhz; 660 bw_params->clk_table.entries[i].dtbclk_mhz = def_max.dtbclk_mhz; 661 662 /* 663 * Set any 0 clocks to max default setting. Not an issue for 664 * power since we aren't doing switching in such case anyway 665 */ 666 for (i = 0; i < bw_params->clk_table.num_entries; i++) { 667 if (!bw_params->clk_table.entries[i].fclk_mhz) { 668 bw_params->clk_table.entries[i].fclk_mhz = def_max.fclk_mhz; 669 bw_params->clk_table.entries[i].memclk_mhz = def_max.memclk_mhz; 670 bw_params->clk_table.entries[i].voltage = def_max.voltage; 671 } 672 if (!bw_params->clk_table.entries[i].dcfclk_mhz) 673 bw_params->clk_table.entries[i].dcfclk_mhz = def_max.dcfclk_mhz; 674 if (!bw_params->clk_table.entries[i].socclk_mhz) 675 bw_params->clk_table.entries[i].socclk_mhz = def_max.socclk_mhz; 676 if (!bw_params->clk_table.entries[i].dispclk_mhz) 677 bw_params->clk_table.entries[i].dispclk_mhz = def_max.dispclk_mhz; 678 if (!bw_params->clk_table.entries[i].dppclk_mhz) 679 bw_params->clk_table.entries[i].dppclk_mhz = def_max.dppclk_mhz; 680 if (!bw_params->clk_table.entries[i].phyclk_mhz) 681 bw_params->clk_table.entries[i].phyclk_mhz = def_max.phyclk_mhz; 682 if (!bw_params->clk_table.entries[i].phyclk_d18_mhz) 683 bw_params->clk_table.entries[i].phyclk_d18_mhz = def_max.phyclk_d18_mhz; 684 if (!bw_params->clk_table.entries[i].dtbclk_mhz) 685 bw_params->clk_table.entries[i].dtbclk_mhz = def_max.dtbclk_mhz; 686 } 687 ASSERT(bw_params->clk_table.entries[i-1].dcfclk_mhz); 688 bw_params->vram_type = bios_info->memory_type; 689 690 bw_params->dram_channel_width_bytes = bios_info->memory_type == 0x22 ? 8 : 4; 691 bw_params->num_channels = bios_info->ma_channel_number ? bios_info->ma_channel_number : 4; 692 693 for (i = 0; i < WM_SET_COUNT; i++) { 694 bw_params->wm_table.entries[i].wm_inst = i; 695 696 if (i >= bw_params->clk_table.num_entries) { 697 bw_params->wm_table.entries[i].valid = false; 698 continue; 699 } 700 701 bw_params->wm_table.entries[i].wm_type = WM_TYPE_PSTATE_CHG; 702 bw_params->wm_table.entries[i].valid = true; 703 } 704 } 705 706 static struct clk_mgr_funcs dcn314_funcs = { 707 .get_dp_ref_clk_frequency = dce12_get_dp_ref_freq_khz, 708 .get_dtb_ref_clk_frequency = dcn31_get_dtb_ref_freq_khz, 709 .update_clocks = dcn314_update_clocks, 710 .init_clocks = dcn31_init_clocks, 711 .enable_pme_wa = dcn314_enable_pme_wa, 712 .are_clock_states_equal = dcn314_are_clock_states_equal, 713 .notify_wm_ranges = dcn314_notify_wm_ranges 714 }; 715 extern struct clk_mgr_funcs dcn3_fpga_funcs; 716 717 void dcn314_clk_mgr_construct( 718 struct dc_context *ctx, 719 struct clk_mgr_dcn314 *clk_mgr, 720 struct pp_smu_funcs *pp_smu, 721 struct dccg *dccg) 722 { 723 struct dcn314_smu_dpm_clks smu_dpm_clks = { 0 }; 724 725 clk_mgr->base.base.ctx = ctx; 726 clk_mgr->base.base.funcs = &dcn314_funcs; 727 728 clk_mgr->base.pp_smu = pp_smu; 729 730 clk_mgr->base.dccg = dccg; 731 clk_mgr->base.dfs_bypass_disp_clk = 0; 732 733 clk_mgr->base.dprefclk_ss_percentage = 0; 734 clk_mgr->base.dprefclk_ss_divider = 1000; 735 clk_mgr->base.ss_on_dprefclk = false; 736 clk_mgr->base.dfs_ref_freq_khz = 48000; 737 738 clk_mgr->smu_wm_set.wm_set = (struct dcn314_watermarks *)dm_helpers_allocate_gpu_mem( 739 clk_mgr->base.base.ctx, 740 DC_MEM_ALLOC_TYPE_FRAME_BUFFER, 741 sizeof(struct dcn314_watermarks), 742 &clk_mgr->smu_wm_set.mc_address.quad_part); 743 744 if (!clk_mgr->smu_wm_set.wm_set) { 745 clk_mgr->smu_wm_set.wm_set = &dummy_wms; 746 clk_mgr->smu_wm_set.mc_address.quad_part = 0; 747 } 748 ASSERT(clk_mgr->smu_wm_set.wm_set); 749 750 smu_dpm_clks.dpm_clks = (DpmClocks314_t *)dm_helpers_allocate_gpu_mem( 751 clk_mgr->base.base.ctx, 752 DC_MEM_ALLOC_TYPE_FRAME_BUFFER, 753 sizeof(DpmClocks314_t), 754 &smu_dpm_clks.mc_address.quad_part); 755 756 if (smu_dpm_clks.dpm_clks == NULL) { 757 smu_dpm_clks.dpm_clks = &dummy_clocks; 758 smu_dpm_clks.mc_address.quad_part = 0; 759 } 760 761 ASSERT(smu_dpm_clks.dpm_clks); 762 763 if (IS_FPGA_MAXIMUS_DC(ctx->dce_environment)) { 764 clk_mgr->base.base.funcs = &dcn3_fpga_funcs; 765 } else { 766 struct clk_log_info log_info = {0}; 767 768 clk_mgr->base.smu_ver = dcn314_smu_get_smu_version(&clk_mgr->base); 769 770 if (clk_mgr->base.smu_ver) 771 clk_mgr->base.smu_present = true; 772 773 /* TODO: Check we get what we expect during bringup */ 774 clk_mgr->base.base.dentist_vco_freq_khz = get_vco_frequency_from_reg(&clk_mgr->base); 775 776 if (ctx->dc_bios->integrated_info->memory_type == LpDdr5MemType) 777 dcn314_bw_params.wm_table = lpddr5_wm_table; 778 else 779 dcn314_bw_params.wm_table = ddr5_wm_table; 780 781 /* Saved clocks configured at boot for debug purposes */ 782 dcn314_dump_clk_registers(&clk_mgr->base.base.boot_snapshot, 783 &clk_mgr->base.base, &log_info); 784 785 } 786 787 clk_mgr->base.base.dprefclk_khz = 600000; 788 clk_mgr->base.base.clks.ref_dtbclk_khz = 600000; 789 dce_clock_read_ss_info(&clk_mgr->base); 790 /*if bios enabled SS, driver needs to adjust dtb clock, only enable with correct bios*/ 791 //clk_mgr->base.dccg->ref_dtbclk_khz = dce_adjust_dp_ref_freq_for_ss(clk_mgr_internal, clk_mgr->base.base.dprefclk_khz); 792 793 clk_mgr->base.base.bw_params = &dcn314_bw_params; 794 795 if (clk_mgr->base.base.ctx->dc->debug.pstate_enabled) { 796 int i; 797 798 dcn314_get_dpm_table_from_smu(&clk_mgr->base, &smu_dpm_clks); 799 DC_LOG_SMU("NumDcfClkLevelsEnabled: %d\n" 800 "NumDispClkLevelsEnabled: %d\n" 801 "NumSocClkLevelsEnabled: %d\n" 802 "VcnClkLevelsEnabled: %d\n" 803 "NumDfPst atesEnabled: %d\n" 804 "MinGfxClk: %d\n" 805 "MaxGfxClk: %d\n", 806 smu_dpm_clks.dpm_clks->NumDcfClkLevelsEnabled, 807 smu_dpm_clks.dpm_clks->NumDispClkLevelsEnabled, 808 smu_dpm_clks.dpm_clks->NumSocClkLevelsEnabled, 809 smu_dpm_clks.dpm_clks->VcnClkLevelsEnabled, 810 smu_dpm_clks.dpm_clks->NumDfPstatesEnabled, 811 smu_dpm_clks.dpm_clks->MinGfxClk, 812 smu_dpm_clks.dpm_clks->MaxGfxClk); 813 for (i = 0; i < smu_dpm_clks.dpm_clks->NumDcfClkLevelsEnabled; i++) { 814 DC_LOG_SMU("smu_dpm_clks.dpm_clks->DcfClocks[%d] = %d\n", 815 i, 816 smu_dpm_clks.dpm_clks->DcfClocks[i]); 817 } 818 for (i = 0; i < smu_dpm_clks.dpm_clks->NumDispClkLevelsEnabled; i++) { 819 DC_LOG_SMU("smu_dpm_clks.dpm_clks->DispClocks[%d] = %d\n", 820 i, smu_dpm_clks.dpm_clks->DispClocks[i]); 821 } 822 for (i = 0; i < smu_dpm_clks.dpm_clks->NumSocClkLevelsEnabled; i++) { 823 DC_LOG_SMU("smu_dpm_clks.dpm_clks->SocClocks[%d] = %d\n", 824 i, smu_dpm_clks.dpm_clks->SocClocks[i]); 825 } 826 for (i = 0; i < NUM_SOC_VOLTAGE_LEVELS; i++) 827 DC_LOG_SMU("smu_dpm_clks.dpm_clks->SocVoltage[%d] = %d\n", 828 i, smu_dpm_clks.dpm_clks->SocVoltage[i]); 829 830 for (i = 0; i < NUM_DF_PSTATE_LEVELS; i++) { 831 DC_LOG_SMU("smu_dpm_clks.dpm_clks.DfPstateTable[%d].FClk = %d\n" 832 "smu_dpm_clks.dpm_clks->DfPstateTable[%d].MemClk= %d\n" 833 "smu_dpm_clks.dpm_clks->DfPstateTable[%d].Voltage = %d\n", 834 i, smu_dpm_clks.dpm_clks->DfPstateTable[i].FClk, 835 i, smu_dpm_clks.dpm_clks->DfPstateTable[i].MemClk, 836 i, smu_dpm_clks.dpm_clks->DfPstateTable[i].Voltage); 837 } 838 839 if (ctx->dc_bios && ctx->dc_bios->integrated_info && ctx->dc->config.use_default_clock_table == false) { 840 dcn314_clk_mgr_helper_populate_bw_params( 841 &clk_mgr->base, 842 ctx->dc_bios->integrated_info, 843 smu_dpm_clks.dpm_clks); 844 } 845 } 846 847 if (smu_dpm_clks.dpm_clks && smu_dpm_clks.mc_address.quad_part != 0) 848 dm_helpers_free_gpu_mem(clk_mgr->base.base.ctx, DC_MEM_ALLOC_TYPE_FRAME_BUFFER, 849 smu_dpm_clks.dpm_clks); 850 } 851 852 void dcn314_clk_mgr_destroy(struct clk_mgr_internal *clk_mgr_int) 853 { 854 struct clk_mgr_dcn314 *clk_mgr = TO_CLK_MGR_DCN314(clk_mgr_int); 855 856 if (clk_mgr->smu_wm_set.wm_set && clk_mgr->smu_wm_set.mc_address.quad_part != 0) 857 dm_helpers_free_gpu_mem(clk_mgr_int->base.ctx, DC_MEM_ALLOC_TYPE_FRAME_BUFFER, 858 clk_mgr->smu_wm_set.wm_set); 859 } 860