1 /*
2  * Copyright 2018 Advanced Micro Devices, Inc.
3  *
4  * Permission is hereby granted, free of charge, to any person obtaining a
5  * copy of this software and associated documentation files (the "Software"),
6  * to deal in the Software without restriction, including without limitation
7  * the rights to use, copy, modify, merge, publish, distribute, sublicense,
8  * and/or sell copies of the Software, and to permit persons to whom the
9  * Software is furnished to do so, subject to the following conditions:
10  *
11  * The above copyright notice and this permission notice shall be included in
12  * all copies or substantial portions of the Software.
13  *
14  * THE SOFTWARE IS PROVIDED "AS IS", WITHOUT WARRANTY OF ANY KIND, EXPRESS OR
15  * IMPLIED, INCLUDING BUT NOT LIMITED TO THE WARRANTIES OF MERCHANTABILITY,
16  * FITNESS FOR A PARTICULAR PURPOSE AND NONINFRINGEMENT.  IN NO EVENT SHALL
17  * THE COPYRIGHT HOLDER(S) OR AUTHOR(S) BE LIABLE FOR ANY CLAIM, DAMAGES OR
18  * OTHER LIABILITY, WHETHER IN AN ACTION OF CONTRACT, TORT OR OTHERWISE,
19  * ARISING FROM, OUT OF OR IN CONNECTION WITH THE SOFTWARE OR THE USE OR
20  * OTHER DEALINGS IN THE SOFTWARE.
21  *
22  * Authors: AMD
23  *
24  */
25 
26 #ifndef DAL_DC_31_SMU_H_
27 #define DAL_DC_31_SMU_H_
28 
29 #ifndef PMFW_DRIVER_IF_H
30 #define PMFW_DRIVER_IF_H
31 #define PMFW_DRIVER_IF_VERSION 4
32 
33 typedef struct {
34   int32_t value;
35   uint32_t numFractionalBits;
36 } FloatInIntFormat_t;
37 
38 typedef enum {
39   DSPCLK_DCFCLK = 0,
40   DSPCLK_DISPCLK,
41   DSPCLK_PIXCLK,
42   DSPCLK_PHYCLK,
43   DSPCLK_COUNT,
44 } DSPCLK_e;
45 
46 typedef struct {
47   uint16_t Freq; // in MHz
48   uint16_t Vid;  // min voltage in SVI3 VID
49 } DisplayClockTable_t;
50 
51 typedef struct {
52   uint16_t MinClock; // This is either DCFCLK or SOCCLK (in MHz)
53   uint16_t MaxClock; // This is either DCFCLK or SOCCLK (in MHz)
54   uint16_t MinMclk;
55   uint16_t MaxMclk;
56 
57   uint8_t  WmSetting;
58   uint8_t  WmType;  // Used for normal pstate change or memory retraining
59   uint8_t  Padding[2];
60 } WatermarkRowGeneric_t;
61 
62 #define NUM_WM_RANGES 4
63 #define WM_PSTATE_CHG 0
64 #define WM_RETRAINING 1
65 
66 typedef enum {
67   WM_SOCCLK = 0,
68   WM_DCFCLK,
69   WM_COUNT,
70 } WM_CLOCK_e;
71 
72 typedef struct {
73   // Watermarks
74   WatermarkRowGeneric_t WatermarkRow[WM_COUNT][NUM_WM_RANGES];
75 
76   uint32_t MmHubPadding[7]; // SMU internal use
77 } Watermarks_t;
78 
79 typedef enum {
80   CUSTOM_DPM_SETTING_GFXCLK,
81   CUSTOM_DPM_SETTING_CCLK,
82   CUSTOM_DPM_SETTING_FCLK_CCX,
83   CUSTOM_DPM_SETTING_FCLK_GFX,
84   CUSTOM_DPM_SETTING_FCLK_STALLS,
85   CUSTOM_DPM_SETTING_LCLK,
86   CUSTOM_DPM_SETTING_COUNT,
87 } CUSTOM_DPM_SETTING_e;
88 
89 typedef struct {
90   uint8_t             ActiveHystLimit;
91   uint8_t             IdleHystLimit;
92   uint8_t             FPS;
93   uint8_t             MinActiveFreqType;
94   FloatInIntFormat_t  MinActiveFreq;
95   FloatInIntFormat_t  PD_Data_limit;
96   FloatInIntFormat_t  PD_Data_time_constant;
97   FloatInIntFormat_t  PD_Data_error_coeff;
98   FloatInIntFormat_t  PD_Data_error_rate_coeff;
99 } DpmActivityMonitorCoeffExt_t;
100 
101 typedef struct {
102   DpmActivityMonitorCoeffExt_t DpmActivityMonitorCoeff[CUSTOM_DPM_SETTING_COUNT];
103 } CustomDpmSettings_t;
104 
105 #define NUM_DCFCLK_DPM_LEVELS   8
106 #define NUM_DISPCLK_DPM_LEVELS  8
107 #define NUM_DPPCLK_DPM_LEVELS   8
108 #define NUM_SOCCLK_DPM_LEVELS   8
109 #define NUM_VCN_DPM_LEVELS      8
110 #define NUM_SOC_VOLTAGE_LEVELS  8
111 #define NUM_DF_PSTATE_LEVELS    4
112 
113 typedef enum{
114   WCK_RATIO_1_1 = 0,  // DDR5, Wck:ck is always 1:1;
115   WCK_RATIO_1_2,
116   WCK_RATIO_1_4,
117   WCK_RATIO_MAX
118 } WCK_RATIO_e;
119 
120 typedef struct {
121   uint32_t FClk;
122   uint32_t MemClk;
123   uint32_t Voltage;
124   uint8_t  WckRatio;
125   uint8_t  Spare[3];
126 } DfPstateTable_t;
127 
128 //Freq in MHz
129 //Voltage in milli volts with 2 fractional bits
130 typedef struct {
131   uint32_t DcfClocks[NUM_DCFCLK_DPM_LEVELS];
132   uint32_t DispClocks[NUM_DISPCLK_DPM_LEVELS];
133   uint32_t DppClocks[NUM_DPPCLK_DPM_LEVELS];
134   uint32_t SocClocks[NUM_SOCCLK_DPM_LEVELS];
135   uint32_t VClocks[NUM_VCN_DPM_LEVELS];
136   uint32_t DClocks[NUM_VCN_DPM_LEVELS];
137   uint32_t SocVoltage[NUM_SOC_VOLTAGE_LEVELS];
138   DfPstateTable_t DfPstateTable[NUM_DF_PSTATE_LEVELS];
139 
140   uint8_t  NumDcfClkLevelsEnabled;
141   uint8_t  NumDispClkLevelsEnabled; //Applies to both Dispclk and Dppclk
142   uint8_t  NumSocClkLevelsEnabled;
143   uint8_t  VcnClkLevelsEnabled;     //Applies to both Vclk and Dclk
144   uint8_t  NumDfPstatesEnabled;
145   uint8_t  spare[3];
146 
147   uint32_t MinGfxClk;
148   uint32_t MaxGfxClk;
149 } DpmClocks_t;
150 
151 
152 // Throttler Status Bitmask
153 #define THROTTLER_STATUS_BIT_SPL            0
154 #define THROTTLER_STATUS_BIT_FPPT           1
155 #define THROTTLER_STATUS_BIT_SPPT           2
156 #define THROTTLER_STATUS_BIT_SPPT_APU       3
157 #define THROTTLER_STATUS_BIT_THM_CORE       4
158 #define THROTTLER_STATUS_BIT_THM_GFX        5
159 #define THROTTLER_STATUS_BIT_THM_SOC        6
160 #define THROTTLER_STATUS_BIT_TDC_VDD        7
161 #define THROTTLER_STATUS_BIT_TDC_SOC        8
162 #define THROTTLER_STATUS_BIT_PROCHOT_CPU    9
163 #define THROTTLER_STATUS_BIT_PROCHOT_GFX   10
164 #define THROTTLER_STATUS_BIT_EDC_CPU       11
165 #define THROTTLER_STATUS_BIT_EDC_GFX       12
166 
167 typedef struct {
168   uint16_t GfxclkFrequency;             //[MHz]
169   uint16_t SocclkFrequency;             //[MHz]
170   uint16_t VclkFrequency;               //[MHz]
171   uint16_t DclkFrequency;               //[MHz]
172   uint16_t MemclkFrequency;             //[MHz]
173   uint16_t spare;
174 
175   uint16_t GfxActivity;                 //[centi]
176   uint16_t UvdActivity;                 //[centi]
177 
178   uint16_t Voltage[2];                  //[mV] indices: VDDCR_VDD, VDDCR_SOC
179   uint16_t Current[2];                  //[mA] indices: VDDCR_VDD, VDDCR_SOC
180   uint16_t Power[2];                    //[mW] indices: VDDCR_VDD, VDDCR_SOC
181 
182   //3rd party tools in Windows need this info in the case of APUs
183   uint16_t CoreFrequency[8];            //[MHz]
184   uint16_t CorePower[8];                //[mW]
185   uint16_t CoreTemperature[8];          //[centi-Celsius]
186   uint16_t L3Frequency;                 //[MHz]
187   uint16_t L3Temperature;               //[centi-Celsius]
188 
189   uint16_t GfxTemperature;              //[centi-Celsius]
190   uint16_t SocTemperature;              //[centi-Celsius]
191   uint16_t ThrottlerStatus;
192 
193   uint16_t CurrentSocketPower;          //[mW]
194   uint16_t StapmOriginalLimit;          //[W]
195   uint16_t StapmCurrentLimit;           //[W]
196   uint16_t ApuPower;                    //[W]
197   uint16_t dGpuPower;                   //[W]
198 
199   uint16_t VddTdcValue;                 //[mA]
200   uint16_t SocTdcValue;                 //[mA]
201   uint16_t VddEdcValue;                 //[mA]
202   uint16_t SocEdcValue;                 //[mA]
203 
204   uint16_t InfrastructureCpuMaxFreq;    //[MHz]
205   uint16_t InfrastructureGfxMaxFreq;    //[MHz]
206 } SmuMetrics_t;
207 
208 
209 // Workload bits
210 #define WORKLOAD_PPLIB_FULL_SCREEN_3D_BIT 0
211 #define WORKLOAD_PPLIB_VIDEO_BIT          2
212 #define WORKLOAD_PPLIB_VR_BIT             3
213 #define WORKLOAD_PPLIB_COMPUTE_BIT        4
214 #define WORKLOAD_PPLIB_CUSTOM_BIT         5
215 #define WORKLOAD_PPLIB_COUNT              6
216 
217 #define TABLE_BIOS_IF            0 // Called by BIOS
218 #define TABLE_WATERMARKS         1 // Called by DAL through VBIOS
219 #define TABLE_CUSTOM_DPM         2 // Called by Driver
220 #define TABLE_SPARE1             3
221 #define TABLE_DPMCLOCKS          4 // Called by Driver
222 #define TABLE_MOMENTARY_PM       5 // Called by Tools
223 #define TABLE_MODERN_STDBY       6 // Called by Tools for Modern Standby Log
224 #define TABLE_SMU_METRICS        7 // Called by Driver
225 #define TABLE_COUNT              8
226 
227 #endif
228 
229 struct dcn31_watermarks {
230   // Watermarks
231   WatermarkRowGeneric_t WatermarkRow[WM_COUNT][NUM_WM_RANGES];
232 
233   uint32_t MmHubPadding[7]; // SMU internal use
234 };
235 
236 struct dcn31_smu_dpm_clks {
237 	DpmClocks_t *dpm_clks;
238 	union large_integer mc_address;
239 };
240 
241 /* TODO: taken from vgh, may not be correct */
242 struct display_idle_optimization {
243 	unsigned int df_request_disabled : 1;
244 	unsigned int phy_ref_clk_off     : 1;
245 	unsigned int s0i2_rdy            : 1;
246 	unsigned int reserved            : 29;
247 };
248 
249 union display_idle_optimization_u {
250 	struct display_idle_optimization idle_info;
251 	uint32_t data;
252 };
253 
254 int dcn31_smu_get_smu_version(struct clk_mgr_internal *clk_mgr);
255 int dcn31_smu_set_dispclk(struct clk_mgr_internal *clk_mgr, int requested_dispclk_khz);
256 int dcn31_smu_set_dprefclk(struct clk_mgr_internal *clk_mgr);
257 int dcn31_smu_set_hard_min_dcfclk(struct clk_mgr_internal *clk_mgr, int requested_dcfclk_khz);
258 int dcn31_smu_set_min_deep_sleep_dcfclk(struct clk_mgr_internal *clk_mgr, int requested_min_ds_dcfclk_khz);
259 int dcn31_smu_set_dppclk(struct clk_mgr_internal *clk_mgr, int requested_dpp_khz);
260 void dcn31_smu_set_display_idle_optimization(struct clk_mgr_internal *clk_mgr, uint32_t idle_info);
261 void dcn31_smu_enable_phy_refclk_pwrdwn(struct clk_mgr_internal *clk_mgr, bool enable);
262 void dcn31_smu_enable_pme_wa(struct clk_mgr_internal *clk_mgr);
263 void dcn31_smu_set_dram_addr_high(struct clk_mgr_internal *clk_mgr, uint32_t addr_high);
264 void dcn31_smu_set_dram_addr_low(struct clk_mgr_internal *clk_mgr, uint32_t addr_low);
265 void dcn31_smu_transfer_dpm_table_smu_2_dram(struct clk_mgr_internal *clk_mgr);
266 void dcn31_smu_transfer_wm_table_dram_2_smu(struct clk_mgr_internal *clk_mgr);
267 
268 void dcn31_smu_set_Z9_support(struct clk_mgr_internal *clk_mgr, bool support);
269 void dcn31_smu_set_dtbclk(struct clk_mgr_internal *clk_mgr, bool enable);
270 
271 #endif /* DAL_DC_31_SMU_H_ */
272