1 /* 2 * Copyright 2012-16 Advanced Micro Devices, Inc. 3 * 4 * Permission is hereby granted, free of charge, to any person obtaining a 5 * copy of this software and associated documentation files (the "Software"), 6 * to deal in the Software without restriction, including without limitation 7 * the rights to use, copy, modify, merge, publish, distribute, sublicense, 8 * and/or sell copies of the Software, and to permit persons to whom the 9 * Software is furnished to do so, subject to the following conditions: 10 * 11 * The above copyright notice and this permission notice shall be included in 12 * all copies or substantial portions of the Software. 13 * 14 * THE SOFTWARE IS PROVIDED "AS IS", WITHOUT WARRANTY OF ANY KIND, EXPRESS OR 15 * IMPLIED, INCLUDING BUT NOT LIMITED TO THE WARRANTIES OF MERCHANTABILITY, 16 * FITNESS FOR A PARTICULAR PURPOSE AND NONINFRINGEMENT. IN NO EVENT SHALL 17 * THE COPYRIGHT HOLDER(S) OR AUTHOR(S) BE LIABLE FOR ANY CLAIM, DAMAGES OR 18 * OTHER LIABILITY, WHETHER IN AN ACTION OF CONTRACT, TORT OR OTHERWISE, 19 * ARISING FROM, OUT OF OR IN CONNECTION WITH THE SOFTWARE OR THE USE OR 20 * OTHER DEALINGS IN THE SOFTWARE. 21 * 22 * Authors: AMD 23 * 24 */ 25 26 #include <linux/delay.h> 27 #include "core_types.h" 28 #include "clk_mgr_internal.h" 29 #include "reg_helper.h" 30 #include "dm_helpers.h" 31 #include "dcn31_smu.h" 32 33 #include "yellow_carp_offset.h" 34 #include "mp/mp_13_0_2_offset.h" 35 #include "mp/mp_13_0_2_sh_mask.h" 36 37 #define REG(reg_name) \ 38 (MP0_BASE.instance[0].segment[reg ## reg_name ## _BASE_IDX] + reg ## reg_name) 39 40 #define FN(reg_name, field) \ 41 FD(reg_name##__##field) 42 43 #define VBIOSSMC_MSG_TestMessage 0x1 44 #define VBIOSSMC_MSG_GetSmuVersion 0x2 45 #define VBIOSSMC_MSG_PowerUpGfx 0x3 46 #define VBIOSSMC_MSG_SetDispclkFreq 0x4 47 #define VBIOSSMC_MSG_SetDprefclkFreq 0x5 //Not used. DPRef is constant 48 #define VBIOSSMC_MSG_SetDppclkFreq 0x6 49 #define VBIOSSMC_MSG_SetHardMinDcfclkByFreq 0x7 50 #define VBIOSSMC_MSG_SetMinDeepSleepDcfclk 0x8 51 #define VBIOSSMC_MSG_SetPhyclkVoltageByFreq 0x9 //Keep it in case VMIN dees not support phy clk 52 #define VBIOSSMC_MSG_GetFclkFrequency 0xA 53 #define VBIOSSMC_MSG_SetDisplayCount 0xB //Not used anymore 54 #define VBIOSSMC_MSG_EnableTmdp48MHzRefclkPwrDown 0xC //Not used anymore 55 #define VBIOSSMC_MSG_UpdatePmeRestore 0xD 56 #define VBIOSSMC_MSG_SetVbiosDramAddrHigh 0xE //Used for WM table txfr 57 #define VBIOSSMC_MSG_SetVbiosDramAddrLow 0xF 58 #define VBIOSSMC_MSG_TransferTableSmu2Dram 0x10 59 #define VBIOSSMC_MSG_TransferTableDram2Smu 0x11 60 #define VBIOSSMC_MSG_SetDisplayIdleOptimizations 0x12 61 #define VBIOSSMC_MSG_GetDprefclkFreq 0x13 62 #define VBIOSSMC_MSG_GetDtbclkFreq 0x14 63 #define VBIOSSMC_MSG_AllowZstatesEntry 0x15 64 #define VBIOSSMC_MSG_DisallowZstatesEntry 0x16 65 #define VBIOSSMC_MSG_SetDtbClk 0x17 66 #define VBIOSSMC_Message_Count 0x18 67 68 #define VBIOSSMC_Status_BUSY 0x0 69 #define VBIOSSMC_Result_OK 0x1 70 #define VBIOSSMC_Result_Failed 0xFF 71 #define VBIOSSMC_Result_UnknownCmd 0xFE 72 #define VBIOSSMC_Result_CmdRejectedPrereq 0xFD 73 #define VBIOSSMC_Result_CmdRejectedBusy 0xFC 74 75 /* 76 * Function to be used instead of REG_WAIT macro because the wait ends when 77 * the register is NOT EQUAL to zero, and because the translation in msg_if.h 78 * won't work with REG_WAIT. 79 */ 80 static uint32_t dcn31_smu_wait_for_response(struct clk_mgr_internal *clk_mgr, unsigned int delay_us, unsigned int max_retries) 81 { 82 uint32_t res_val = VBIOSSMC_Status_BUSY; 83 84 do { 85 res_val = REG_READ(MP1_SMN_C2PMSG_91); 86 if (res_val != VBIOSSMC_Status_BUSY) 87 break; 88 89 if (delay_us >= 1000) 90 msleep(delay_us/1000); 91 else if (delay_us > 0) 92 udelay(delay_us); 93 } while (max_retries--); 94 95 return res_val; 96 } 97 98 static int dcn31_smu_send_msg_with_param(struct clk_mgr_internal *clk_mgr, 99 unsigned int msg_id, 100 unsigned int param) 101 { 102 uint32_t result; 103 104 result = dcn31_smu_wait_for_response(clk_mgr, 10, 200000); 105 ASSERT(result == VBIOSSMC_Result_OK); 106 107 if (result == VBIOSSMC_Status_BUSY) { 108 return -1; 109 } 110 111 /* First clear response register */ 112 REG_WRITE(MP1_SMN_C2PMSG_91, VBIOSSMC_Status_BUSY); 113 114 /* Set the parameter register for the SMU message, unit is Mhz */ 115 REG_WRITE(MP1_SMN_C2PMSG_83, param); 116 117 /* Trigger the message transaction by writing the message ID */ 118 REG_WRITE(MP1_SMN_C2PMSG_67, msg_id); 119 120 result = dcn31_smu_wait_for_response(clk_mgr, 10, 200000); 121 122 if (result == VBIOSSMC_Result_Failed) { 123 ASSERT(0); 124 REG_WRITE(MP1_SMN_C2PMSG_91, VBIOSSMC_Result_OK); 125 return -1; 126 } 127 128 if (IS_SMU_TIMEOUT(result)) { 129 ASSERT(0); 130 dm_helpers_smu_timeout(CTX, msg_id, param, 10 * 200000); 131 } 132 133 return REG_READ(MP1_SMN_C2PMSG_83); 134 } 135 136 int dcn31_smu_get_smu_version(struct clk_mgr_internal *clk_mgr) 137 { 138 return dcn31_smu_send_msg_with_param( 139 clk_mgr, 140 VBIOSSMC_MSG_GetSmuVersion, 141 0); 142 } 143 144 145 int dcn31_smu_set_dispclk(struct clk_mgr_internal *clk_mgr, int requested_dispclk_khz) 146 { 147 int actual_dispclk_set_mhz = -1; 148 149 if (!clk_mgr->smu_present) 150 return requested_dispclk_khz; 151 152 /* Unit of SMU msg parameter is Mhz */ 153 actual_dispclk_set_mhz = dcn31_smu_send_msg_with_param( 154 clk_mgr, 155 VBIOSSMC_MSG_SetDispclkFreq, 156 khz_to_mhz_ceil(requested_dispclk_khz)); 157 158 return actual_dispclk_set_mhz * 1000; 159 } 160 161 int dcn31_smu_set_dprefclk(struct clk_mgr_internal *clk_mgr) 162 { 163 int actual_dprefclk_set_mhz = -1; 164 165 if (!clk_mgr->smu_present) 166 return clk_mgr->base.dprefclk_khz; 167 168 actual_dprefclk_set_mhz = dcn31_smu_send_msg_with_param( 169 clk_mgr, 170 VBIOSSMC_MSG_SetDprefclkFreq, 171 khz_to_mhz_ceil(clk_mgr->base.dprefclk_khz)); 172 173 /* TODO: add code for programing DP DTO, currently this is down by command table */ 174 175 return actual_dprefclk_set_mhz * 1000; 176 } 177 178 int dcn31_smu_set_hard_min_dcfclk(struct clk_mgr_internal *clk_mgr, int requested_dcfclk_khz) 179 { 180 int actual_dcfclk_set_mhz = -1; 181 182 if (!clk_mgr->base.ctx->dc->debug.pstate_enabled) 183 return -1; 184 185 if (!clk_mgr->smu_present) 186 return requested_dcfclk_khz; 187 188 actual_dcfclk_set_mhz = dcn31_smu_send_msg_with_param( 189 clk_mgr, 190 VBIOSSMC_MSG_SetHardMinDcfclkByFreq, 191 khz_to_mhz_ceil(requested_dcfclk_khz)); 192 193 return actual_dcfclk_set_mhz * 1000; 194 } 195 196 int dcn31_smu_set_min_deep_sleep_dcfclk(struct clk_mgr_internal *clk_mgr, int requested_min_ds_dcfclk_khz) 197 { 198 int actual_min_ds_dcfclk_mhz = -1; 199 200 if (!clk_mgr->base.ctx->dc->debug.pstate_enabled) 201 return -1; 202 203 if (!clk_mgr->smu_present) 204 return requested_min_ds_dcfclk_khz; 205 206 actual_min_ds_dcfclk_mhz = dcn31_smu_send_msg_with_param( 207 clk_mgr, 208 VBIOSSMC_MSG_SetMinDeepSleepDcfclk, 209 khz_to_mhz_ceil(requested_min_ds_dcfclk_khz)); 210 211 return actual_min_ds_dcfclk_mhz * 1000; 212 } 213 214 int dcn31_smu_set_dppclk(struct clk_mgr_internal *clk_mgr, int requested_dpp_khz) 215 { 216 int actual_dppclk_set_mhz = -1; 217 218 if (!clk_mgr->smu_present) 219 return requested_dpp_khz; 220 221 actual_dppclk_set_mhz = dcn31_smu_send_msg_with_param( 222 clk_mgr, 223 VBIOSSMC_MSG_SetDppclkFreq, 224 khz_to_mhz_ceil(requested_dpp_khz)); 225 226 return actual_dppclk_set_mhz * 1000; 227 } 228 229 void dcn31_smu_set_display_idle_optimization(struct clk_mgr_internal *clk_mgr, uint32_t idle_info) 230 { 231 if (!clk_mgr->base.ctx->dc->debug.pstate_enabled) 232 return; 233 234 if (!clk_mgr->smu_present) 235 return; 236 237 //TODO: Work with smu team to define optimization options. 238 dcn31_smu_send_msg_with_param( 239 clk_mgr, 240 VBIOSSMC_MSG_SetDisplayIdleOptimizations, 241 idle_info); 242 } 243 244 void dcn31_smu_enable_phy_refclk_pwrdwn(struct clk_mgr_internal *clk_mgr, bool enable) 245 { 246 union display_idle_optimization_u idle_info = { 0 }; 247 248 if (!clk_mgr->smu_present) 249 return; 250 251 if (enable) { 252 idle_info.idle_info.df_request_disabled = 1; 253 idle_info.idle_info.phy_ref_clk_off = 1; 254 } 255 256 dcn31_smu_send_msg_with_param( 257 clk_mgr, 258 VBIOSSMC_MSG_SetDisplayIdleOptimizations, 259 idle_info.data); 260 } 261 262 void dcn31_smu_enable_pme_wa(struct clk_mgr_internal *clk_mgr) 263 { 264 if (!clk_mgr->smu_present) 265 return; 266 267 dcn31_smu_send_msg_with_param( 268 clk_mgr, 269 VBIOSSMC_MSG_UpdatePmeRestore, 270 0); 271 } 272 273 void dcn31_smu_set_dram_addr_high(struct clk_mgr_internal *clk_mgr, uint32_t addr_high) 274 { 275 if (!clk_mgr->smu_present) 276 return; 277 278 dcn31_smu_send_msg_with_param(clk_mgr, 279 VBIOSSMC_MSG_SetVbiosDramAddrHigh, addr_high); 280 } 281 282 void dcn31_smu_set_dram_addr_low(struct clk_mgr_internal *clk_mgr, uint32_t addr_low) 283 { 284 if (!clk_mgr->smu_present) 285 return; 286 287 dcn31_smu_send_msg_with_param(clk_mgr, 288 VBIOSSMC_MSG_SetVbiosDramAddrLow, addr_low); 289 } 290 291 void dcn31_smu_transfer_dpm_table_smu_2_dram(struct clk_mgr_internal *clk_mgr) 292 { 293 if (!clk_mgr->smu_present) 294 return; 295 296 dcn31_smu_send_msg_with_param(clk_mgr, 297 VBIOSSMC_MSG_TransferTableSmu2Dram, TABLE_DPMCLOCKS); 298 } 299 300 void dcn31_smu_transfer_wm_table_dram_2_smu(struct clk_mgr_internal *clk_mgr) 301 { 302 if (!clk_mgr->smu_present) 303 return; 304 305 dcn31_smu_send_msg_with_param(clk_mgr, 306 VBIOSSMC_MSG_TransferTableDram2Smu, TABLE_WATERMARKS); 307 } 308 309 void dcn31_smu_set_Z9_support(struct clk_mgr_internal *clk_mgr, bool support) 310 { 311 //TODO: Work with smu team to define optimization options. 312 unsigned int msg_id; 313 314 if (!clk_mgr->smu_present) 315 return; 316 317 if (support) 318 msg_id = VBIOSSMC_MSG_AllowZstatesEntry; 319 else 320 msg_id = VBIOSSMC_MSG_DisallowZstatesEntry; 321 322 dcn31_smu_send_msg_with_param( 323 clk_mgr, 324 msg_id, 325 0); 326 327 } 328 329 /* Arg = 1: Turn DTB on; 0: Turn DTB CLK OFF. when it is on, it is 600MHZ */ 330 void dcn31_smu_set_dtbclk(struct clk_mgr_internal *clk_mgr, bool enable) 331 { 332 if (!clk_mgr->smu_present) 333 return; 334 335 dcn31_smu_send_msg_with_param( 336 clk_mgr, 337 VBIOSSMC_MSG_SetDtbClk, 338 enable); 339 } 340