1*118a3315SNicholas Kazlauskas /* 2*118a3315SNicholas Kazlauskas * Copyright 2019 Advanced Micro Devices, Inc. 3*118a3315SNicholas Kazlauskas * 4*118a3315SNicholas Kazlauskas * Permission is hereby granted, free of charge, to any person obtaining a 5*118a3315SNicholas Kazlauskas * copy of this software and associated documentation files (the "Software"), 6*118a3315SNicholas Kazlauskas * to deal in the Software without restriction, including without limitation 7*118a3315SNicholas Kazlauskas * the rights to use, copy, modify, merge, publish, distribute, sublicense, 8*118a3315SNicholas Kazlauskas * and/or sell copies of the Software, and to permit persons to whom the 9*118a3315SNicholas Kazlauskas * Software is furnished to do so, subject to the following conditions: 10*118a3315SNicholas Kazlauskas * 11*118a3315SNicholas Kazlauskas * The above copyright notice and this permission notice shall be included in 12*118a3315SNicholas Kazlauskas * all copies or substantial portions of the Software. 13*118a3315SNicholas Kazlauskas * 14*118a3315SNicholas Kazlauskas * THE SOFTWARE IS PROVIDED "AS IS", WITHOUT WARRANTY OF ANY KIND, EXPRESS OR 15*118a3315SNicholas Kazlauskas * IMPLIED, INCLUDING BUT NOT LIMITED TO THE WARRANTIES OF MERCHANTABILITY, 16*118a3315SNicholas Kazlauskas * FITNESS FOR A PARTICULAR PURPOSE AND NONINFRINGEMENT. IN NO EVENT SHALL 17*118a3315SNicholas Kazlauskas * THE COPYRIGHT HOLDER(S) OR AUTHOR(S) BE LIABLE FOR ANY CLAIM, DAMAGES OR 18*118a3315SNicholas Kazlauskas * OTHER LIABILITY, WHETHER IN AN ACTION OF CONTRACT, TORT OR OTHERWISE, 19*118a3315SNicholas Kazlauskas * ARISING FROM, OUT OF OR IN CONNECTION WITH THE SOFTWARE OR THE USE OR 20*118a3315SNicholas Kazlauskas * OTHER DEALINGS IN THE SOFTWARE. 21*118a3315SNicholas Kazlauskas * 22*118a3315SNicholas Kazlauskas * Authors: AMD 23*118a3315SNicholas Kazlauskas * 24*118a3315SNicholas Kazlauskas */ 25*118a3315SNicholas Kazlauskas 26*118a3315SNicholas Kazlauskas #ifndef __DCN31_CLK_MGR_H__ 27*118a3315SNicholas Kazlauskas #define __DCN31_CLK_MGR_H__ 28*118a3315SNicholas Kazlauskas #include "clk_mgr_internal.h" 29*118a3315SNicholas Kazlauskas 30*118a3315SNicholas Kazlauskas //CLK1_CLK_PLL_REQ 31*118a3315SNicholas Kazlauskas #ifndef CLK11_CLK1_CLK_PLL_REQ__FbMult_int__SHIFT 32*118a3315SNicholas Kazlauskas #define CLK11_CLK1_CLK_PLL_REQ__FbMult_int__SHIFT 0x0 33*118a3315SNicholas Kazlauskas #define CLK11_CLK1_CLK_PLL_REQ__PllSpineDiv__SHIFT 0xc 34*118a3315SNicholas Kazlauskas #define CLK11_CLK1_CLK_PLL_REQ__FbMult_frac__SHIFT 0x10 35*118a3315SNicholas Kazlauskas #define CLK11_CLK1_CLK_PLL_REQ__FbMult_int_MASK 0x000001FFL 36*118a3315SNicholas Kazlauskas #define CLK11_CLK1_CLK_PLL_REQ__PllSpineDiv_MASK 0x0000F000L 37*118a3315SNicholas Kazlauskas #define CLK11_CLK1_CLK_PLL_REQ__FbMult_frac_MASK 0xFFFF0000L 38*118a3315SNicholas Kazlauskas //CLK1_CLK0_DFS_CNTL 39*118a3315SNicholas Kazlauskas #define CLK11_CLK1_CLK0_DFS_CNTL__CLK0_DIVIDER__SHIFT 0x0 40*118a3315SNicholas Kazlauskas #define CLK11_CLK1_CLK0_DFS_CNTL__CLK0_DIVIDER_MASK 0x0000007FL 41*118a3315SNicholas Kazlauskas /*DPREF clock related*/ 42*118a3315SNicholas Kazlauskas #define CLK0_CLK3_DFS_CNTL__CLK3_DIVIDER__SHIFT 0x0 43*118a3315SNicholas Kazlauskas #define CLK0_CLK3_DFS_CNTL__CLK3_DIVIDER_MASK 0x0000007FL 44*118a3315SNicholas Kazlauskas #define CLK1_CLK3_DFS_CNTL__CLK3_DIVIDER__SHIFT 0x0 45*118a3315SNicholas Kazlauskas #define CLK1_CLK3_DFS_CNTL__CLK3_DIVIDER_MASK 0x0000007FL 46*118a3315SNicholas Kazlauskas #define CLK2_CLK3_DFS_CNTL__CLK3_DIVIDER__SHIFT 0x0 47*118a3315SNicholas Kazlauskas #define CLK2_CLK3_DFS_CNTL__CLK3_DIVIDER_MASK 0x0000007FL 48*118a3315SNicholas Kazlauskas #define CLK3_CLK3_DFS_CNTL__CLK3_DIVIDER__SHIFT 0x0 49*118a3315SNicholas Kazlauskas #define CLK3_CLK3_DFS_CNTL__CLK3_DIVIDER_MASK 0x0000007FL 50*118a3315SNicholas Kazlauskas 51*118a3315SNicholas Kazlauskas //CLK3_0_CLK3_CLK_PLL_REQ 52*118a3315SNicholas Kazlauskas #define CLK3_0_CLK3_CLK_PLL_REQ__FbMult_int__SHIFT 0x0 53*118a3315SNicholas Kazlauskas #define CLK3_0_CLK3_CLK_PLL_REQ__PllSpineDiv__SHIFT 0xc 54*118a3315SNicholas Kazlauskas #define CLK3_0_CLK3_CLK_PLL_REQ__FbMult_frac__SHIFT 0x10 55*118a3315SNicholas Kazlauskas #define CLK3_0_CLK3_CLK_PLL_REQ__FbMult_int_MASK 0x000001FFL 56*118a3315SNicholas Kazlauskas #define CLK3_0_CLK3_CLK_PLL_REQ__PllSpineDiv_MASK 0x0000F000L 57*118a3315SNicholas Kazlauskas #define CLK3_0_CLK3_CLK_PLL_REQ__FbMult_frac_MASK 0xFFFF0000L 58*118a3315SNicholas Kazlauskas 59*118a3315SNicholas Kazlauskas #define mmCLK0_CLK3_DFS_CNTL 0x16C60 60*118a3315SNicholas Kazlauskas #define mmCLK00_CLK0_CLK3_DFS_CNTL 0x16C60 61*118a3315SNicholas Kazlauskas #define mmCLK01_CLK0_CLK3_DFS_CNTL 0x16E60 62*118a3315SNicholas Kazlauskas #define mmCLK02_CLK0_CLK3_DFS_CNTL 0x17060 63*118a3315SNicholas Kazlauskas #define mmCLK03_CLK0_CLK3_DFS_CNTL 0x17260 64*118a3315SNicholas Kazlauskas 65*118a3315SNicholas Kazlauskas #define mmCLK0_CLK_PLL_REQ 0x16C10 66*118a3315SNicholas Kazlauskas #define mmCLK00_CLK0_CLK_PLL_REQ 0x16C10 67*118a3315SNicholas Kazlauskas #define mmCLK01_CLK0_CLK_PLL_REQ 0x16E10 68*118a3315SNicholas Kazlauskas #define mmCLK02_CLK0_CLK_PLL_REQ 0x17010 69*118a3315SNicholas Kazlauskas #define mmCLK03_CLK0_CLK_PLL_REQ 0x17210 70*118a3315SNicholas Kazlauskas 71*118a3315SNicholas Kazlauskas #define mmCLK1_CLK_PLL_REQ 0x1B00D 72*118a3315SNicholas Kazlauskas #define mmCLK10_CLK1_CLK_PLL_REQ 0x1B00D 73*118a3315SNicholas Kazlauskas #define mmCLK11_CLK1_CLK_PLL_REQ 0x1B20D 74*118a3315SNicholas Kazlauskas #define mmCLK12_CLK1_CLK_PLL_REQ 0x1B40D 75*118a3315SNicholas Kazlauskas #define mmCLK13_CLK1_CLK_PLL_REQ 0x1B60D 76*118a3315SNicholas Kazlauskas 77*118a3315SNicholas Kazlauskas #define mmCLK2_CLK_PLL_REQ 0x17E0D 78*118a3315SNicholas Kazlauskas 79*118a3315SNicholas Kazlauskas /*AMCLK*/ 80*118a3315SNicholas Kazlauskas #define mmCLK11_CLK1_CLK0_DFS_CNTL 0x1B23F 81*118a3315SNicholas Kazlauskas #define mmCLK11_CLK1_CLK_PLL_REQ 0x1B20D 82*118a3315SNicholas Kazlauskas #endif 83*118a3315SNicholas Kazlauskas 84*118a3315SNicholas Kazlauskas struct dcn31_watermarks; 85*118a3315SNicholas Kazlauskas 86*118a3315SNicholas Kazlauskas struct dcn31_smu_watermark_set { 87*118a3315SNicholas Kazlauskas struct dcn31_watermarks *wm_set; 88*118a3315SNicholas Kazlauskas union large_integer mc_address; 89*118a3315SNicholas Kazlauskas }; 90*118a3315SNicholas Kazlauskas 91*118a3315SNicholas Kazlauskas struct clk_mgr_dcn31 { 92*118a3315SNicholas Kazlauskas struct clk_mgr_internal base; 93*118a3315SNicholas Kazlauskas struct dcn31_smu_watermark_set smu_wm_set; 94*118a3315SNicholas Kazlauskas }; 95*118a3315SNicholas Kazlauskas 96*118a3315SNicholas Kazlauskas void dcn31_clk_mgr_construct(struct dc_context *ctx, 97*118a3315SNicholas Kazlauskas struct clk_mgr_dcn31 *clk_mgr, 98*118a3315SNicholas Kazlauskas struct pp_smu_funcs *pp_smu, 99*118a3315SNicholas Kazlauskas struct dccg *dccg); 100*118a3315SNicholas Kazlauskas 101*118a3315SNicholas Kazlauskas void dcn31_clk_mgr_destroy(struct clk_mgr_internal *clk_mgr_int); 102*118a3315SNicholas Kazlauskas 103*118a3315SNicholas Kazlauskas #endif //__DCN31_CLK_MGR_H__ 104