1 /* 2 * Copyright 2019 Advanced Micro Devices, Inc. 3 * 4 * Permission is hereby granted, free of charge, to any person obtaining a 5 * copy of this software and associated documentation files (the "Software"), 6 * to deal in the Software without restriction, including without limitation 7 * the rights to use, copy, modify, merge, publish, distribute, sublicense, 8 * and/or sell copies of the Software, and to permit persons to whom the 9 * Software is furnished to do so, subject to the following conditions: 10 * 11 * The above copyright notice and this permission notice shall be included in 12 * all copies or substantial portions of the Software. 13 * 14 * THE SOFTWARE IS PROVIDED "AS IS", WITHOUT WARRANTY OF ANY KIND, EXPRESS OR 15 * IMPLIED, INCLUDING BUT NOT LIMITED TO THE WARRANTIES OF MERCHANTABILITY, 16 * FITNESS FOR A PARTICULAR PURPOSE AND NONINFRINGEMENT. IN NO EVENT SHALL 17 * THE COPYRIGHT HOLDER(S) OR AUTHOR(S) BE LIABLE FOR ANY CLAIM, DAMAGES OR 18 * OTHER LIABILITY, WHETHER IN AN ACTION OF CONTRACT, TORT OR OTHERWISE, 19 * ARISING FROM, OUT OF OR IN CONNECTION WITH THE SOFTWARE OR THE USE OR 20 * OTHER DEALINGS IN THE SOFTWARE. 21 * 22 * Authors: AMD 23 * 24 */ 25 26 27 28 #include "dccg.h" 29 #include "clk_mgr_internal.h" 30 31 // For dce12_get_dp_ref_freq_khz 32 #include "dce100/dce_clk_mgr.h" 33 34 // For dcn20_update_clocks_update_dpp_dto 35 #include "dcn20/dcn20_clk_mgr.h" 36 37 38 39 #include "dcn31_clk_mgr.h" 40 41 #include "reg_helper.h" 42 #include "core_types.h" 43 #include "dcn31_smu.h" 44 #include "dm_helpers.h" 45 46 /* TODO: remove this include once we ported over remaining clk mgr functions*/ 47 #include "dcn30/dcn30_clk_mgr.h" 48 49 #include "dc_dmub_srv.h" 50 51 #include "yellow_carp_offset.h" 52 53 #define regCLK1_CLK_PLL_REQ 0x0237 54 #define regCLK1_CLK_PLL_REQ_BASE_IDX 0 55 56 #define CLK1_CLK_PLL_REQ__FbMult_int__SHIFT 0x0 57 #define CLK1_CLK_PLL_REQ__PllSpineDiv__SHIFT 0xc 58 #define CLK1_CLK_PLL_REQ__FbMult_frac__SHIFT 0x10 59 #define CLK1_CLK_PLL_REQ__FbMult_int_MASK 0x000001FFL 60 #define CLK1_CLK_PLL_REQ__PllSpineDiv_MASK 0x0000F000L 61 #define CLK1_CLK_PLL_REQ__FbMult_frac_MASK 0xFFFF0000L 62 63 #define REG(reg_name) \ 64 (CLK_BASE.instance[0].segment[reg ## reg_name ## _BASE_IDX] + reg ## reg_name) 65 66 #define TO_CLK_MGR_DCN31(clk_mgr)\ 67 container_of(clk_mgr, struct clk_mgr_dcn31, base) 68 69 static int dcn31_get_active_display_cnt_wa( 70 struct dc *dc, 71 struct dc_state *context) 72 { 73 int i, display_count; 74 bool tmds_present = false; 75 76 display_count = 0; 77 for (i = 0; i < context->stream_count; i++) { 78 const struct dc_stream_state *stream = context->streams[i]; 79 80 if (stream->signal == SIGNAL_TYPE_HDMI_TYPE_A || 81 stream->signal == SIGNAL_TYPE_DVI_SINGLE_LINK || 82 stream->signal == SIGNAL_TYPE_DVI_DUAL_LINK) 83 tmds_present = true; 84 } 85 86 for (i = 0; i < dc->link_count; i++) { 87 const struct dc_link *link = dc->links[i]; 88 89 /* abusing the fact that the dig and phy are coupled to see if the phy is enabled */ 90 if (link->link_enc && link->link_enc->funcs->is_dig_enabled && 91 link->link_enc->funcs->is_dig_enabled(link->link_enc)) 92 display_count++; 93 } 94 95 /* WA for hang on HDMI after display off back back on*/ 96 if (display_count == 0 && tmds_present) 97 display_count = 1; 98 99 return display_count; 100 } 101 102 static void dcn31_disable_otg_wa(struct clk_mgr *clk_mgr_base, bool disable) 103 { 104 struct dc *dc = clk_mgr_base->ctx->dc; 105 int i; 106 107 for (i = 0; i < dc->res_pool->pipe_count; ++i) { 108 struct pipe_ctx *pipe = &dc->current_state->res_ctx.pipe_ctx[i]; 109 110 if (pipe->top_pipe || pipe->prev_odm_pipe) 111 continue; 112 if (pipe->stream && (pipe->stream->dpms_off || dc_is_virtual_signal(pipe->stream->signal))) { 113 if (disable) 114 pipe->stream_res.tg->funcs->immediate_disable_crtc(pipe->stream_res.tg); 115 else 116 pipe->stream_res.tg->funcs->enable_crtc(pipe->stream_res.tg); 117 } 118 } 119 } 120 121 void dcn31_update_clocks(struct clk_mgr *clk_mgr_base, 122 struct dc_state *context, 123 bool safe_to_lower) 124 { 125 union dmub_rb_cmd cmd; 126 struct clk_mgr_internal *clk_mgr = TO_CLK_MGR_INTERNAL(clk_mgr_base); 127 struct dc_clocks *new_clocks = &context->bw_ctx.bw.dcn.clk; 128 struct dc *dc = clk_mgr_base->ctx->dc; 129 int display_count; 130 bool update_dppclk = false; 131 bool update_dispclk = false; 132 bool dpp_clock_lowered = false; 133 134 if (dc->work_arounds.skip_clock_update) 135 return; 136 137 /* 138 * if it is safe to lower, but we are already in the lower state, we don't have to do anything 139 * also if safe to lower is false, we just go in the higher state 140 */ 141 if (safe_to_lower) { 142 if (new_clocks->zstate_support != DCN_ZSTATE_SUPPORT_DISALLOW && 143 new_clocks->zstate_support != clk_mgr_base->clks.zstate_support) { 144 dcn31_smu_set_zstate_support(clk_mgr, new_clocks->zstate_support); 145 dm_helpers_enable_periodic_detection(clk_mgr_base->ctx, true); 146 clk_mgr_base->clks.zstate_support = new_clocks->zstate_support; 147 } 148 149 if (clk_mgr_base->clks.dtbclk_en && !new_clocks->dtbclk_en) { 150 dcn31_smu_set_dtbclk(clk_mgr, false); 151 clk_mgr_base->clks.dtbclk_en = new_clocks->dtbclk_en; 152 } 153 /* check that we're not already in lower */ 154 if (clk_mgr_base->clks.pwr_state != DCN_PWR_STATE_LOW_POWER) { 155 display_count = dcn31_get_active_display_cnt_wa(dc, context); 156 /* if we can go lower, go lower */ 157 if (display_count == 0) { 158 union display_idle_optimization_u idle_info = { 0 }; 159 idle_info.idle_info.df_request_disabled = 1; 160 idle_info.idle_info.phy_ref_clk_off = 1; 161 idle_info.idle_info.s0i2_rdy = 1; 162 dcn31_smu_set_display_idle_optimization(clk_mgr, idle_info.data); 163 /* update power state */ 164 clk_mgr_base->clks.pwr_state = DCN_PWR_STATE_LOW_POWER; 165 } 166 } 167 } else { 168 if (new_clocks->zstate_support == DCN_ZSTATE_SUPPORT_DISALLOW && 169 new_clocks->zstate_support != clk_mgr_base->clks.zstate_support) { 170 dcn31_smu_set_zstate_support(clk_mgr, DCN_ZSTATE_SUPPORT_DISALLOW); 171 dm_helpers_enable_periodic_detection(clk_mgr_base->ctx, false); 172 clk_mgr_base->clks.zstate_support = new_clocks->zstate_support; 173 } 174 175 if (!clk_mgr_base->clks.dtbclk_en && new_clocks->dtbclk_en) { 176 dcn31_smu_set_dtbclk(clk_mgr, true); 177 clk_mgr_base->clks.dtbclk_en = new_clocks->dtbclk_en; 178 } 179 180 /* check that we're not already in D0 */ 181 if (clk_mgr_base->clks.pwr_state != DCN_PWR_STATE_MISSION_MODE) { 182 union display_idle_optimization_u idle_info = { 0 }; 183 dcn31_smu_set_display_idle_optimization(clk_mgr, idle_info.data); 184 /* update power state */ 185 clk_mgr_base->clks.pwr_state = DCN_PWR_STATE_MISSION_MODE; 186 } 187 } 188 189 if (should_set_clock(safe_to_lower, new_clocks->dcfclk_khz, clk_mgr_base->clks.dcfclk_khz)) { 190 clk_mgr_base->clks.dcfclk_khz = new_clocks->dcfclk_khz; 191 dcn31_smu_set_hard_min_dcfclk(clk_mgr, clk_mgr_base->clks.dcfclk_khz); 192 } 193 194 if (should_set_clock(safe_to_lower, 195 new_clocks->dcfclk_deep_sleep_khz, clk_mgr_base->clks.dcfclk_deep_sleep_khz)) { 196 clk_mgr_base->clks.dcfclk_deep_sleep_khz = new_clocks->dcfclk_deep_sleep_khz; 197 dcn31_smu_set_min_deep_sleep_dcfclk(clk_mgr, clk_mgr_base->clks.dcfclk_deep_sleep_khz); 198 } 199 200 // workaround: Limit dppclk to 100Mhz to avoid lower eDP panel switch to plus 4K monitor underflow. 201 if (!IS_DIAG_DC(dc->ctx->dce_environment)) { 202 if (new_clocks->dppclk_khz < 100000) 203 new_clocks->dppclk_khz = 100000; 204 } 205 206 if (should_set_clock(safe_to_lower, new_clocks->dppclk_khz, clk_mgr->base.clks.dppclk_khz)) { 207 if (clk_mgr->base.clks.dppclk_khz > new_clocks->dppclk_khz) 208 dpp_clock_lowered = true; 209 clk_mgr_base->clks.dppclk_khz = new_clocks->dppclk_khz; 210 update_dppclk = true; 211 } 212 213 if (should_set_clock(safe_to_lower, new_clocks->dispclk_khz, clk_mgr_base->clks.dispclk_khz)) { 214 dcn31_disable_otg_wa(clk_mgr_base, true); 215 216 clk_mgr_base->clks.dispclk_khz = new_clocks->dispclk_khz; 217 dcn31_smu_set_dispclk(clk_mgr, clk_mgr_base->clks.dispclk_khz); 218 dcn31_disable_otg_wa(clk_mgr_base, false); 219 220 update_dispclk = true; 221 } 222 223 if (dpp_clock_lowered) { 224 // increase per DPP DTO before lowering global dppclk 225 dcn20_update_clocks_update_dpp_dto(clk_mgr, context, safe_to_lower); 226 dcn31_smu_set_dppclk(clk_mgr, clk_mgr_base->clks.dppclk_khz); 227 } else { 228 // increase global DPPCLK before lowering per DPP DTO 229 if (update_dppclk || update_dispclk) 230 dcn31_smu_set_dppclk(clk_mgr, clk_mgr_base->clks.dppclk_khz); 231 // always update dtos unless clock is lowered and not safe to lower 232 if (new_clocks->dppclk_khz >= dc->current_state->bw_ctx.bw.dcn.clk.dppclk_khz) 233 dcn20_update_clocks_update_dpp_dto(clk_mgr, context, safe_to_lower); 234 } 235 236 // notify DMCUB of latest clocks 237 memset(&cmd, 0, sizeof(cmd)); 238 cmd.notify_clocks.header.type = DMUB_CMD__CLK_MGR; 239 cmd.notify_clocks.header.sub_type = DMUB_CMD__CLK_MGR_NOTIFY_CLOCKS; 240 cmd.notify_clocks.clocks.dcfclk_khz = clk_mgr_base->clks.dcfclk_khz; 241 cmd.notify_clocks.clocks.dcfclk_deep_sleep_khz = 242 clk_mgr_base->clks.dcfclk_deep_sleep_khz; 243 cmd.notify_clocks.clocks.dispclk_khz = clk_mgr_base->clks.dispclk_khz; 244 cmd.notify_clocks.clocks.dppclk_khz = clk_mgr_base->clks.dppclk_khz; 245 246 dc_dmub_srv_cmd_queue(dc->ctx->dmub_srv, &cmd); 247 dc_dmub_srv_cmd_execute(dc->ctx->dmub_srv); 248 dc_dmub_srv_wait_idle(dc->ctx->dmub_srv); 249 } 250 251 static int get_vco_frequency_from_reg(struct clk_mgr_internal *clk_mgr) 252 { 253 /* get FbMult value */ 254 struct fixed31_32 pll_req; 255 unsigned int fbmult_frac_val = 0; 256 unsigned int fbmult_int_val = 0; 257 258 /* 259 * Register value of fbmult is in 8.16 format, we are converting to 31.32 260 * to leverage the fix point operations available in driver 261 */ 262 263 REG_GET(CLK1_CLK_PLL_REQ, FbMult_frac, &fbmult_frac_val); /* 16 bit fractional part*/ 264 REG_GET(CLK1_CLK_PLL_REQ, FbMult_int, &fbmult_int_val); /* 8 bit integer part */ 265 266 pll_req = dc_fixpt_from_int(fbmult_int_val); 267 268 /* 269 * since fractional part is only 16 bit in register definition but is 32 bit 270 * in our fix point definiton, need to shift left by 16 to obtain correct value 271 */ 272 pll_req.value |= fbmult_frac_val << 16; 273 274 /* multiply by REFCLK period */ 275 pll_req = dc_fixpt_mul_int(pll_req, clk_mgr->dfs_ref_freq_khz); 276 277 /* integer part is now VCO frequency in kHz */ 278 return dc_fixpt_floor(pll_req); 279 } 280 281 static void dcn31_enable_pme_wa(struct clk_mgr *clk_mgr_base) 282 { 283 struct clk_mgr_internal *clk_mgr = TO_CLK_MGR_INTERNAL(clk_mgr_base); 284 285 dcn31_smu_enable_pme_wa(clk_mgr); 286 } 287 288 void dcn31_init_clocks(struct clk_mgr *clk_mgr) 289 { 290 uint32_t ref_dtbclk = clk_mgr->clks.ref_dtbclk_khz; 291 292 memset(&(clk_mgr->clks), 0, sizeof(struct dc_clocks)); 293 // Assumption is that boot state always supports pstate 294 clk_mgr->clks.ref_dtbclk_khz = ref_dtbclk; // restore ref_dtbclk 295 clk_mgr->clks.p_state_change_support = true; 296 clk_mgr->clks.prev_p_state_change_support = true; 297 clk_mgr->clks.pwr_state = DCN_PWR_STATE_UNKNOWN; 298 clk_mgr->clks.zstate_support = DCN_ZSTATE_SUPPORT_UNKNOWN; 299 } 300 301 bool dcn31_are_clock_states_equal(struct dc_clocks *a, 302 struct dc_clocks *b) 303 { 304 if (a->dispclk_khz != b->dispclk_khz) 305 return false; 306 else if (a->dppclk_khz != b->dppclk_khz) 307 return false; 308 else if (a->dcfclk_khz != b->dcfclk_khz) 309 return false; 310 else if (a->dcfclk_deep_sleep_khz != b->dcfclk_deep_sleep_khz) 311 return false; 312 else if (a->zstate_support != b->zstate_support) 313 return false; 314 else if (a->dtbclk_en != b->dtbclk_en) 315 return false; 316 317 return true; 318 } 319 320 static void dcn31_dump_clk_registers(struct clk_state_registers_and_bypass *regs_and_bypass, 321 struct clk_mgr *clk_mgr_base, struct clk_log_info *log_info) 322 { 323 return; 324 } 325 326 static struct clk_bw_params dcn31_bw_params = { 327 .vram_type = Ddr4MemType, 328 .num_channels = 1, 329 .clk_table = { 330 .num_entries = 4, 331 }, 332 333 }; 334 335 static struct wm_table ddr5_wm_table = { 336 .entries = { 337 { 338 .wm_inst = WM_A, 339 .wm_type = WM_TYPE_PSTATE_CHG, 340 .pstate_latency_us = 11.72, 341 .sr_exit_time_us = 9, 342 .sr_enter_plus_exit_time_us = 11, 343 .valid = true, 344 }, 345 { 346 .wm_inst = WM_B, 347 .wm_type = WM_TYPE_PSTATE_CHG, 348 .pstate_latency_us = 11.72, 349 .sr_exit_time_us = 9, 350 .sr_enter_plus_exit_time_us = 11, 351 .valid = true, 352 }, 353 { 354 .wm_inst = WM_C, 355 .wm_type = WM_TYPE_PSTATE_CHG, 356 .pstate_latency_us = 11.72, 357 .sr_exit_time_us = 9, 358 .sr_enter_plus_exit_time_us = 11, 359 .valid = true, 360 }, 361 { 362 .wm_inst = WM_D, 363 .wm_type = WM_TYPE_PSTATE_CHG, 364 .pstate_latency_us = 11.72, 365 .sr_exit_time_us = 9, 366 .sr_enter_plus_exit_time_us = 11, 367 .valid = true, 368 }, 369 } 370 }; 371 372 static struct wm_table lpddr5_wm_table = { 373 .entries = { 374 { 375 .wm_inst = WM_A, 376 .wm_type = WM_TYPE_PSTATE_CHG, 377 .pstate_latency_us = 11.65333, 378 .sr_exit_time_us = 11.5, 379 .sr_enter_plus_exit_time_us = 14.5, 380 .valid = true, 381 }, 382 { 383 .wm_inst = WM_B, 384 .wm_type = WM_TYPE_PSTATE_CHG, 385 .pstate_latency_us = 11.65333, 386 .sr_exit_time_us = 11.5, 387 .sr_enter_plus_exit_time_us = 14.5, 388 .valid = true, 389 }, 390 { 391 .wm_inst = WM_C, 392 .wm_type = WM_TYPE_PSTATE_CHG, 393 .pstate_latency_us = 11.65333, 394 .sr_exit_time_us = 11.5, 395 .sr_enter_plus_exit_time_us = 14.5, 396 .valid = true, 397 }, 398 { 399 .wm_inst = WM_D, 400 .wm_type = WM_TYPE_PSTATE_CHG, 401 .pstate_latency_us = 11.65333, 402 .sr_exit_time_us = 11.5, 403 .sr_enter_plus_exit_time_us = 14.5, 404 .valid = true, 405 }, 406 } 407 }; 408 409 static DpmClocks_t dummy_clocks; 410 411 static struct dcn31_watermarks dummy_wms = { 0 }; 412 413 static void dcn31_build_watermark_ranges(struct clk_bw_params *bw_params, struct dcn31_watermarks *table) 414 { 415 int i, num_valid_sets; 416 417 num_valid_sets = 0; 418 419 for (i = 0; i < WM_SET_COUNT; i++) { 420 /* skip empty entries, the smu array has no holes*/ 421 if (!bw_params->wm_table.entries[i].valid) 422 continue; 423 424 table->WatermarkRow[WM_DCFCLK][num_valid_sets].WmSetting = bw_params->wm_table.entries[i].wm_inst; 425 table->WatermarkRow[WM_DCFCLK][num_valid_sets].WmType = bw_params->wm_table.entries[i].wm_type; 426 /* We will not select WM based on fclk, so leave it as unconstrained */ 427 table->WatermarkRow[WM_DCFCLK][num_valid_sets].MinClock = 0; 428 table->WatermarkRow[WM_DCFCLK][num_valid_sets].MaxClock = 0xFFFF; 429 430 if (table->WatermarkRow[WM_DCFCLK][num_valid_sets].WmType == WM_TYPE_PSTATE_CHG) { 431 if (i == 0) 432 table->WatermarkRow[WM_DCFCLK][num_valid_sets].MinMclk = 0; 433 else { 434 /* add 1 to make it non-overlapping with next lvl */ 435 table->WatermarkRow[WM_DCFCLK][num_valid_sets].MinMclk = 436 bw_params->clk_table.entries[i - 1].dcfclk_mhz + 1; 437 } 438 table->WatermarkRow[WM_DCFCLK][num_valid_sets].MaxMclk = 439 bw_params->clk_table.entries[i].dcfclk_mhz; 440 441 } else { 442 /* unconstrained for memory retraining */ 443 table->WatermarkRow[WM_DCFCLK][num_valid_sets].MinClock = 0; 444 table->WatermarkRow[WM_DCFCLK][num_valid_sets].MaxClock = 0xFFFF; 445 446 /* Modify previous watermark range to cover up to max */ 447 table->WatermarkRow[WM_DCFCLK][num_valid_sets - 1].MaxClock = 0xFFFF; 448 } 449 num_valid_sets++; 450 } 451 452 ASSERT(num_valid_sets != 0); /* Must have at least one set of valid watermarks */ 453 454 /* modify the min and max to make sure we cover the whole range*/ 455 table->WatermarkRow[WM_DCFCLK][0].MinMclk = 0; 456 table->WatermarkRow[WM_DCFCLK][0].MinClock = 0; 457 table->WatermarkRow[WM_DCFCLK][num_valid_sets - 1].MaxMclk = 0xFFFF; 458 table->WatermarkRow[WM_DCFCLK][num_valid_sets - 1].MaxClock = 0xFFFF; 459 460 /* This is for writeback only, does not matter currently as no writeback support*/ 461 table->WatermarkRow[WM_SOCCLK][0].WmSetting = WM_A; 462 table->WatermarkRow[WM_SOCCLK][0].MinClock = 0; 463 table->WatermarkRow[WM_SOCCLK][0].MaxClock = 0xFFFF; 464 table->WatermarkRow[WM_SOCCLK][0].MinMclk = 0; 465 table->WatermarkRow[WM_SOCCLK][0].MaxMclk = 0xFFFF; 466 } 467 468 static void dcn31_notify_wm_ranges(struct clk_mgr *clk_mgr_base) 469 { 470 struct clk_mgr_internal *clk_mgr = TO_CLK_MGR_INTERNAL(clk_mgr_base); 471 struct clk_mgr_dcn31 *clk_mgr_dcn31 = TO_CLK_MGR_DCN31(clk_mgr); 472 struct dcn31_watermarks *table = clk_mgr_dcn31->smu_wm_set.wm_set; 473 474 if (!clk_mgr->smu_ver) 475 return; 476 477 if (!table || clk_mgr_dcn31->smu_wm_set.mc_address.quad_part == 0) 478 return; 479 480 memset(table, 0, sizeof(*table)); 481 482 dcn31_build_watermark_ranges(clk_mgr_base->bw_params, table); 483 484 dcn31_smu_set_dram_addr_high(clk_mgr, 485 clk_mgr_dcn31->smu_wm_set.mc_address.high_part); 486 dcn31_smu_set_dram_addr_low(clk_mgr, 487 clk_mgr_dcn31->smu_wm_set.mc_address.low_part); 488 dcn31_smu_transfer_wm_table_dram_2_smu(clk_mgr); 489 } 490 491 static void dcn31_get_dpm_table_from_smu(struct clk_mgr_internal *clk_mgr, 492 struct dcn31_smu_dpm_clks *smu_dpm_clks) 493 { 494 DpmClocks_t *table = smu_dpm_clks->dpm_clks; 495 496 if (!clk_mgr->smu_ver) 497 return; 498 499 if (!table || smu_dpm_clks->mc_address.quad_part == 0) 500 return; 501 502 memset(table, 0, sizeof(*table)); 503 504 dcn31_smu_set_dram_addr_high(clk_mgr, 505 smu_dpm_clks->mc_address.high_part); 506 dcn31_smu_set_dram_addr_low(clk_mgr, 507 smu_dpm_clks->mc_address.low_part); 508 dcn31_smu_transfer_dpm_table_smu_2_dram(clk_mgr); 509 } 510 511 static uint32_t find_max_clk_value(const uint32_t clocks[], uint32_t num_clocks) 512 { 513 uint32_t max = 0; 514 int i; 515 516 for (i = 0; i < num_clocks; ++i) { 517 if (clocks[i] > max) 518 max = clocks[i]; 519 } 520 521 return max; 522 } 523 524 static unsigned int find_clk_for_voltage( 525 const DpmClocks_t *clock_table, 526 const uint32_t clocks[], 527 unsigned int voltage) 528 { 529 int i; 530 int max_voltage = 0; 531 int clock = 0; 532 533 for (i = 0; i < NUM_SOC_VOLTAGE_LEVELS; i++) { 534 if (clock_table->SocVoltage[i] == voltage) { 535 return clocks[i]; 536 } else if (clock_table->SocVoltage[i] >= max_voltage && 537 clock_table->SocVoltage[i] < voltage) { 538 max_voltage = clock_table->SocVoltage[i]; 539 clock = clocks[i]; 540 } 541 } 542 543 ASSERT(clock); 544 return clock; 545 } 546 547 static void dcn31_clk_mgr_helper_populate_bw_params(struct clk_mgr_internal *clk_mgr, 548 struct integrated_info *bios_info, 549 const DpmClocks_t *clock_table) 550 { 551 int i, j; 552 struct clk_bw_params *bw_params = clk_mgr->base.bw_params; 553 uint32_t max_dispclk = 0, max_dppclk = 0; 554 555 j = -1; 556 557 ASSERT(NUM_DF_PSTATE_LEVELS <= MAX_NUM_DPM_LVL); 558 559 /* Find lowest DPM, FCLK is filled in reverse order*/ 560 561 for (i = NUM_DF_PSTATE_LEVELS - 1; i >= 0; i--) { 562 if (clock_table->DfPstateTable[i].FClk != 0) { 563 j = i; 564 break; 565 } 566 } 567 568 if (j == -1) { 569 /* clock table is all 0s, just use our own hardcode */ 570 ASSERT(0); 571 return; 572 } 573 574 bw_params->clk_table.num_entries = j + 1; 575 576 /* dispclk and dppclk can be max at any voltage, same number of levels for both */ 577 if (clock_table->NumDispClkLevelsEnabled <= NUM_DISPCLK_DPM_LEVELS && 578 clock_table->NumDispClkLevelsEnabled <= NUM_DPPCLK_DPM_LEVELS) { 579 max_dispclk = find_max_clk_value(clock_table->DispClocks, clock_table->NumDispClkLevelsEnabled); 580 max_dppclk = find_max_clk_value(clock_table->DppClocks, clock_table->NumDispClkLevelsEnabled); 581 } else { 582 ASSERT(0); 583 } 584 585 for (i = 0; i < bw_params->clk_table.num_entries; i++, j--) { 586 bw_params->clk_table.entries[i].fclk_mhz = clock_table->DfPstateTable[j].FClk; 587 bw_params->clk_table.entries[i].memclk_mhz = clock_table->DfPstateTable[j].MemClk; 588 bw_params->clk_table.entries[i].voltage = clock_table->DfPstateTable[j].Voltage; 589 switch (clock_table->DfPstateTable[j].WckRatio) { 590 case WCK_RATIO_1_2: 591 bw_params->clk_table.entries[i].wck_ratio = 2; 592 break; 593 case WCK_RATIO_1_4: 594 bw_params->clk_table.entries[i].wck_ratio = 4; 595 break; 596 default: 597 bw_params->clk_table.entries[i].wck_ratio = 1; 598 } 599 bw_params->clk_table.entries[i].dcfclk_mhz = find_clk_for_voltage(clock_table, clock_table->DcfClocks, clock_table->DfPstateTable[j].Voltage); 600 bw_params->clk_table.entries[i].socclk_mhz = find_clk_for_voltage(clock_table, clock_table->SocClocks, clock_table->DfPstateTable[j].Voltage); 601 bw_params->clk_table.entries[i].dispclk_mhz = max_dispclk; 602 bw_params->clk_table.entries[i].dppclk_mhz = max_dppclk; 603 } 604 605 bw_params->vram_type = bios_info->memory_type; 606 bw_params->num_channels = bios_info->ma_channel_number; 607 608 for (i = 0; i < WM_SET_COUNT; i++) { 609 bw_params->wm_table.entries[i].wm_inst = i; 610 611 if (i >= bw_params->clk_table.num_entries) { 612 bw_params->wm_table.entries[i].valid = false; 613 continue; 614 } 615 616 bw_params->wm_table.entries[i].wm_type = WM_TYPE_PSTATE_CHG; 617 bw_params->wm_table.entries[i].valid = true; 618 } 619 } 620 621 static void dcn31_set_low_power_state(struct clk_mgr *clk_mgr_base) 622 { 623 int display_count; 624 struct clk_mgr_internal *clk_mgr = TO_CLK_MGR_INTERNAL(clk_mgr_base); 625 struct dc *dc = clk_mgr_base->ctx->dc; 626 struct dc_state *context = dc->current_state; 627 628 if (clk_mgr_base->clks.pwr_state != DCN_PWR_STATE_LOW_POWER) { 629 display_count = dcn31_get_active_display_cnt_wa(dc, context); 630 /* if we can go lower, go lower */ 631 if (display_count == 0) { 632 union display_idle_optimization_u idle_info = { 0 }; 633 634 idle_info.idle_info.df_request_disabled = 1; 635 idle_info.idle_info.phy_ref_clk_off = 1; 636 idle_info.idle_info.s0i2_rdy = 1; 637 dcn31_smu_set_display_idle_optimization(clk_mgr, idle_info.data); 638 /* update power state */ 639 clk_mgr_base->clks.pwr_state = DCN_PWR_STATE_LOW_POWER; 640 } 641 } 642 } 643 644 int dcn31_get_dtb_ref_freq_khz(struct clk_mgr *clk_mgr_base) 645 { 646 return clk_mgr_base->clks.ref_dtbclk_khz; 647 } 648 649 static struct clk_mgr_funcs dcn31_funcs = { 650 .get_dp_ref_clk_frequency = dce12_get_dp_ref_freq_khz, 651 .get_dtb_ref_clk_frequency = dcn31_get_dtb_ref_freq_khz, 652 .update_clocks = dcn31_update_clocks, 653 .init_clocks = dcn31_init_clocks, 654 .enable_pme_wa = dcn31_enable_pme_wa, 655 .are_clock_states_equal = dcn31_are_clock_states_equal, 656 .notify_wm_ranges = dcn31_notify_wm_ranges, 657 .set_low_power_state = dcn31_set_low_power_state 658 }; 659 extern struct clk_mgr_funcs dcn3_fpga_funcs; 660 661 void dcn31_clk_mgr_construct( 662 struct dc_context *ctx, 663 struct clk_mgr_dcn31 *clk_mgr, 664 struct pp_smu_funcs *pp_smu, 665 struct dccg *dccg) 666 { 667 struct dcn31_smu_dpm_clks smu_dpm_clks = { 0 }; 668 669 clk_mgr->base.base.ctx = ctx; 670 clk_mgr->base.base.funcs = &dcn31_funcs; 671 672 clk_mgr->base.pp_smu = pp_smu; 673 674 clk_mgr->base.dccg = dccg; 675 clk_mgr->base.dfs_bypass_disp_clk = 0; 676 677 clk_mgr->base.dprefclk_ss_percentage = 0; 678 clk_mgr->base.dprefclk_ss_divider = 1000; 679 clk_mgr->base.ss_on_dprefclk = false; 680 clk_mgr->base.dfs_ref_freq_khz = 48000; 681 682 clk_mgr->smu_wm_set.wm_set = (struct dcn31_watermarks *)dm_helpers_allocate_gpu_mem( 683 clk_mgr->base.base.ctx, 684 DC_MEM_ALLOC_TYPE_FRAME_BUFFER, 685 sizeof(struct dcn31_watermarks), 686 &clk_mgr->smu_wm_set.mc_address.quad_part); 687 688 if (!clk_mgr->smu_wm_set.wm_set) { 689 clk_mgr->smu_wm_set.wm_set = &dummy_wms; 690 clk_mgr->smu_wm_set.mc_address.quad_part = 0; 691 } 692 ASSERT(clk_mgr->smu_wm_set.wm_set); 693 694 smu_dpm_clks.dpm_clks = (DpmClocks_t *)dm_helpers_allocate_gpu_mem( 695 clk_mgr->base.base.ctx, 696 DC_MEM_ALLOC_TYPE_FRAME_BUFFER, 697 sizeof(DpmClocks_t), 698 &smu_dpm_clks.mc_address.quad_part); 699 700 if (smu_dpm_clks.dpm_clks == NULL) { 701 smu_dpm_clks.dpm_clks = &dummy_clocks; 702 smu_dpm_clks.mc_address.quad_part = 0; 703 } 704 705 ASSERT(smu_dpm_clks.dpm_clks); 706 707 if (IS_FPGA_MAXIMUS_DC(ctx->dce_environment)) { 708 clk_mgr->base.base.funcs = &dcn3_fpga_funcs; 709 } else { 710 struct clk_log_info log_info = {0}; 711 712 clk_mgr->base.smu_ver = dcn31_smu_get_smu_version(&clk_mgr->base); 713 714 if (clk_mgr->base.smu_ver) 715 clk_mgr->base.smu_present = true; 716 717 /* TODO: Check we get what we expect during bringup */ 718 clk_mgr->base.base.dentist_vco_freq_khz = get_vco_frequency_from_reg(&clk_mgr->base); 719 720 if (ctx->dc_bios->integrated_info->memory_type == LpDdr5MemType) { 721 dcn31_bw_params.wm_table = lpddr5_wm_table; 722 } else { 723 dcn31_bw_params.wm_table = ddr5_wm_table; 724 } 725 /* Saved clocks configured at boot for debug purposes */ 726 dcn31_dump_clk_registers(&clk_mgr->base.base.boot_snapshot, &clk_mgr->base.base, &log_info); 727 728 } 729 730 clk_mgr->base.base.dprefclk_khz = 600000; 731 clk_mgr->base.base.clks.ref_dtbclk_khz = 600000; 732 dce_clock_read_ss_info(&clk_mgr->base); 733 /*if bios enabled SS, driver needs to adjust dtb clock, only enable with correct bios*/ 734 //clk_mgr->base.dccg->ref_dtbclk_khz = dce_adjust_dp_ref_freq_for_ss(clk_mgr_internal, clk_mgr->base.base.dprefclk_khz); 735 736 clk_mgr->base.base.bw_params = &dcn31_bw_params; 737 738 if (clk_mgr->base.base.ctx->dc->debug.pstate_enabled) { 739 dcn31_get_dpm_table_from_smu(&clk_mgr->base, &smu_dpm_clks); 740 741 if (ctx->dc_bios && ctx->dc_bios->integrated_info) { 742 dcn31_clk_mgr_helper_populate_bw_params( 743 &clk_mgr->base, 744 ctx->dc_bios->integrated_info, 745 smu_dpm_clks.dpm_clks); 746 } 747 } 748 749 if (smu_dpm_clks.dpm_clks && smu_dpm_clks.mc_address.quad_part != 0) 750 dm_helpers_free_gpu_mem(clk_mgr->base.base.ctx, DC_MEM_ALLOC_TYPE_FRAME_BUFFER, 751 smu_dpm_clks.dpm_clks); 752 } 753 754 void dcn31_clk_mgr_destroy(struct clk_mgr_internal *clk_mgr_int) 755 { 756 struct clk_mgr_dcn31 *clk_mgr = TO_CLK_MGR_DCN31(clk_mgr_int); 757 758 if (clk_mgr->smu_wm_set.wm_set && clk_mgr->smu_wm_set.mc_address.quad_part != 0) 759 dm_helpers_free_gpu_mem(clk_mgr_int->base.ctx, DC_MEM_ALLOC_TYPE_FRAME_BUFFER, 760 clk_mgr->smu_wm_set.wm_set); 761 } 762