1 /* 2 * Copyright 2020 Advanced Micro Devices, Inc. 3 * 4 * Permission is hereby granted, free of charge, to any person obtaining a 5 * copy of this software and associated documentation files (the "Software"), 6 * to deal in the Software without restriction, including without limitation 7 * the rights to use, copy, modify, merge, publish, distribute, sublicense, 8 * and/or sell copies of the Software, and to permit persons to whom the 9 * Software is furnished to do so, subject to the following conditions: 10 * 11 * The above copyright notice and this permission notice shall be included in 12 * all copies or substantial portions of the Software. 13 * 14 * THE SOFTWARE IS PROVIDED "AS IS", WITHOUT WARRANTY OF ANY KIND, EXPRESS OR 15 * IMPLIED, INCLUDING BUT NOT LIMITED TO THE WARRANTIES OF MERCHANTABILITY, 16 * FITNESS FOR A PARTICULAR PURPOSE AND NONINFRINGEMENT. IN NO EVENT SHALL 17 * THE COPYRIGHT HOLDER(S) OR AUTHOR(S) BE LIABLE FOR ANY CLAIM, DAMAGES OR 18 * OTHER LIABILITY, WHETHER IN AN ACTION OF CONTRACT, TORT OR OTHERWISE, 19 * ARISING FROM, OUT OF OR IN CONNECTION WITH THE SOFTWARE OR THE USE OR 20 * OTHER DEALINGS IN THE SOFTWARE. 21 * 22 * Authors: AMD 23 * 24 */ 25 26 #include "dccg.h" 27 #include "clk_mgr_internal.h" 28 29 // For dce12_get_dp_ref_freq_khz 30 #include "dce100/dce_clk_mgr.h" 31 32 // For dcn20_update_clocks_update_dpp_dto 33 #include "dcn20/dcn20_clk_mgr.h" 34 35 #include "vg_clk_mgr.h" 36 #include "dcn301_smu.h" 37 #include "reg_helper.h" 38 #include "core_types.h" 39 #include "dm_helpers.h" 40 41 #include "atomfirmware.h" 42 #include "vangogh_ip_offset.h" 43 #include "clk/clk_11_5_0_offset.h" 44 #include "clk/clk_11_5_0_sh_mask.h" 45 46 /* Constants */ 47 48 #define LPDDR_MEM_RETRAIN_LATENCY 4.977 /* Number obtained from LPDDR4 Training Counter Requirement doc */ 49 50 /* Macros */ 51 52 #define TO_CLK_MGR_VGH(clk_mgr)\ 53 container_of(clk_mgr, struct clk_mgr_vgh, base) 54 55 #define REG(reg_name) \ 56 (CLK_BASE.instance[0].segment[mm ## reg_name ## _BASE_IDX] + mm ## reg_name) 57 58 /* TODO: evaluate how to lower or disable all dcn clocks in screen off case */ 59 static int vg_get_active_display_cnt_wa( 60 struct dc *dc, 61 struct dc_state *context) 62 { 63 int i, display_count; 64 bool tmds_present = false; 65 66 display_count = 0; 67 for (i = 0; i < context->stream_count; i++) { 68 const struct dc_stream_state *stream = context->streams[i]; 69 70 if (stream->signal == SIGNAL_TYPE_HDMI_TYPE_A || 71 stream->signal == SIGNAL_TYPE_DVI_SINGLE_LINK || 72 stream->signal == SIGNAL_TYPE_DVI_DUAL_LINK) 73 tmds_present = true; 74 } 75 76 for (i = 0; i < dc->link_count; i++) { 77 const struct dc_link *link = dc->links[i]; 78 79 /* abusing the fact that the dig and phy are coupled to see if the phy is enabled */ 80 if (link->link_enc->funcs->is_dig_enabled && 81 link->link_enc->funcs->is_dig_enabled(link->link_enc)) 82 display_count++; 83 } 84 85 /* WA for hang on HDMI after display off back back on*/ 86 if (display_count == 0 && tmds_present) 87 display_count = 1; 88 89 return display_count; 90 } 91 92 void vg_update_clocks(struct clk_mgr *clk_mgr_base, 93 struct dc_state *context, 94 bool safe_to_lower) 95 { 96 struct clk_mgr_internal *clk_mgr = TO_CLK_MGR_INTERNAL(clk_mgr_base); 97 struct dc_clocks *new_clocks = &context->bw_ctx.bw.dcn.clk; 98 struct dc *dc = clk_mgr_base->ctx->dc; 99 int display_count; 100 bool update_dppclk = false; 101 bool update_dispclk = false; 102 bool dpp_clock_lowered = false; 103 104 if (dc->work_arounds.skip_clock_update) 105 return; 106 107 /* 108 * if it is safe to lower, but we are already in the lower state, we don't have to do anything 109 * also if safe to lower is false, we just go in the higher state 110 */ 111 if (safe_to_lower) { 112 /* check that we're not already in lower */ 113 if (clk_mgr_base->clks.pwr_state != DCN_PWR_STATE_LOW_POWER) { 114 115 display_count = vg_get_active_display_cnt_wa(dc, context); 116 /* if we can go lower, go lower */ 117 if (display_count == 0 && !IS_DIAG_DC(dc->ctx->dce_environment)) { 118 union display_idle_optimization_u idle_info = { 0 }; 119 120 idle_info.idle_info.df_request_disabled = 1; 121 idle_info.idle_info.phy_ref_clk_off = 1; 122 123 dcn301_smu_set_display_idle_optimization(clk_mgr, idle_info.data); 124 /* update power state */ 125 clk_mgr_base->clks.pwr_state = DCN_PWR_STATE_LOW_POWER; 126 } 127 } 128 } else { 129 /* check that we're not already in D0 */ 130 if (clk_mgr_base->clks.pwr_state != DCN_PWR_STATE_MISSION_MODE) { 131 union display_idle_optimization_u idle_info = { 0 }; 132 133 dcn301_smu_set_display_idle_optimization(clk_mgr, idle_info.data); 134 /* update power state */ 135 clk_mgr_base->clks.pwr_state = DCN_PWR_STATE_MISSION_MODE; 136 } 137 } 138 139 if (should_set_clock(safe_to_lower, new_clocks->dcfclk_khz, clk_mgr_base->clks.dcfclk_khz) && !dc->debug.disable_min_fclk) { 140 clk_mgr_base->clks.dcfclk_khz = new_clocks->dcfclk_khz; 141 dcn301_smu_set_hard_min_dcfclk(clk_mgr, clk_mgr_base->clks.dcfclk_khz); 142 } 143 144 if (should_set_clock(safe_to_lower, 145 new_clocks->dcfclk_deep_sleep_khz, clk_mgr_base->clks.dcfclk_deep_sleep_khz) && !dc->debug.disable_min_fclk) { 146 clk_mgr_base->clks.dcfclk_deep_sleep_khz = new_clocks->dcfclk_deep_sleep_khz; 147 dcn301_smu_set_min_deep_sleep_dcfclk(clk_mgr, clk_mgr_base->clks.dcfclk_deep_sleep_khz); 148 } 149 150 // workaround: Limit dppclk to 100Mhz to avoid lower eDP panel switch to plus 4K monitor underflow. 151 if (!IS_DIAG_DC(dc->ctx->dce_environment)) { 152 if (new_clocks->dppclk_khz < 100000) 153 new_clocks->dppclk_khz = 100000; 154 } 155 156 if (should_set_clock(safe_to_lower, new_clocks->dppclk_khz, clk_mgr->base.clks.dppclk_khz)) { 157 if (clk_mgr->base.clks.dppclk_khz > new_clocks->dppclk_khz) 158 dpp_clock_lowered = true; 159 clk_mgr_base->clks.dppclk_khz = new_clocks->dppclk_khz; 160 update_dppclk = true; 161 } 162 163 if (should_set_clock(safe_to_lower, new_clocks->dispclk_khz, clk_mgr_base->clks.dispclk_khz)) { 164 clk_mgr_base->clks.dispclk_khz = new_clocks->dispclk_khz; 165 dcn301_smu_set_dispclk(clk_mgr, clk_mgr_base->clks.dispclk_khz); 166 167 update_dispclk = true; 168 } 169 170 if (dpp_clock_lowered) { 171 // increase per DPP DTO before lowering global dppclk 172 dcn20_update_clocks_update_dpp_dto(clk_mgr, context, safe_to_lower); 173 dcn301_smu_set_dppclk(clk_mgr, clk_mgr_base->clks.dppclk_khz); 174 } else { 175 // increase global DPPCLK before lowering per DPP DTO 176 if (update_dppclk || update_dispclk) 177 dcn301_smu_set_dppclk(clk_mgr, clk_mgr_base->clks.dppclk_khz); 178 // always update dtos unless clock is lowered and not safe to lower 179 if (new_clocks->dppclk_khz >= dc->current_state->bw_ctx.bw.dcn.clk.dppclk_khz) 180 dcn20_update_clocks_update_dpp_dto(clk_mgr, context, safe_to_lower); 181 } 182 } 183 184 185 static int get_vco_frequency_from_reg(struct clk_mgr_internal *clk_mgr) 186 { 187 /* get FbMult value */ 188 struct fixed31_32 pll_req; 189 unsigned int fbmult_frac_val = 0; 190 unsigned int fbmult_int_val = 0; 191 192 193 /* 194 * Register value of fbmult is in 8.16 format, we are converting to 31.32 195 * to leverage the fix point operations available in driver 196 */ 197 198 REG_GET(CLK1_0_CLK1_CLK_PLL_REQ, FbMult_frac, &fbmult_frac_val); /* 16 bit fractional part*/ 199 REG_GET(CLK1_0_CLK1_CLK_PLL_REQ, FbMult_int, &fbmult_int_val); /* 8 bit integer part */ 200 201 pll_req = dc_fixpt_from_int(fbmult_int_val); 202 203 /* 204 * since fractional part is only 16 bit in register definition but is 32 bit 205 * in our fix point definiton, need to shift left by 16 to obtain correct value 206 */ 207 pll_req.value |= fbmult_frac_val << 16; 208 209 /* multiply by REFCLK period */ 210 pll_req = dc_fixpt_mul_int(pll_req, clk_mgr->dfs_ref_freq_khz); 211 212 /* integer part is now VCO frequency in kHz */ 213 return dc_fixpt_floor(pll_req); 214 } 215 216 static void vg_dump_clk_registers_internal(struct dcn301_clk_internal *internal, struct clk_mgr *clk_mgr_base) 217 { 218 struct clk_mgr_internal *clk_mgr = TO_CLK_MGR_INTERNAL(clk_mgr_base); 219 220 internal->CLK1_CLK3_CURRENT_CNT = REG_READ(CLK1_0_CLK1_CLK3_CURRENT_CNT); 221 internal->CLK1_CLK3_BYPASS_CNTL = REG_READ(CLK1_0_CLK1_CLK3_BYPASS_CNTL); 222 223 internal->CLK1_CLK3_DS_CNTL = REG_READ(CLK1_0_CLK1_CLK3_DS_CNTL); //dcf deep sleep divider 224 internal->CLK1_CLK3_ALLOW_DS = REG_READ(CLK1_0_CLK1_CLK3_ALLOW_DS); 225 226 internal->CLK1_CLK1_CURRENT_CNT = REG_READ(CLK1_0_CLK1_CLK1_CURRENT_CNT); 227 internal->CLK1_CLK1_BYPASS_CNTL = REG_READ(CLK1_0_CLK1_CLK1_BYPASS_CNTL); 228 229 internal->CLK1_CLK2_CURRENT_CNT = REG_READ(CLK1_0_CLK1_CLK2_CURRENT_CNT); 230 internal->CLK1_CLK2_BYPASS_CNTL = REG_READ(CLK1_0_CLK1_CLK2_BYPASS_CNTL); 231 232 internal->CLK1_CLK0_CURRENT_CNT = REG_READ(CLK1_0_CLK1_CLK0_CURRENT_CNT); 233 internal->CLK1_CLK0_BYPASS_CNTL = REG_READ(CLK1_0_CLK1_CLK0_BYPASS_CNTL); 234 } 235 236 /* This function collect raw clk register values */ 237 static void vg_dump_clk_registers(struct clk_state_registers_and_bypass *regs_and_bypass, 238 struct clk_mgr *clk_mgr_base, struct clk_log_info *log_info) 239 { 240 struct dcn301_clk_internal internal = {0}; 241 char *bypass_clks[5] = {"0x0 DFS", "0x1 REFCLK", "0x2 ERROR", "0x3 400 FCH", "0x4 600 FCH"}; 242 unsigned int chars_printed = 0; 243 unsigned int remaining_buffer = log_info->bufSize; 244 245 vg_dump_clk_registers_internal(&internal, clk_mgr_base); 246 247 regs_and_bypass->dcfclk = internal.CLK1_CLK3_CURRENT_CNT / 10; 248 regs_and_bypass->dcf_deep_sleep_divider = internal.CLK1_CLK3_DS_CNTL / 10; 249 regs_and_bypass->dcf_deep_sleep_allow = internal.CLK1_CLK3_ALLOW_DS; 250 regs_and_bypass->dprefclk = internal.CLK1_CLK2_CURRENT_CNT / 10; 251 regs_and_bypass->dispclk = internal.CLK1_CLK0_CURRENT_CNT / 10; 252 regs_and_bypass->dppclk = internal.CLK1_CLK1_CURRENT_CNT / 10; 253 254 regs_and_bypass->dppclk_bypass = internal.CLK1_CLK1_BYPASS_CNTL & 0x0007; 255 if (regs_and_bypass->dppclk_bypass < 0 || regs_and_bypass->dppclk_bypass > 4) 256 regs_and_bypass->dppclk_bypass = 0; 257 regs_and_bypass->dcfclk_bypass = internal.CLK1_CLK3_BYPASS_CNTL & 0x0007; 258 if (regs_and_bypass->dcfclk_bypass < 0 || regs_and_bypass->dcfclk_bypass > 4) 259 regs_and_bypass->dcfclk_bypass = 0; 260 regs_and_bypass->dispclk_bypass = internal.CLK1_CLK0_BYPASS_CNTL & 0x0007; 261 if (regs_and_bypass->dispclk_bypass < 0 || regs_and_bypass->dispclk_bypass > 4) 262 regs_and_bypass->dispclk_bypass = 0; 263 regs_and_bypass->dprefclk_bypass = internal.CLK1_CLK2_BYPASS_CNTL & 0x0007; 264 if (regs_and_bypass->dprefclk_bypass < 0 || regs_and_bypass->dprefclk_bypass > 4) 265 regs_and_bypass->dprefclk_bypass = 0; 266 267 if (log_info->enabled) { 268 chars_printed = snprintf_count(log_info->pBuf, remaining_buffer, "clk_type,clk_value,deepsleep_cntl,deepsleep_allow,bypass\n"); 269 remaining_buffer -= chars_printed; 270 *log_info->sum_chars_printed += chars_printed; 271 log_info->pBuf += chars_printed; 272 273 chars_printed = snprintf_count(log_info->pBuf, remaining_buffer, "dcfclk,%d,%d,%d,%s\n", 274 regs_and_bypass->dcfclk, 275 regs_and_bypass->dcf_deep_sleep_divider, 276 regs_and_bypass->dcf_deep_sleep_allow, 277 bypass_clks[(int) regs_and_bypass->dcfclk_bypass]); 278 remaining_buffer -= chars_printed; 279 *log_info->sum_chars_printed += chars_printed; 280 log_info->pBuf += chars_printed; 281 282 chars_printed = snprintf_count(log_info->pBuf, remaining_buffer, "dprefclk,%d,N/A,N/A,%s\n", 283 regs_and_bypass->dprefclk, 284 bypass_clks[(int) regs_and_bypass->dprefclk_bypass]); 285 remaining_buffer -= chars_printed; 286 *log_info->sum_chars_printed += chars_printed; 287 log_info->pBuf += chars_printed; 288 289 chars_printed = snprintf_count(log_info->pBuf, remaining_buffer, "dispclk,%d,N/A,N/A,%s\n", 290 regs_and_bypass->dispclk, 291 bypass_clks[(int) regs_and_bypass->dispclk_bypass]); 292 remaining_buffer -= chars_printed; 293 *log_info->sum_chars_printed += chars_printed; 294 log_info->pBuf += chars_printed; 295 296 //split 297 chars_printed = snprintf_count(log_info->pBuf, remaining_buffer, "SPLIT\n"); 298 remaining_buffer -= chars_printed; 299 *log_info->sum_chars_printed += chars_printed; 300 log_info->pBuf += chars_printed; 301 302 // REGISTER VALUES 303 chars_printed = snprintf_count(log_info->pBuf, remaining_buffer, "reg_name,value,clk_type\n"); 304 remaining_buffer -= chars_printed; 305 *log_info->sum_chars_printed += chars_printed; 306 log_info->pBuf += chars_printed; 307 308 chars_printed = snprintf_count(log_info->pBuf, remaining_buffer, "CLK1_CLK3_CURRENT_CNT,%d,dcfclk\n", 309 internal.CLK1_CLK3_CURRENT_CNT); 310 remaining_buffer -= chars_printed; 311 *log_info->sum_chars_printed += chars_printed; 312 log_info->pBuf += chars_printed; 313 314 chars_printed = snprintf_count(log_info->pBuf, remaining_buffer, "CLK1_CLK3_DS_CNTL,%d,dcf_deep_sleep_divider\n", 315 internal.CLK1_CLK3_DS_CNTL); 316 remaining_buffer -= chars_printed; 317 *log_info->sum_chars_printed += chars_printed; 318 log_info->pBuf += chars_printed; 319 320 chars_printed = snprintf_count(log_info->pBuf, remaining_buffer, "CLK1_CLK3_ALLOW_DS,%d,dcf_deep_sleep_allow\n", 321 internal.CLK1_CLK3_ALLOW_DS); 322 remaining_buffer -= chars_printed; 323 *log_info->sum_chars_printed += chars_printed; 324 log_info->pBuf += chars_printed; 325 326 chars_printed = snprintf_count(log_info->pBuf, remaining_buffer, "CLK1_CLK2_CURRENT_CNT,%d,dprefclk\n", 327 internal.CLK1_CLK2_CURRENT_CNT); 328 remaining_buffer -= chars_printed; 329 *log_info->sum_chars_printed += chars_printed; 330 log_info->pBuf += chars_printed; 331 332 chars_printed = snprintf_count(log_info->pBuf, remaining_buffer, "CLK1_CLK0_CURRENT_CNT,%d,dispclk\n", 333 internal.CLK1_CLK0_CURRENT_CNT); 334 remaining_buffer -= chars_printed; 335 *log_info->sum_chars_printed += chars_printed; 336 log_info->pBuf += chars_printed; 337 338 chars_printed = snprintf_count(log_info->pBuf, remaining_buffer, "CLK1_CLK1_CURRENT_CNT,%d,dppclk\n", 339 internal.CLK1_CLK1_CURRENT_CNT); 340 remaining_buffer -= chars_printed; 341 *log_info->sum_chars_printed += chars_printed; 342 log_info->pBuf += chars_printed; 343 344 chars_printed = snprintf_count(log_info->pBuf, remaining_buffer, "CLK1_CLK3_BYPASS_CNTL,%d,dcfclk_bypass\n", 345 internal.CLK1_CLK3_BYPASS_CNTL); 346 remaining_buffer -= chars_printed; 347 *log_info->sum_chars_printed += chars_printed; 348 log_info->pBuf += chars_printed; 349 350 chars_printed = snprintf_count(log_info->pBuf, remaining_buffer, "CLK1_CLK2_BYPASS_CNTL,%d,dprefclk_bypass\n", 351 internal.CLK1_CLK2_BYPASS_CNTL); 352 remaining_buffer -= chars_printed; 353 *log_info->sum_chars_printed += chars_printed; 354 log_info->pBuf += chars_printed; 355 356 chars_printed = snprintf_count(log_info->pBuf, remaining_buffer, "CLK1_CLK0_BYPASS_CNTL,%d,dispclk_bypass\n", 357 internal.CLK1_CLK0_BYPASS_CNTL); 358 remaining_buffer -= chars_printed; 359 *log_info->sum_chars_printed += chars_printed; 360 log_info->pBuf += chars_printed; 361 362 chars_printed = snprintf_count(log_info->pBuf, remaining_buffer, "CLK1_CLK1_BYPASS_CNTL,%d,dppclk_bypass\n", 363 internal.CLK1_CLK1_BYPASS_CNTL); 364 remaining_buffer -= chars_printed; 365 *log_info->sum_chars_printed += chars_printed; 366 log_info->pBuf += chars_printed; 367 } 368 } 369 370 /* This function produce translated logical clk state values*/ 371 void vg_get_clk_states(struct clk_mgr *clk_mgr_base, struct clk_states *s) 372 { 373 374 struct clk_state_registers_and_bypass sb = { 0 }; 375 struct clk_log_info log_info = { 0 }; 376 377 vg_dump_clk_registers(&sb, clk_mgr_base, &log_info); 378 379 s->dprefclk_khz = sb.dprefclk * 1000; 380 } 381 382 static void vg_enable_pme_wa(struct clk_mgr *clk_mgr_base) 383 { 384 struct clk_mgr_internal *clk_mgr = TO_CLK_MGR_INTERNAL(clk_mgr_base); 385 386 dcn301_smu_enable_pme_wa(clk_mgr); 387 } 388 389 void vg_init_clocks(struct clk_mgr *clk_mgr) 390 { 391 memset(&(clk_mgr->clks), 0, sizeof(struct dc_clocks)); 392 // Assumption is that boot state always supports pstate 393 clk_mgr->clks.p_state_change_support = true; 394 clk_mgr->clks.prev_p_state_change_support = true; 395 clk_mgr->clks.pwr_state = DCN_PWR_STATE_UNKNOWN; 396 } 397 398 static void vg_build_watermark_ranges(struct clk_bw_params *bw_params, struct watermarks *table) 399 { 400 int i, num_valid_sets; 401 402 num_valid_sets = 0; 403 404 for (i = 0; i < WM_SET_COUNT; i++) { 405 /* skip empty entries, the smu array has no holes*/ 406 if (!bw_params->wm_table.entries[i].valid) 407 continue; 408 409 table->WatermarkRow[WM_DCFCLK][num_valid_sets].WmSetting = bw_params->wm_table.entries[i].wm_inst; 410 table->WatermarkRow[WM_DCFCLK][num_valid_sets].WmType = bw_params->wm_table.entries[i].wm_type; 411 /* We will not select WM based on fclk, so leave it as unconstrained */ 412 table->WatermarkRow[WM_DCFCLK][num_valid_sets].MinClock = 0; 413 table->WatermarkRow[WM_DCFCLK][num_valid_sets].MaxClock = 0xFFFF; 414 415 if (table->WatermarkRow[WM_DCFCLK][num_valid_sets].WmType == WM_TYPE_PSTATE_CHG) { 416 if (i == 0) 417 table->WatermarkRow[WM_DCFCLK][num_valid_sets].MinMclk = 0; 418 else { 419 /* add 1 to make it non-overlapping with next lvl */ 420 table->WatermarkRow[WM_DCFCLK][num_valid_sets].MinMclk = 421 bw_params->clk_table.entries[i - 1].dcfclk_mhz + 1; 422 } 423 table->WatermarkRow[WM_DCFCLK][num_valid_sets].MaxMclk = 424 bw_params->clk_table.entries[i].dcfclk_mhz; 425 426 } else { 427 /* unconstrained for memory retraining */ 428 table->WatermarkRow[WM_DCFCLK][num_valid_sets].MinClock = 0; 429 table->WatermarkRow[WM_DCFCLK][num_valid_sets].MaxClock = 0xFFFF; 430 431 /* Modify previous watermark range to cover up to max */ 432 table->WatermarkRow[WM_DCFCLK][num_valid_sets - 1].MaxClock = 0xFFFF; 433 } 434 num_valid_sets++; 435 } 436 437 ASSERT(num_valid_sets != 0); /* Must have at least one set of valid watermarks */ 438 439 /* modify the min and max to make sure we cover the whole range*/ 440 table->WatermarkRow[WM_DCFCLK][0].MinMclk = 0; 441 table->WatermarkRow[WM_DCFCLK][0].MinClock = 0; 442 table->WatermarkRow[WM_DCFCLK][num_valid_sets - 1].MaxMclk = 0xFFFF; 443 table->WatermarkRow[WM_DCFCLK][num_valid_sets - 1].MaxClock = 0xFFFF; 444 445 /* This is for writeback only, does not matter currently as no writeback support*/ 446 table->WatermarkRow[WM_SOCCLK][0].WmSetting = WM_A; 447 table->WatermarkRow[WM_SOCCLK][0].MinClock = 0; 448 table->WatermarkRow[WM_SOCCLK][0].MaxClock = 0xFFFF; 449 table->WatermarkRow[WM_SOCCLK][0].MinMclk = 0; 450 table->WatermarkRow[WM_SOCCLK][0].MaxMclk = 0xFFFF; 451 } 452 453 454 static void vg_notify_wm_ranges(struct clk_mgr *clk_mgr_base) 455 { 456 struct clk_mgr_internal *clk_mgr = TO_CLK_MGR_INTERNAL(clk_mgr_base); 457 struct clk_mgr_vgh *clk_mgr_vgh = TO_CLK_MGR_VGH(clk_mgr); 458 struct watermarks *table = clk_mgr_vgh->smu_wm_set.wm_set; 459 460 if (!clk_mgr->smu_ver) 461 return; 462 463 if (!table || clk_mgr_vgh->smu_wm_set.mc_address.quad_part == 0) 464 return; 465 466 memset(table, 0, sizeof(*table)); 467 468 vg_build_watermark_ranges(clk_mgr_base->bw_params, table); 469 470 dcn301_smu_set_dram_addr_high(clk_mgr, 471 clk_mgr_vgh->smu_wm_set.mc_address.high_part); 472 dcn301_smu_set_dram_addr_low(clk_mgr, 473 clk_mgr_vgh->smu_wm_set.mc_address.low_part); 474 dcn301_smu_transfer_wm_table_dram_2_smu(clk_mgr); 475 } 476 477 static bool vg_are_clock_states_equal(struct dc_clocks *a, 478 struct dc_clocks *b) 479 { 480 if (a->dispclk_khz != b->dispclk_khz) 481 return false; 482 else if (a->dppclk_khz != b->dppclk_khz) 483 return false; 484 else if (a->dcfclk_khz != b->dcfclk_khz) 485 return false; 486 else if (a->dcfclk_deep_sleep_khz != b->dcfclk_deep_sleep_khz) 487 return false; 488 489 return true; 490 } 491 492 493 static struct clk_mgr_funcs vg_funcs = { 494 .get_dp_ref_clk_frequency = dce12_get_dp_ref_freq_khz, 495 .update_clocks = vg_update_clocks, 496 .init_clocks = vg_init_clocks, 497 .enable_pme_wa = vg_enable_pme_wa, 498 .are_clock_states_equal = vg_are_clock_states_equal, 499 .notify_wm_ranges = vg_notify_wm_ranges 500 }; 501 502 static struct clk_bw_params vg_bw_params = { 503 .vram_type = Ddr4MemType, 504 .num_channels = 1, 505 .clk_table = { 506 .entries = { 507 { 508 .voltage = 0, 509 .dcfclk_mhz = 400, 510 .fclk_mhz = 400, 511 .memclk_mhz = 800, 512 .socclk_mhz = 0, 513 }, 514 { 515 .voltage = 0, 516 .dcfclk_mhz = 483, 517 .fclk_mhz = 800, 518 .memclk_mhz = 1600, 519 .socclk_mhz = 0, 520 }, 521 { 522 .voltage = 0, 523 .dcfclk_mhz = 602, 524 .fclk_mhz = 1067, 525 .memclk_mhz = 1067, 526 .socclk_mhz = 0, 527 }, 528 { 529 .voltage = 0, 530 .dcfclk_mhz = 738, 531 .fclk_mhz = 1333, 532 .memclk_mhz = 1600, 533 .socclk_mhz = 0, 534 }, 535 }, 536 537 .num_entries = 4, 538 }, 539 540 }; 541 542 static struct wm_table ddr4_wm_table = { 543 .entries = { 544 { 545 .wm_inst = WM_A, 546 .wm_type = WM_TYPE_PSTATE_CHG, 547 .pstate_latency_us = 11.72, 548 .sr_exit_time_us = 6.09, 549 .sr_enter_plus_exit_time_us = 7.14, 550 .valid = true, 551 }, 552 { 553 .wm_inst = WM_B, 554 .wm_type = WM_TYPE_PSTATE_CHG, 555 .pstate_latency_us = 11.72, 556 .sr_exit_time_us = 10.12, 557 .sr_enter_plus_exit_time_us = 11.48, 558 .valid = true, 559 }, 560 { 561 .wm_inst = WM_C, 562 .wm_type = WM_TYPE_PSTATE_CHG, 563 .pstate_latency_us = 11.72, 564 .sr_exit_time_us = 10.12, 565 .sr_enter_plus_exit_time_us = 11.48, 566 .valid = true, 567 }, 568 { 569 .wm_inst = WM_D, 570 .wm_type = WM_TYPE_PSTATE_CHG, 571 .pstate_latency_us = 11.72, 572 .sr_exit_time_us = 10.12, 573 .sr_enter_plus_exit_time_us = 11.48, 574 .valid = true, 575 }, 576 } 577 }; 578 579 static struct wm_table lpddr5_wm_table = { 580 .entries = { 581 { 582 .wm_inst = WM_A, 583 .wm_type = WM_TYPE_PSTATE_CHG, 584 .pstate_latency_us = 11.65333, 585 .sr_exit_time_us = 7.95, 586 .sr_enter_plus_exit_time_us = 9, 587 .valid = true, 588 }, 589 { 590 .wm_inst = WM_B, 591 .wm_type = WM_TYPE_PSTATE_CHG, 592 .pstate_latency_us = 11.65333, 593 .sr_exit_time_us = 9.82, 594 .sr_enter_plus_exit_time_us = 11.196, 595 .valid = true, 596 }, 597 { 598 .wm_inst = WM_C, 599 .wm_type = WM_TYPE_PSTATE_CHG, 600 .pstate_latency_us = 11.65333, 601 .sr_exit_time_us = 9.89, 602 .sr_enter_plus_exit_time_us = 11.24, 603 .valid = true, 604 }, 605 { 606 .wm_inst = WM_D, 607 .wm_type = WM_TYPE_PSTATE_CHG, 608 .pstate_latency_us = 11.65333, 609 .sr_exit_time_us = 9.748, 610 .sr_enter_plus_exit_time_us = 11.102, 611 .valid = true, 612 }, 613 } 614 }; 615 616 617 static unsigned int find_dcfclk_for_voltage(const struct vg_dpm_clocks *clock_table, 618 unsigned int voltage) 619 { 620 int i; 621 622 for (i = 0; i < VG_NUM_SOC_VOLTAGE_LEVELS; i++) { 623 if (clock_table->SocVoltage[i] == voltage) 624 return clock_table->DcfClocks[i]; 625 } 626 627 ASSERT(0); 628 return 0; 629 } 630 631 static void vg_clk_mgr_helper_populate_bw_params( 632 struct clk_mgr_internal *clk_mgr, 633 struct integrated_info *bios_info, 634 const struct vg_dpm_clocks *clock_table) 635 { 636 int i, j; 637 struct clk_bw_params *bw_params = clk_mgr->base.bw_params; 638 639 j = -1; 640 641 ASSERT(VG_NUM_FCLK_DPM_LEVELS <= MAX_NUM_DPM_LVL); 642 643 /* Find lowest DPM, FCLK is filled in reverse order*/ 644 645 for (i = VG_NUM_FCLK_DPM_LEVELS - 1; i >= 0; i--) { 646 if (clock_table->DfPstateTable[i].fclk != 0) { 647 j = i; 648 break; 649 } 650 } 651 652 if (j == -1) { 653 /* clock table is all 0s, just use our own hardcode */ 654 ASSERT(0); 655 return; 656 } 657 658 bw_params->clk_table.num_entries = j + 1; 659 660 for (i = 0; i < bw_params->clk_table.num_entries; i++, j--) { 661 bw_params->clk_table.entries[i].fclk_mhz = clock_table->DfPstateTable[j].fclk; 662 bw_params->clk_table.entries[i].memclk_mhz = clock_table->DfPstateTable[j].memclk; 663 bw_params->clk_table.entries[i].voltage = clock_table->DfPstateTable[j].voltage; 664 bw_params->clk_table.entries[i].dcfclk_mhz = find_dcfclk_for_voltage(clock_table, clock_table->DfPstateTable[j].voltage); 665 } 666 667 bw_params->vram_type = bios_info->memory_type; 668 bw_params->num_channels = bios_info->ma_channel_number; 669 670 for (i = 0; i < WM_SET_COUNT; i++) { 671 bw_params->wm_table.entries[i].wm_inst = i; 672 673 if (i >= bw_params->clk_table.num_entries) { 674 bw_params->wm_table.entries[i].valid = false; 675 continue; 676 } 677 678 bw_params->wm_table.entries[i].wm_type = WM_TYPE_PSTATE_CHG; 679 bw_params->wm_table.entries[i].valid = true; 680 } 681 682 if (bw_params->vram_type == LpDdr4MemType) { 683 /* 684 * WM set D will be re-purposed for memory retraining 685 */ 686 bw_params->wm_table.entries[WM_D].pstate_latency_us = LPDDR_MEM_RETRAIN_LATENCY; 687 bw_params->wm_table.entries[WM_D].wm_inst = WM_D; 688 bw_params->wm_table.entries[WM_D].wm_type = WM_TYPE_RETRAINING; 689 bw_params->wm_table.entries[WM_D].valid = true; 690 } 691 692 } 693 694 /* Temporary Place holder until we can get them from fuse */ 695 static struct vg_dpm_clocks dummy_clocks = { 696 .DcfClocks = { 201, 403, 403, 403, 403, 403, 403 }, 697 .SocClocks = { 400, 600, 600, 600, 600, 600, 600 }, 698 .SocVoltage = { 2800, 2860, 2860, 2860, 2860, 2860, 2860, 2860 }, 699 .DfPstateTable = { 700 { .fclk = 400, .memclk = 400, .voltage = 2800 }, 701 { .fclk = 400, .memclk = 400, .voltage = 2800 }, 702 { .fclk = 400, .memclk = 400, .voltage = 2800 }, 703 { .fclk = 400, .memclk = 400, .voltage = 2800 } 704 } 705 }; 706 707 static struct watermarks dummy_wms = { 0 }; 708 709 static void vg_get_dpm_table_from_smu(struct clk_mgr_internal *clk_mgr, 710 struct smu_dpm_clks *smu_dpm_clks) 711 { 712 struct vg_dpm_clocks *table = smu_dpm_clks->dpm_clks; 713 714 if (!clk_mgr->smu_ver) 715 return; 716 717 if (!table || smu_dpm_clks->mc_address.quad_part == 0) 718 return; 719 720 memset(table, 0, sizeof(*table)); 721 722 dcn301_smu_set_dram_addr_high(clk_mgr, 723 smu_dpm_clks->mc_address.high_part); 724 dcn301_smu_set_dram_addr_low(clk_mgr, 725 smu_dpm_clks->mc_address.low_part); 726 dcn301_smu_transfer_dpm_table_smu_2_dram(clk_mgr); 727 } 728 729 void vg_clk_mgr_construct( 730 struct dc_context *ctx, 731 struct clk_mgr_vgh *clk_mgr, 732 struct pp_smu_funcs *pp_smu, 733 struct dccg *dccg) 734 { 735 struct smu_dpm_clks smu_dpm_clks = { 0 }; 736 737 clk_mgr->base.base.ctx = ctx; 738 clk_mgr->base.base.funcs = &vg_funcs; 739 740 clk_mgr->base.pp_smu = pp_smu; 741 742 clk_mgr->base.dccg = dccg; 743 clk_mgr->base.dfs_bypass_disp_clk = 0; 744 745 clk_mgr->base.dprefclk_ss_percentage = 0; 746 clk_mgr->base.dprefclk_ss_divider = 1000; 747 clk_mgr->base.ss_on_dprefclk = false; 748 clk_mgr->base.dfs_ref_freq_khz = 48000; 749 750 clk_mgr->smu_wm_set.wm_set = (struct watermarks *)dm_helpers_allocate_gpu_mem( 751 clk_mgr->base.base.ctx, 752 DC_MEM_ALLOC_TYPE_FRAME_BUFFER, 753 sizeof(struct watermarks), 754 &clk_mgr->smu_wm_set.mc_address.quad_part); 755 756 if (clk_mgr->smu_wm_set.wm_set == 0) { 757 clk_mgr->smu_wm_set.wm_set = &dummy_wms; 758 clk_mgr->smu_wm_set.mc_address.quad_part = 0; 759 } 760 ASSERT(clk_mgr->smu_wm_set.wm_set); 761 762 smu_dpm_clks.dpm_clks = (struct vg_dpm_clocks *)dm_helpers_allocate_gpu_mem( 763 clk_mgr->base.base.ctx, 764 DC_MEM_ALLOC_TYPE_FRAME_BUFFER, 765 sizeof(struct vg_dpm_clocks), 766 &smu_dpm_clks.mc_address.quad_part); 767 768 if (smu_dpm_clks.dpm_clks == NULL) { 769 smu_dpm_clks.dpm_clks = &dummy_clocks; 770 smu_dpm_clks.mc_address.quad_part = 0; 771 } 772 773 ASSERT(smu_dpm_clks.dpm_clks); 774 775 if (IS_FPGA_MAXIMUS_DC(ctx->dce_environment)) { 776 vg_funcs.update_clocks = dcn2_update_clocks_fpga; 777 clk_mgr->base.base.dentist_vco_freq_khz = 3600000; 778 } else { 779 struct clk_log_info log_info = {0}; 780 781 clk_mgr->base.smu_ver = dcn301_smu_get_smu_version(&clk_mgr->base); 782 783 if (clk_mgr->base.smu_ver) 784 clk_mgr->base.smu_present = true; 785 786 /* TODO: Check we get what we expect during bringup */ 787 clk_mgr->base.base.dentist_vco_freq_khz = get_vco_frequency_from_reg(&clk_mgr->base); 788 789 /* in case we don't get a value from the register, use default */ 790 if (clk_mgr->base.base.dentist_vco_freq_khz == 0) 791 clk_mgr->base.base.dentist_vco_freq_khz = 3600000; 792 793 if (ctx->dc_bios->integrated_info->memory_type == LpDdr5MemType) { 794 vg_bw_params.wm_table = lpddr5_wm_table; 795 } else { 796 vg_bw_params.wm_table = ddr4_wm_table; 797 } 798 /* Saved clocks configured at boot for debug purposes */ 799 vg_dump_clk_registers(&clk_mgr->base.base.boot_snapshot, &clk_mgr->base.base, &log_info); 800 } 801 802 clk_mgr->base.base.dprefclk_khz = 600000; 803 dce_clock_read_ss_info(&clk_mgr->base); 804 805 clk_mgr->base.base.bw_params = &vg_bw_params; 806 807 vg_get_dpm_table_from_smu(&clk_mgr->base, &smu_dpm_clks); 808 if (ctx->dc_bios && ctx->dc_bios->integrated_info) { 809 vg_clk_mgr_helper_populate_bw_params( 810 &clk_mgr->base, 811 ctx->dc_bios->integrated_info, 812 smu_dpm_clks.dpm_clks); 813 } 814 815 if (smu_dpm_clks.dpm_clks && smu_dpm_clks.mc_address.quad_part != 0) 816 dm_helpers_free_gpu_mem(clk_mgr->base.base.ctx, DC_MEM_ALLOC_TYPE_FRAME_BUFFER, 817 smu_dpm_clks.dpm_clks); 818 /* 819 if (!IS_FPGA_MAXIMUS_DC(ctx->dce_environment) && clk_mgr->base.smu_ver) { 820 enable powerfeatures when displaycount goes to 0 821 dcn301_smu_enable_phy_refclk_pwrdwn(clk_mgr, !debug->disable_48mhz_pwrdwn); 822 } 823 */ 824 } 825 826 void vg_clk_mgr_destroy(struct clk_mgr_internal *clk_mgr_int) 827 { 828 struct clk_mgr_vgh *clk_mgr = TO_CLK_MGR_VGH(clk_mgr_int); 829 830 if (clk_mgr->smu_wm_set.wm_set && clk_mgr->smu_wm_set.mc_address.quad_part != 0) 831 dm_helpers_free_gpu_mem(clk_mgr_int->base.ctx, DC_MEM_ALLOC_TYPE_FRAME_BUFFER, 832 clk_mgr->smu_wm_set.wm_set); 833 } 834