1 /* 2 * Copyright 2020 Advanced Micro Devices, Inc. 3 * 4 * Permission is hereby granted, free of charge, to any person obtaining a 5 * copy of this software and associated documentation files (the "Software"), 6 * to deal in the Software without restriction, including without limitation 7 * the rights to use, copy, modify, merge, publish, distribute, sublicense, 8 * and/or sell copies of the Software, and to permit persons to whom the 9 * Software is furnished to do so, subject to the following conditions: 10 * 11 * The above copyright notice and this permission notice shall be included in 12 * all copies or substantial portions of the Software. 13 * 14 * THE SOFTWARE IS PROVIDED "AS IS", WITHOUT WARRANTY OF ANY KIND, EXPRESS OR 15 * IMPLIED, INCLUDING BUT NOT LIMITED TO THE WARRANTIES OF MERCHANTABILITY, 16 * FITNESS FOR A PARTICULAR PURPOSE AND NONINFRINGEMENT. IN NO EVENT SHALL 17 * THE COPYRIGHT HOLDER(S) OR AUTHOR(S) BE LIABLE FOR ANY CLAIM, DAMAGES OR 18 * OTHER LIABILITY, WHETHER IN AN ACTION OF CONTRACT, TORT OR OTHERWISE, 19 * ARISING FROM, OUT OF OR IN CONNECTION WITH THE SOFTWARE OR THE USE OR 20 * OTHER DEALINGS IN THE SOFTWARE. 21 * 22 * Authors: AMD 23 * 24 */ 25 26 #include "dccg.h" 27 #include "clk_mgr_internal.h" 28 29 #include "dcn30_clk_mgr_smu_msg.h" 30 #include "dcn20/dcn20_clk_mgr.h" 31 #include "dce100/dce_clk_mgr.h" 32 #include "reg_helper.h" 33 #include "core_types.h" 34 #include "dm_helpers.h" 35 36 #include "atomfirmware.h" 37 38 39 #include "sienna_cichlid_ip_offset.h" 40 #include "dcn/dcn_3_0_0_offset.h" 41 #include "dcn/dcn_3_0_0_sh_mask.h" 42 43 #include "nbio/nbio_7_4_offset.h" 44 45 #include "dcn/dpcs_3_0_0_offset.h" 46 #include "dcn/dpcs_3_0_0_sh_mask.h" 47 48 #include "mmhub/mmhub_2_0_0_offset.h" 49 #include "mmhub/mmhub_2_0_0_sh_mask.h" 50 /*we don't have clk folder yet*/ 51 #include "dcn30/dcn30_clk_mgr.h" 52 53 #undef FN 54 #define FN(reg_name, field_name) \ 55 clk_mgr->clk_mgr_shift->field_name, clk_mgr->clk_mgr_mask->field_name 56 57 #define REG(reg) \ 58 (clk_mgr->regs->reg) 59 60 #define BASE_INNER(seg) DCN_BASE__INST0_SEG ## seg 61 62 #define BASE(seg) BASE_INNER(seg) 63 64 #define SR(reg_name)\ 65 .reg_name = BASE(mm ## reg_name ## _BASE_IDX) + \ 66 mm ## reg_name 67 68 #undef CLK_SRI 69 #define CLK_SRI(reg_name, block, inst)\ 70 .reg_name = mm ## block ## _ ## reg_name 71 72 static const struct clk_mgr_registers clk_mgr_regs = { 73 CLK_REG_LIST_DCN3() 74 }; 75 76 static const struct clk_mgr_shift clk_mgr_shift = { 77 CLK_COMMON_MASK_SH_LIST_DCN20_BASE(__SHIFT) 78 }; 79 80 static const struct clk_mgr_mask clk_mgr_mask = { 81 CLK_COMMON_MASK_SH_LIST_DCN20_BASE(_MASK) 82 }; 83 84 85 /* Query SMU for all clock states for a particular clock */ 86 static void dcn3_init_single_clock(struct clk_mgr_internal *clk_mgr, PPCLK_e clk, unsigned int *entry_0, unsigned int *num_levels) 87 { 88 unsigned int i; 89 char *entry_i = (char *)entry_0; 90 uint32_t ret = dcn30_smu_get_dpm_freq_by_index(clk_mgr, clk, 0xFF); 91 92 if (ret & (1 << 31)) 93 /* fine-grained, only min and max */ 94 *num_levels = 2; 95 else 96 /* discrete, a number of fixed states */ 97 /* will set num_levels to 0 on failure */ 98 *num_levels = ret & 0xFF; 99 100 /* if the initial message failed, num_levels will be 0 */ 101 for (i = 0; i < *num_levels; i++) { 102 *((unsigned int *)entry_i) = (dcn30_smu_get_dpm_freq_by_index(clk_mgr, clk, i) & 0xFFFF); 103 entry_i += sizeof(clk_mgr->base.bw_params->clk_table.entries[0]); 104 } 105 } 106 107 static void dcn3_build_wm_range_table(struct clk_mgr_internal *clk_mgr) 108 { 109 /* defaults */ 110 double pstate_latency_us = clk_mgr->base.ctx->dc->dml.soc.dram_clock_change_latency_us; 111 double sr_exit_time_us = clk_mgr->base.ctx->dc->dml.soc.sr_exit_time_us; 112 double sr_enter_plus_exit_time_us = clk_mgr->base.ctx->dc->dml.soc.sr_enter_plus_exit_time_us; 113 uint16_t min_uclk_mhz = clk_mgr->base.bw_params->clk_table.entries[0].memclk_mhz; 114 115 /* Set A - Normal - default values*/ 116 clk_mgr->base.bw_params->wm_table.nv_entries[WM_A].valid = true; 117 clk_mgr->base.bw_params->wm_table.nv_entries[WM_A].dml_input.pstate_latency_us = pstate_latency_us; 118 clk_mgr->base.bw_params->wm_table.nv_entries[WM_A].dml_input.sr_exit_time_us = sr_exit_time_us; 119 clk_mgr->base.bw_params->wm_table.nv_entries[WM_A].dml_input.sr_enter_plus_exit_time_us = sr_enter_plus_exit_time_us; 120 clk_mgr->base.bw_params->wm_table.nv_entries[WM_A].pmfw_breakdown.wm_type = WATERMARKS_CLOCK_RANGE; 121 clk_mgr->base.bw_params->wm_table.nv_entries[WM_A].pmfw_breakdown.min_dcfclk = 0; 122 clk_mgr->base.bw_params->wm_table.nv_entries[WM_A].pmfw_breakdown.max_dcfclk = 0xFFFF; 123 clk_mgr->base.bw_params->wm_table.nv_entries[WM_A].pmfw_breakdown.min_uclk = min_uclk_mhz; 124 clk_mgr->base.bw_params->wm_table.nv_entries[WM_A].pmfw_breakdown.max_uclk = 0xFFFF; 125 126 /* Set B - Performance - higher minimum clocks */ 127 // clk_mgr->base.bw_params->wm_table.nv_entries[WM_B].valid = true; 128 // clk_mgr->base.bw_params->wm_table.nv_entries[WM_B].dml_input.pstate_latency_us = pstate_latency_us; 129 // clk_mgr->base.bw_params->wm_table.nv_entries[WM_B].dml_input.sr_exit_time_us = sr_exit_time_us; 130 // clk_mgr->base.bw_params->wm_table.nv_entries[WM_B].dml_input.sr_enter_plus_exit_time_us = sr_enter_plus_exit_time_us; 131 // clk_mgr->base.bw_params->wm_table.nv_entries[WM_B].pmfw_breakdown.wm_type = WATERMARKS_CLOCK_RANGE; 132 // clk_mgr->base.bw_params->wm_table.nv_entries[WM_B].pmfw_breakdown.min_dcfclk = TUNED VALUE; 133 // clk_mgr->base.bw_params->wm_table.nv_entries[WM_B].pmfw_breakdown.max_dcfclk = 0xFFFF; 134 // clk_mgr->base.bw_params->wm_table.nv_entries[WM_B].pmfw_breakdown.min_uclk = TUNED VALUE; 135 // clk_mgr->base.bw_params->wm_table.nv_entries[WM_B].pmfw_breakdown.max_uclk = 0xFFFF; 136 137 /* Set C - Dummy P-State - P-State latency set to "dummy p-state" value */ 138 clk_mgr->base.bw_params->wm_table.nv_entries[WM_C].valid = true; 139 clk_mgr->base.bw_params->wm_table.nv_entries[WM_C].dml_input.pstate_latency_us = clk_mgr->base.ctx->dc->dml.soc.dummy_pstate_latency_us; 140 clk_mgr->base.bw_params->wm_table.nv_entries[WM_C].dml_input.sr_exit_time_us = sr_exit_time_us; 141 clk_mgr->base.bw_params->wm_table.nv_entries[WM_C].dml_input.sr_enter_plus_exit_time_us = sr_enter_plus_exit_time_us; 142 clk_mgr->base.bw_params->wm_table.nv_entries[WM_C].pmfw_breakdown.wm_type = WATERMARKS_DUMMY_PSTATE; 143 clk_mgr->base.bw_params->wm_table.nv_entries[WM_C].pmfw_breakdown.min_dcfclk = 0; 144 clk_mgr->base.bw_params->wm_table.nv_entries[WM_C].pmfw_breakdown.max_dcfclk = 0xFFFF; 145 clk_mgr->base.bw_params->wm_table.nv_entries[WM_C].pmfw_breakdown.min_uclk = min_uclk_mhz; 146 clk_mgr->base.bw_params->wm_table.nv_entries[WM_C].pmfw_breakdown.max_uclk = 0xFFFF; 147 148 } 149 150 void dcn3_init_clocks(struct clk_mgr *clk_mgr_base) 151 { 152 struct clk_mgr_internal *clk_mgr = TO_CLK_MGR_INTERNAL(clk_mgr_base); 153 unsigned int num_levels; 154 155 memset(&(clk_mgr_base->clks), 0, sizeof(struct dc_clocks)); 156 clk_mgr_base->clks.p_state_change_support = true; 157 clk_mgr_base->clks.prev_p_state_change_support = true; 158 clk_mgr->smu_present = false; 159 160 if (!clk_mgr_base->bw_params) 161 return; 162 163 if (!clk_mgr_base->force_smu_not_present && dcn30_smu_get_smu_version(clk_mgr, &clk_mgr->smu_ver)) 164 clk_mgr->smu_present = true; 165 166 if (!clk_mgr->smu_present) 167 return; 168 169 // do we fail if these fail? if so, how? do we not care to check? 170 dcn30_smu_check_driver_if_version(clk_mgr); 171 dcn30_smu_check_msg_header_version(clk_mgr); 172 173 /* DCFCLK */ 174 dcn3_init_single_clock(clk_mgr, PPCLK_DCEFCLK, 175 &clk_mgr_base->bw_params->clk_table.entries[0].dcfclk_mhz, 176 &num_levels); 177 178 /* DTBCLK */ 179 dcn3_init_single_clock(clk_mgr, PPCLK_DTBCLK, 180 &clk_mgr_base->bw_params->clk_table.entries[0].dtbclk_mhz, 181 &num_levels); 182 183 // DPREFCLK ??? 184 185 /* DISPCLK */ 186 dcn3_init_single_clock(clk_mgr, PPCLK_DISPCLK, 187 &clk_mgr_base->bw_params->clk_table.entries[0].dispclk_mhz, 188 &num_levels); 189 190 /* DPPCLK */ 191 dcn3_init_single_clock(clk_mgr, PPCLK_PIXCLK, 192 &clk_mgr_base->bw_params->clk_table.entries[0].dppclk_mhz, 193 &num_levels); 194 195 /* PHYCLK */ 196 dcn3_init_single_clock(clk_mgr, PPCLK_PHYCLK, 197 &clk_mgr_base->bw_params->clk_table.entries[0].phyclk_mhz, 198 &num_levels); 199 200 /* Get UCLK, update bounding box */ 201 clk_mgr_base->funcs->get_memclk_states_from_smu(clk_mgr_base); 202 203 /* WM range table */ 204 dcn3_build_wm_range_table(clk_mgr); 205 } 206 207 static int dcn30_get_vco_frequency_from_reg(struct clk_mgr_internal *clk_mgr) 208 { 209 /* get FbMult value */ 210 struct fixed31_32 pll_req; 211 /* get FbMult value */ 212 uint32_t pll_req_reg = REG_READ(CLK0_CLK_PLL_REQ); 213 214 /* set up a fixed-point number 215 * this works because the int part is on the right edge of the register 216 * and the frac part is on the left edge 217 */ 218 pll_req = dc_fixpt_from_int(pll_req_reg & clk_mgr->clk_mgr_mask->FbMult_int); 219 pll_req.value |= pll_req_reg & clk_mgr->clk_mgr_mask->FbMult_frac; 220 221 /* multiply by REFCLK period */ 222 pll_req = dc_fixpt_mul_int(pll_req, clk_mgr->dfs_ref_freq_khz); 223 224 return dc_fixpt_floor(pll_req); 225 } 226 227 static void dcn3_update_clocks(struct clk_mgr *clk_mgr_base, 228 struct dc_state *context, 229 bool safe_to_lower) 230 { 231 struct clk_mgr_internal *clk_mgr = TO_CLK_MGR_INTERNAL(clk_mgr_base); 232 struct dc_clocks *new_clocks = &context->bw_ctx.bw.dcn.clk; 233 struct dc *dc = clk_mgr_base->ctx->dc; 234 int display_count; 235 bool update_dppclk = false; 236 bool update_dispclk = false; 237 bool enter_display_off = false; 238 bool dpp_clock_lowered = false; 239 struct dmcu *dmcu = clk_mgr_base->ctx->dc->res_pool->dmcu; 240 bool force_reset = false; 241 bool update_uclk = false; 242 243 if (dc->work_arounds.skip_clock_update || !clk_mgr->smu_present) 244 return; 245 246 if (clk_mgr_base->clks.dispclk_khz == 0 || 247 (dc->debug.force_clock_mode & 0x1)) { 248 /* this is from resume or boot up, if forced_clock cfg option used, we bypass program dispclk and DPPCLK, but need set them for S3. */ 249 force_reset = true; 250 251 dcn2_read_clocks_from_hw_dentist(clk_mgr_base); 252 253 /* force_clock_mode 0x1: force reset the clock even it is the same clock as long as it is in Passive level. */ 254 } 255 display_count = clk_mgr_helper_get_active_display_cnt(dc, context); 256 257 if (display_count == 0) 258 enter_display_off = true; 259 260 if (enter_display_off == safe_to_lower) 261 dcn30_smu_set_num_of_displays(clk_mgr, display_count); 262 263 if (dc->debug.force_min_dcfclk_mhz > 0) 264 new_clocks->dcfclk_khz = (new_clocks->dcfclk_khz > (dc->debug.force_min_dcfclk_mhz * 1000)) ? 265 new_clocks->dcfclk_khz : (dc->debug.force_min_dcfclk_mhz * 1000); 266 267 if (should_set_clock(safe_to_lower, new_clocks->dcfclk_khz, clk_mgr_base->clks.dcfclk_khz)) { 268 clk_mgr_base->clks.dcfclk_khz = new_clocks->dcfclk_khz; 269 dcn30_smu_set_hard_min_by_freq(clk_mgr, PPCLK_DCEFCLK, clk_mgr_base->clks.dcfclk_khz / 1000); 270 } 271 272 if (should_set_clock(safe_to_lower, new_clocks->dcfclk_deep_sleep_khz, clk_mgr_base->clks.dcfclk_deep_sleep_khz)) { 273 clk_mgr_base->clks.dcfclk_deep_sleep_khz = new_clocks->dcfclk_deep_sleep_khz; 274 dcn30_smu_set_min_deep_sleep_dcef_clk(clk_mgr, clk_mgr_base->clks.dcfclk_deep_sleep_khz / 1000); 275 } 276 277 if (should_set_clock(safe_to_lower, new_clocks->socclk_khz, clk_mgr_base->clks.socclk_khz)) 278 /* We don't actually care about socclk, don't notify SMU of hard min */ 279 clk_mgr_base->clks.socclk_khz = new_clocks->socclk_khz; 280 281 clk_mgr_base->clks.prev_p_state_change_support = clk_mgr_base->clks.p_state_change_support; 282 if (should_update_pstate_support(safe_to_lower, new_clocks->p_state_change_support, clk_mgr_base->clks.p_state_change_support)) { 283 clk_mgr_base->clks.p_state_change_support = new_clocks->p_state_change_support; 284 285 /* to disable P-State switching, set UCLK min = max */ 286 if (!clk_mgr_base->clks.p_state_change_support) 287 dcn30_smu_set_hard_min_by_freq(clk_mgr, PPCLK_UCLK, 288 clk_mgr_base->bw_params->clk_table.entries[clk_mgr_base->bw_params->clk_table.num_entries - 1].memclk_mhz); 289 } 290 291 /* Always update saved value, even if new value not set due to P-State switching unsupported */ 292 if (should_set_clock(safe_to_lower, new_clocks->dramclk_khz, clk_mgr_base->clks.dramclk_khz)) { 293 clk_mgr_base->clks.dramclk_khz = new_clocks->dramclk_khz; 294 update_uclk = true; 295 } 296 297 /* set UCLK to requested value if P-State switching is supported, or to re-enable P-State switching */ 298 if (clk_mgr_base->clks.p_state_change_support && 299 (update_uclk || !clk_mgr_base->clks.prev_p_state_change_support)) 300 dcn30_smu_set_hard_min_by_freq(clk_mgr, PPCLK_UCLK, clk_mgr_base->clks.dramclk_khz / 1000); 301 302 if (should_set_clock(safe_to_lower, new_clocks->dppclk_khz, clk_mgr_base->clks.dppclk_khz)) { 303 if (clk_mgr_base->clks.dppclk_khz > new_clocks->dppclk_khz) 304 dpp_clock_lowered = true; 305 306 clk_mgr_base->clks.dppclk_khz = new_clocks->dppclk_khz; 307 dcn30_smu_set_hard_min_by_freq(clk_mgr, PPCLK_PIXCLK, clk_mgr_base->clks.dppclk_khz / 1000); 308 update_dppclk = true; 309 } 310 311 if (should_set_clock(safe_to_lower, new_clocks->dispclk_khz, clk_mgr_base->clks.dispclk_khz)) { 312 clk_mgr_base->clks.dispclk_khz = new_clocks->dispclk_khz; 313 dcn30_smu_set_hard_min_by_freq(clk_mgr, PPCLK_DISPCLK, clk_mgr_base->clks.dispclk_khz / 1000); 314 update_dispclk = true; 315 } 316 317 if (dc->config.forced_clocks == false || (force_reset && safe_to_lower)) { 318 if (dpp_clock_lowered) { 319 /* if clock is being lowered, increase DTO before lowering refclk */ 320 dcn20_update_clocks_update_dpp_dto(clk_mgr, context, safe_to_lower); 321 dcn20_update_clocks_update_dentist(clk_mgr); 322 } else { 323 /* if clock is being raised, increase refclk before lowering DTO */ 324 if (update_dppclk || update_dispclk) 325 dcn20_update_clocks_update_dentist(clk_mgr); 326 /* There is a check inside dcn20_update_clocks_update_dpp_dto which ensures 327 * that we do not lower dto when it is not safe to lower. We do not need to 328 * compare the current and new dppclk before calling this function.*/ 329 dcn20_update_clocks_update_dpp_dto(clk_mgr, context, safe_to_lower); 330 } 331 } 332 333 if (update_dispclk && dmcu && dmcu->funcs->is_dmcu_initialized(dmcu)) 334 /*update dmcu for wait_loop count*/ 335 dmcu->funcs->set_psr_wait_loop(dmcu, 336 clk_mgr_base->clks.dispclk_khz / 1000 / 7); 337 } 338 339 340 static void dcn3_notify_wm_ranges(struct clk_mgr *clk_mgr_base) 341 { 342 unsigned int i; 343 struct clk_mgr_internal *clk_mgr = TO_CLK_MGR_INTERNAL(clk_mgr_base); 344 WatermarksExternal_t *table = (WatermarksExternal_t *) clk_mgr->wm_range_table; 345 346 if (!clk_mgr->smu_present) 347 return; 348 349 if (!table) 350 // should log failure 351 return; 352 353 memset(table, 0, sizeof(*table)); 354 355 /* collect valid ranges, place in pmfw table */ 356 for (i = 0; i < WM_SET_COUNT; i++) 357 if (clk_mgr->base.bw_params->wm_table.nv_entries[i].valid) { 358 table->Watermarks.WatermarkRow[WM_DCEFCLK][i].MinClock = clk_mgr->base.bw_params->wm_table.nv_entries[i].pmfw_breakdown.min_dcfclk; 359 table->Watermarks.WatermarkRow[WM_DCEFCLK][i].MaxClock = clk_mgr->base.bw_params->wm_table.nv_entries[i].pmfw_breakdown.max_dcfclk; 360 table->Watermarks.WatermarkRow[WM_DCEFCLK][i].MinUclk = clk_mgr->base.bw_params->wm_table.nv_entries[i].pmfw_breakdown.min_uclk; 361 table->Watermarks.WatermarkRow[WM_DCEFCLK][i].MaxUclk = clk_mgr->base.bw_params->wm_table.nv_entries[i].pmfw_breakdown.max_uclk; 362 table->Watermarks.WatermarkRow[WM_DCEFCLK][i].WmSetting = i; 363 table->Watermarks.WatermarkRow[WM_DCEFCLK][i].Flags = clk_mgr->base.bw_params->wm_table.nv_entries[i].pmfw_breakdown.wm_type; 364 } 365 366 dcn30_smu_set_dram_addr_high(clk_mgr, clk_mgr->wm_range_table_addr >> 32); 367 dcn30_smu_set_dram_addr_low(clk_mgr, clk_mgr->wm_range_table_addr & 0xFFFFFFFF); 368 dcn30_smu_transfer_wm_table_dram_2_smu(clk_mgr); 369 } 370 371 /* Set min memclk to minimum, either constrained by the current mode or DPM0 */ 372 static void dcn3_set_hard_min_memclk(struct clk_mgr *clk_mgr_base, bool current_mode) 373 { 374 struct clk_mgr_internal *clk_mgr = TO_CLK_MGR_INTERNAL(clk_mgr_base); 375 376 if (!clk_mgr->smu_present) 377 return; 378 379 if (current_mode) 380 dcn30_smu_set_hard_min_by_freq(clk_mgr, PPCLK_UCLK, 381 clk_mgr_base->clks.dramclk_khz / 1000); 382 else 383 dcn30_smu_set_hard_min_by_freq(clk_mgr, PPCLK_UCLK, 384 clk_mgr_base->bw_params->clk_table.entries[0].memclk_mhz); 385 } 386 387 /* Set max memclk to highest DPM value */ 388 static void dcn3_set_hard_max_memclk(struct clk_mgr *clk_mgr_base) 389 { 390 struct clk_mgr_internal *clk_mgr = TO_CLK_MGR_INTERNAL(clk_mgr_base); 391 392 if (!clk_mgr->smu_present) 393 return; 394 395 dcn30_smu_set_hard_max_by_freq(clk_mgr, PPCLK_UCLK, 396 clk_mgr_base->bw_params->clk_table.entries[clk_mgr_base->bw_params->clk_table.num_entries - 1].memclk_mhz); 397 } 398 399 /* Get current memclk states, update bounding box */ 400 static void dcn3_get_memclk_states_from_smu(struct clk_mgr *clk_mgr_base) 401 { 402 struct clk_mgr_internal *clk_mgr = TO_CLK_MGR_INTERNAL(clk_mgr_base); 403 unsigned int num_levels; 404 405 if (!clk_mgr->smu_present) 406 return; 407 408 /* Refresh memclk states */ 409 dcn3_init_single_clock(clk_mgr, PPCLK_UCLK, 410 &clk_mgr_base->bw_params->clk_table.entries[0].memclk_mhz, 411 &num_levels); 412 clk_mgr_base->bw_params->clk_table.num_entries = num_levels ? num_levels : 1; 413 414 /* Refresh bounding box */ 415 clk_mgr_base->ctx->dc->res_pool->funcs->update_bw_bounding_box( 416 clk_mgr->base.ctx->dc, clk_mgr_base->bw_params); 417 } 418 419 static bool dcn3_are_clock_states_equal(struct dc_clocks *a, 420 struct dc_clocks *b) 421 { 422 if (a->dispclk_khz != b->dispclk_khz) 423 return false; 424 else if (a->dppclk_khz != b->dppclk_khz) 425 return false; 426 else if (a->dcfclk_khz != b->dcfclk_khz) 427 return false; 428 else if (a->dcfclk_deep_sleep_khz != b->dcfclk_deep_sleep_khz) 429 return false; 430 else if (a->dramclk_khz != b->dramclk_khz) 431 return false; 432 else if (a->p_state_change_support != b->p_state_change_support) 433 return false; 434 435 return true; 436 } 437 438 static void dcn3_enable_pme_wa(struct clk_mgr *clk_mgr_base) 439 { 440 struct clk_mgr_internal *clk_mgr = TO_CLK_MGR_INTERNAL(clk_mgr_base); 441 442 if (!clk_mgr->smu_present) 443 return; 444 445 dcn30_smu_set_pme_workaround(clk_mgr); 446 } 447 448 /* Notify clk_mgr of a change in link rate, update phyclk frequency if necessary */ 449 static void dcn30_notify_link_rate_change(struct clk_mgr *clk_mgr_base, struct dc_link *link) 450 { 451 struct clk_mgr_internal *clk_mgr = TO_CLK_MGR_INTERNAL(clk_mgr_base); 452 unsigned int i, max_phyclk_req = clk_mgr_base->bw_params->clk_table.entries[0].phyclk_mhz * 1000; 453 454 if (!clk_mgr->smu_present) 455 return; 456 457 clk_mgr->cur_phyclk_req_table[link->link_index] = link->cur_link_settings.link_rate * LINK_RATE_REF_FREQ_IN_KHZ; 458 459 for (i = 0; i < MAX_PIPES * 2; i++) { 460 if (clk_mgr->cur_phyclk_req_table[i] > max_phyclk_req) 461 max_phyclk_req = clk_mgr->cur_phyclk_req_table[i]; 462 } 463 464 if (max_phyclk_req != clk_mgr_base->clks.phyclk_khz) { 465 clk_mgr_base->clks.phyclk_khz = max_phyclk_req; 466 dcn30_smu_set_hard_min_by_freq(clk_mgr, PPCLK_PHYCLK, clk_mgr_base->clks.phyclk_khz / 1000); 467 } 468 } 469 470 static struct clk_mgr_funcs dcn3_funcs = { 471 .get_dp_ref_clk_frequency = dce12_get_dp_ref_freq_khz, 472 .update_clocks = dcn3_update_clocks, 473 .init_clocks = dcn3_init_clocks, 474 .notify_wm_ranges = dcn3_notify_wm_ranges, 475 .set_hard_min_memclk = dcn3_set_hard_min_memclk, 476 .set_hard_max_memclk = dcn3_set_hard_max_memclk, 477 .get_memclk_states_from_smu = dcn3_get_memclk_states_from_smu, 478 .are_clock_states_equal = dcn3_are_clock_states_equal, 479 .enable_pme_wa = dcn3_enable_pme_wa, 480 .notify_link_rate_change = dcn30_notify_link_rate_change, 481 }; 482 483 static void dcn3_init_clocks_fpga(struct clk_mgr *clk_mgr) 484 { 485 dcn2_init_clocks(clk_mgr); 486 487 /* TODO: Implement the functions and remove the ifndef guard */ 488 } 489 490 static struct clk_mgr_funcs dcn3_fpga_funcs = { 491 .get_dp_ref_clk_frequency = dce12_get_dp_ref_freq_khz, 492 .update_clocks = dcn2_update_clocks_fpga, 493 .init_clocks = dcn3_init_clocks_fpga, 494 }; 495 496 /*todo for dcn30 for clk register offset*/ 497 void dcn3_clk_mgr_construct( 498 struct dc_context *ctx, 499 struct clk_mgr_internal *clk_mgr, 500 struct pp_smu_funcs *pp_smu, 501 struct dccg *dccg) 502 { 503 clk_mgr->base.ctx = ctx; 504 clk_mgr->base.funcs = &dcn3_funcs; 505 clk_mgr->regs = &clk_mgr_regs; 506 clk_mgr->clk_mgr_shift = &clk_mgr_shift; 507 clk_mgr->clk_mgr_mask = &clk_mgr_mask; 508 509 clk_mgr->dccg = dccg; 510 clk_mgr->dfs_bypass_disp_clk = 0; 511 512 clk_mgr->dprefclk_ss_percentage = 0; 513 clk_mgr->dprefclk_ss_divider = 1000; 514 clk_mgr->ss_on_dprefclk = false; 515 clk_mgr->dfs_ref_freq_khz = 100000; 516 517 clk_mgr->base.dprefclk_khz = 730000; // 700 MHz planned if VCO is 3.85 GHz, will be retrieved 518 519 if (IS_FPGA_MAXIMUS_DC(ctx->dce_environment)) { 520 clk_mgr->base.funcs = &dcn3_fpga_funcs; 521 clk_mgr->base.dentist_vco_freq_khz = 3650000; 522 523 } else { 524 struct clk_state_registers_and_bypass s = { 0 }; 525 526 /* integer part is now VCO frequency in kHz */ 527 clk_mgr->base.dentist_vco_freq_khz = dcn30_get_vco_frequency_from_reg(clk_mgr); 528 529 /* in case we don't get a value from the register, use default */ 530 if (clk_mgr->base.dentist_vco_freq_khz == 0) 531 clk_mgr->base.dentist_vco_freq_khz = 3650000; 532 /* Convert dprefclk units from MHz to KHz */ 533 /* Value already divided by 10, some resolution lost */ 534 535 /*TODO: uncomment assert once dcn3_dump_clk_registers is implemented */ 536 //ASSERT(s.dprefclk != 0); 537 if (s.dprefclk != 0) 538 clk_mgr->base.dprefclk_khz = s.dprefclk * 1000; 539 } 540 541 clk_mgr->dfs_bypass_enabled = false; 542 543 clk_mgr->smu_present = false; 544 545 dce_clock_read_ss_info(clk_mgr); 546 547 clk_mgr->base.bw_params = kzalloc(sizeof(*clk_mgr->base.bw_params), GFP_KERNEL); 548 549 /* need physical address of table to give to PMFW */ 550 clk_mgr->wm_range_table = dm_helpers_allocate_gpu_mem(clk_mgr->base.ctx, 551 DC_MEM_ALLOC_TYPE_GART, sizeof(WatermarksExternal_t), 552 &clk_mgr->wm_range_table_addr); 553 } 554 555 void dcn3_clk_mgr_destroy(struct clk_mgr_internal *clk_mgr) 556 { 557 if (clk_mgr->base.bw_params) 558 kfree(clk_mgr->base.bw_params); 559 560 if (clk_mgr->wm_range_table) 561 dm_helpers_free_gpu_mem(clk_mgr->base.ctx, DC_MEM_ALLOC_TYPE_GART, 562 clk_mgr->wm_range_table); 563 } 564