1 /* 2 * Copyright 2020 Advanced Micro Devices, Inc. 3 * 4 * Permission is hereby granted, free of charge, to any person obtaining a 5 * copy of this software and associated documentation files (the "Software"), 6 * to deal in the Software without restriction, including without limitation 7 * the rights to use, copy, modify, merge, publish, distribute, sublicense, 8 * and/or sell copies of the Software, and to permit persons to whom the 9 * Software is furnished to do so, subject to the following conditions: 10 * 11 * The above copyright notice and this permission notice shall be included in 12 * all copies or substantial portions of the Software. 13 * 14 * THE SOFTWARE IS PROVIDED "AS IS", WITHOUT WARRANTY OF ANY KIND, EXPRESS OR 15 * IMPLIED, INCLUDING BUT NOT LIMITED TO THE WARRANTIES OF MERCHANTABILITY, 16 * FITNESS FOR A PARTICULAR PURPOSE AND NONINFRINGEMENT. IN NO EVENT SHALL 17 * THE COPYRIGHT HOLDER(S) OR AUTHOR(S) BE LIABLE FOR ANY CLAIM, DAMAGES OR 18 * OTHER LIABILITY, WHETHER IN AN ACTION OF CONTRACT, TORT OR OTHERWISE, 19 * ARISING FROM, OUT OF OR IN CONNECTION WITH THE SOFTWARE OR THE USE OR 20 * OTHER DEALINGS IN THE SOFTWARE. 21 * 22 * Authors: AMD 23 * 24 */ 25 26 #include "dccg.h" 27 #include "clk_mgr_internal.h" 28 29 #include "dcn30_clk_mgr_smu_msg.h" 30 #include "dcn20/dcn20_clk_mgr.h" 31 #include "dce100/dce_clk_mgr.h" 32 #include "reg_helper.h" 33 #include "core_types.h" 34 #include "dm_helpers.h" 35 36 #include "atomfirmware.h" 37 38 39 #include "sienna_cichlid_ip_offset.h" 40 #include "dcn/dcn_3_0_0_offset.h" 41 #include "dcn/dcn_3_0_0_sh_mask.h" 42 43 #include "nbio/nbio_7_4_offset.h" 44 45 #include "dcn/dpcs_3_0_0_offset.h" 46 #include "dcn/dpcs_3_0_0_sh_mask.h" 47 48 #include "mmhub/mmhub_2_0_0_offset.h" 49 #include "mmhub/mmhub_2_0_0_sh_mask.h" 50 /*we don't have clk folder yet*/ 51 #include "dcn30/dcn30_clk_mgr.h" 52 53 #undef FN 54 #define FN(reg_name, field_name) \ 55 clk_mgr->clk_mgr_shift->field_name, clk_mgr->clk_mgr_mask->field_name 56 57 #define REG(reg) \ 58 (clk_mgr->regs->reg) 59 60 #define BASE_INNER(seg) DCN_BASE__INST0_SEG ## seg 61 62 #define BASE(seg) BASE_INNER(seg) 63 64 #define SR(reg_name)\ 65 .reg_name = BASE(mm ## reg_name ## _BASE_IDX) + \ 66 mm ## reg_name 67 68 #undef CLK_SRI 69 #define CLK_SRI(reg_name, block, inst)\ 70 .reg_name = mm ## block ## _ ## reg_name 71 72 static const struct clk_mgr_registers clk_mgr_regs = { 73 CLK_REG_LIST_DCN3() 74 }; 75 76 static const struct clk_mgr_shift clk_mgr_shift = { 77 CLK_COMMON_MASK_SH_LIST_DCN20_BASE(__SHIFT) 78 }; 79 80 static const struct clk_mgr_mask clk_mgr_mask = { 81 CLK_COMMON_MASK_SH_LIST_DCN20_BASE(_MASK) 82 }; 83 84 85 /* Query SMU for all clock states for a particular clock */ 86 static void dcn3_init_single_clock(struct clk_mgr_internal *clk_mgr, PPCLK_e clk, unsigned int *entry_0, unsigned int *num_levels) 87 { 88 unsigned int i; 89 char *entry_i = (char *)entry_0; 90 uint32_t ret = dcn30_smu_get_dpm_freq_by_index(clk_mgr, clk, 0xFF); 91 92 if (ret & (1 << 31)) 93 /* fine-grained, only min and max */ 94 *num_levels = 2; 95 else 96 /* discrete, a number of fixed states */ 97 /* will set num_levels to 0 on failure */ 98 *num_levels = ret & 0xFF; 99 100 /* if the initial message failed, num_levels will be 0 */ 101 for (i = 0; i < *num_levels; i++) { 102 *((unsigned int *)entry_i) = (dcn30_smu_get_dpm_freq_by_index(clk_mgr, clk, i) & 0xFFFF); 103 entry_i += sizeof(clk_mgr->base.bw_params->clk_table.entries[0]); 104 } 105 } 106 107 static noinline void dcn3_build_wm_range_table(struct clk_mgr_internal *clk_mgr) 108 { 109 /* defaults */ 110 double pstate_latency_us = clk_mgr->base.ctx->dc->dml.soc.dram_clock_change_latency_us; 111 double sr_exit_time_us = clk_mgr->base.ctx->dc->dml.soc.sr_exit_time_us; 112 double sr_enter_plus_exit_time_us = clk_mgr->base.ctx->dc->dml.soc.sr_enter_plus_exit_time_us; 113 uint16_t min_uclk_mhz = clk_mgr->base.bw_params->clk_table.entries[0].memclk_mhz; 114 115 /* Set A - Normal - default values*/ 116 clk_mgr->base.bw_params->wm_table.nv_entries[WM_A].valid = true; 117 clk_mgr->base.bw_params->wm_table.nv_entries[WM_A].dml_input.pstate_latency_us = pstate_latency_us; 118 clk_mgr->base.bw_params->wm_table.nv_entries[WM_A].dml_input.sr_exit_time_us = sr_exit_time_us; 119 clk_mgr->base.bw_params->wm_table.nv_entries[WM_A].dml_input.sr_enter_plus_exit_time_us = sr_enter_plus_exit_time_us; 120 clk_mgr->base.bw_params->wm_table.nv_entries[WM_A].pmfw_breakdown.wm_type = WATERMARKS_CLOCK_RANGE; 121 clk_mgr->base.bw_params->wm_table.nv_entries[WM_A].pmfw_breakdown.min_dcfclk = 0; 122 clk_mgr->base.bw_params->wm_table.nv_entries[WM_A].pmfw_breakdown.max_dcfclk = 0xFFFF; 123 clk_mgr->base.bw_params->wm_table.nv_entries[WM_A].pmfw_breakdown.min_uclk = min_uclk_mhz; 124 clk_mgr->base.bw_params->wm_table.nv_entries[WM_A].pmfw_breakdown.max_uclk = 0xFFFF; 125 126 /* Set B - Performance - higher minimum clocks */ 127 // clk_mgr->base.bw_params->wm_table.nv_entries[WM_B].valid = true; 128 // clk_mgr->base.bw_params->wm_table.nv_entries[WM_B].dml_input.pstate_latency_us = pstate_latency_us; 129 // clk_mgr->base.bw_params->wm_table.nv_entries[WM_B].dml_input.sr_exit_time_us = sr_exit_time_us; 130 // clk_mgr->base.bw_params->wm_table.nv_entries[WM_B].dml_input.sr_enter_plus_exit_time_us = sr_enter_plus_exit_time_us; 131 // clk_mgr->base.bw_params->wm_table.nv_entries[WM_B].pmfw_breakdown.wm_type = WATERMARKS_CLOCK_RANGE; 132 // clk_mgr->base.bw_params->wm_table.nv_entries[WM_B].pmfw_breakdown.min_dcfclk = TUNED VALUE; 133 // clk_mgr->base.bw_params->wm_table.nv_entries[WM_B].pmfw_breakdown.max_dcfclk = 0xFFFF; 134 // clk_mgr->base.bw_params->wm_table.nv_entries[WM_B].pmfw_breakdown.min_uclk = TUNED VALUE; 135 // clk_mgr->base.bw_params->wm_table.nv_entries[WM_B].pmfw_breakdown.max_uclk = 0xFFFF; 136 137 /* Set C - Dummy P-State - P-State latency set to "dummy p-state" value */ 138 clk_mgr->base.bw_params->wm_table.nv_entries[WM_C].valid = true; 139 clk_mgr->base.bw_params->wm_table.nv_entries[WM_C].dml_input.pstate_latency_us = clk_mgr->base.ctx->dc->dml.soc.dummy_pstate_latency_us; 140 clk_mgr->base.bw_params->wm_table.nv_entries[WM_C].dml_input.sr_exit_time_us = sr_exit_time_us; 141 clk_mgr->base.bw_params->wm_table.nv_entries[WM_C].dml_input.sr_enter_plus_exit_time_us = sr_enter_plus_exit_time_us; 142 clk_mgr->base.bw_params->wm_table.nv_entries[WM_C].pmfw_breakdown.wm_type = WATERMARKS_DUMMY_PSTATE; 143 clk_mgr->base.bw_params->wm_table.nv_entries[WM_C].pmfw_breakdown.min_dcfclk = 0; 144 clk_mgr->base.bw_params->wm_table.nv_entries[WM_C].pmfw_breakdown.max_dcfclk = 0xFFFF; 145 clk_mgr->base.bw_params->wm_table.nv_entries[WM_C].pmfw_breakdown.min_uclk = min_uclk_mhz; 146 clk_mgr->base.bw_params->wm_table.nv_entries[WM_C].pmfw_breakdown.max_uclk = 0xFFFF; 147 148 /* Set D - MALL - SR enter and exit times adjusted for MALL */ 149 // clk_mgr->base.bw_params->wm_table.nv_entries[WM_D].valid = true; 150 // clk_mgr->base.bw_params->wm_table.nv_entries[WM_D].dml_input.pstate_latency_us = pstate_latency_us; 151 // clk_mgr->base.bw_params->wm_table.nv_entries[WM_D].dml_input.sr_exit_time_us = 2; 152 // clk_mgr->base.bw_params->wm_table.nv_entries[WM_D].dml_input.sr_enter_plus_exit_time_us = 4; 153 // clk_mgr->base.bw_params->wm_table.nv_entries[WM_D].pmfw_breakdown.wm_type = WATERMARKS_MALL; 154 // clk_mgr->base.bw_params->wm_table.nv_entries[WM_D].pmfw_breakdown.min_dcfclk = 0; 155 // clk_mgr->base.bw_params->wm_table.nv_entries[WM_D].pmfw_breakdown.max_dcfclk = 0xFFFF; 156 // clk_mgr->base.bw_params->wm_table.nv_entries[WM_D].pmfw_breakdown.min_uclk = min_uclk_mhz; 157 // clk_mgr->base.bw_params->wm_table.nv_entries[WM_D].pmfw_breakdown.max_uclk = 0xFFFF; 158 } 159 160 void dcn3_init_clocks(struct clk_mgr *clk_mgr_base) 161 { 162 struct clk_mgr_internal *clk_mgr = TO_CLK_MGR_INTERNAL(clk_mgr_base); 163 unsigned int num_levels; 164 165 memset(&(clk_mgr_base->clks), 0, sizeof(struct dc_clocks)); 166 clk_mgr_base->clks.p_state_change_support = true; 167 clk_mgr_base->clks.prev_p_state_change_support = true; 168 clk_mgr->smu_present = false; 169 170 if (!clk_mgr_base->bw_params) 171 return; 172 173 if (!clk_mgr_base->force_smu_not_present && dcn30_smu_get_smu_version(clk_mgr, &clk_mgr->smu_ver)) 174 clk_mgr->smu_present = true; 175 176 if (!clk_mgr->smu_present) 177 return; 178 179 // do we fail if these fail? if so, how? do we not care to check? 180 dcn30_smu_check_driver_if_version(clk_mgr); 181 dcn30_smu_check_msg_header_version(clk_mgr); 182 183 /* DCFCLK */ 184 dcn3_init_single_clock(clk_mgr, PPCLK_DCEFCLK, 185 &clk_mgr_base->bw_params->clk_table.entries[0].dcfclk_mhz, 186 &num_levels); 187 188 /* DTBCLK */ 189 dcn3_init_single_clock(clk_mgr, PPCLK_DTBCLK, 190 &clk_mgr_base->bw_params->clk_table.entries[0].dtbclk_mhz, 191 &num_levels); 192 193 // DPREFCLK ??? 194 195 /* DISPCLK */ 196 dcn3_init_single_clock(clk_mgr, PPCLK_DISPCLK, 197 &clk_mgr_base->bw_params->clk_table.entries[0].dispclk_mhz, 198 &num_levels); 199 200 /* DPPCLK */ 201 dcn3_init_single_clock(clk_mgr, PPCLK_PIXCLK, 202 &clk_mgr_base->bw_params->clk_table.entries[0].dppclk_mhz, 203 &num_levels); 204 205 /* PHYCLK */ 206 dcn3_init_single_clock(clk_mgr, PPCLK_PHYCLK, 207 &clk_mgr_base->bw_params->clk_table.entries[0].phyclk_mhz, 208 &num_levels); 209 210 /* Get UCLK, update bounding box */ 211 clk_mgr_base->funcs->get_memclk_states_from_smu(clk_mgr_base); 212 213 /* WM range table */ 214 DC_FP_START(); 215 dcn3_build_wm_range_table(clk_mgr); 216 DC_FP_END(); 217 } 218 219 static int dcn30_get_vco_frequency_from_reg(struct clk_mgr_internal *clk_mgr) 220 { 221 /* get FbMult value */ 222 struct fixed31_32 pll_req; 223 /* get FbMult value */ 224 uint32_t pll_req_reg = REG_READ(CLK0_CLK_PLL_REQ); 225 226 /* set up a fixed-point number 227 * this works because the int part is on the right edge of the register 228 * and the frac part is on the left edge 229 */ 230 pll_req = dc_fixpt_from_int(pll_req_reg & clk_mgr->clk_mgr_mask->FbMult_int); 231 pll_req.value |= pll_req_reg & clk_mgr->clk_mgr_mask->FbMult_frac; 232 233 /* multiply by REFCLK period */ 234 pll_req = dc_fixpt_mul_int(pll_req, clk_mgr->dfs_ref_freq_khz); 235 236 return dc_fixpt_floor(pll_req); 237 } 238 239 static void dcn3_update_clocks(struct clk_mgr *clk_mgr_base, 240 struct dc_state *context, 241 bool safe_to_lower) 242 { 243 struct clk_mgr_internal *clk_mgr = TO_CLK_MGR_INTERNAL(clk_mgr_base); 244 struct dc_clocks *new_clocks = &context->bw_ctx.bw.dcn.clk; 245 struct dc *dc = clk_mgr_base->ctx->dc; 246 int display_count; 247 bool update_dppclk = false; 248 bool update_dispclk = false; 249 bool enter_display_off = false; 250 bool dpp_clock_lowered = false; 251 struct dmcu *dmcu = clk_mgr_base->ctx->dc->res_pool->dmcu; 252 bool force_reset = false; 253 bool update_uclk = false; 254 255 if (dc->work_arounds.skip_clock_update || !clk_mgr->smu_present) 256 return; 257 258 if (clk_mgr_base->clks.dispclk_khz == 0 || 259 (dc->debug.force_clock_mode & 0x1)) { 260 /* this is from resume or boot up, if forced_clock cfg option used, we bypass program dispclk and DPPCLK, but need set them for S3. */ 261 force_reset = true; 262 263 dcn2_read_clocks_from_hw_dentist(clk_mgr_base); 264 265 /* force_clock_mode 0x1: force reset the clock even it is the same clock as long as it is in Passive level. */ 266 } 267 display_count = clk_mgr_helper_get_active_display_cnt(dc, context); 268 269 if (display_count == 0) 270 enter_display_off = true; 271 272 if (enter_display_off == safe_to_lower) 273 dcn30_smu_set_num_of_displays(clk_mgr, display_count); 274 275 if (dc->debug.force_min_dcfclk_mhz > 0) 276 new_clocks->dcfclk_khz = (new_clocks->dcfclk_khz > (dc->debug.force_min_dcfclk_mhz * 1000)) ? 277 new_clocks->dcfclk_khz : (dc->debug.force_min_dcfclk_mhz * 1000); 278 279 if (should_set_clock(safe_to_lower, new_clocks->dcfclk_khz, clk_mgr_base->clks.dcfclk_khz)) { 280 clk_mgr_base->clks.dcfclk_khz = new_clocks->dcfclk_khz; 281 dcn30_smu_set_hard_min_by_freq(clk_mgr, PPCLK_DCEFCLK, clk_mgr_base->clks.dcfclk_khz / 1000); 282 } 283 284 if (should_set_clock(safe_to_lower, new_clocks->dcfclk_deep_sleep_khz, clk_mgr_base->clks.dcfclk_deep_sleep_khz)) { 285 clk_mgr_base->clks.dcfclk_deep_sleep_khz = new_clocks->dcfclk_deep_sleep_khz; 286 dcn30_smu_set_min_deep_sleep_dcef_clk(clk_mgr, clk_mgr_base->clks.dcfclk_deep_sleep_khz / 1000); 287 } 288 289 if (should_set_clock(safe_to_lower, new_clocks->socclk_khz, clk_mgr_base->clks.socclk_khz)) 290 /* We don't actually care about socclk, don't notify SMU of hard min */ 291 clk_mgr_base->clks.socclk_khz = new_clocks->socclk_khz; 292 293 clk_mgr_base->clks.prev_p_state_change_support = clk_mgr_base->clks.p_state_change_support; 294 if (should_update_pstate_support(safe_to_lower, new_clocks->p_state_change_support, clk_mgr_base->clks.p_state_change_support)) { 295 clk_mgr_base->clks.p_state_change_support = new_clocks->p_state_change_support; 296 297 /* to disable P-State switching, set UCLK min = max */ 298 if (!clk_mgr_base->clks.p_state_change_support) 299 dcn30_smu_set_hard_min_by_freq(clk_mgr, PPCLK_UCLK, 300 clk_mgr_base->bw_params->clk_table.entries[clk_mgr_base->bw_params->clk_table.num_entries - 1].memclk_mhz); 301 } 302 303 /* Always update saved value, even if new value not set due to P-State switching unsupported */ 304 if (should_set_clock(safe_to_lower, new_clocks->dramclk_khz, clk_mgr_base->clks.dramclk_khz)) { 305 clk_mgr_base->clks.dramclk_khz = new_clocks->dramclk_khz; 306 update_uclk = true; 307 } 308 309 /* set UCLK to requested value if P-State switching is supported, or to re-enable P-State switching */ 310 if (clk_mgr_base->clks.p_state_change_support && 311 (update_uclk || !clk_mgr_base->clks.prev_p_state_change_support)) 312 dcn30_smu_set_hard_min_by_freq(clk_mgr, PPCLK_UCLK, clk_mgr_base->clks.dramclk_khz / 1000); 313 314 if (should_set_clock(safe_to_lower, new_clocks->dppclk_khz, clk_mgr_base->clks.dppclk_khz)) { 315 if (clk_mgr_base->clks.dppclk_khz > new_clocks->dppclk_khz) 316 dpp_clock_lowered = true; 317 318 clk_mgr_base->clks.dppclk_khz = new_clocks->dppclk_khz; 319 dcn30_smu_set_hard_min_by_freq(clk_mgr, PPCLK_PIXCLK, clk_mgr_base->clks.dppclk_khz / 1000); 320 update_dppclk = true; 321 } 322 323 if (should_set_clock(safe_to_lower, new_clocks->dispclk_khz, clk_mgr_base->clks.dispclk_khz)) { 324 clk_mgr_base->clks.dispclk_khz = new_clocks->dispclk_khz; 325 dcn30_smu_set_hard_min_by_freq(clk_mgr, PPCLK_DISPCLK, clk_mgr_base->clks.dispclk_khz / 1000); 326 update_dispclk = true; 327 } 328 329 if (dc->config.forced_clocks == false || (force_reset && safe_to_lower)) { 330 if (dpp_clock_lowered) { 331 /* if clock is being lowered, increase DTO before lowering refclk */ 332 dcn20_update_clocks_update_dpp_dto(clk_mgr, context, safe_to_lower); 333 dcn20_update_clocks_update_dentist(clk_mgr); 334 } else { 335 /* if clock is being raised, increase refclk before lowering DTO */ 336 if (update_dppclk || update_dispclk) 337 dcn20_update_clocks_update_dentist(clk_mgr); 338 /* There is a check inside dcn20_update_clocks_update_dpp_dto which ensures 339 * that we do not lower dto when it is not safe to lower. We do not need to 340 * compare the current and new dppclk before calling this function.*/ 341 dcn20_update_clocks_update_dpp_dto(clk_mgr, context, safe_to_lower); 342 } 343 } 344 345 if (update_dispclk && dmcu && dmcu->funcs->is_dmcu_initialized(dmcu)) 346 /*update dmcu for wait_loop count*/ 347 dmcu->funcs->set_psr_wait_loop(dmcu, 348 clk_mgr_base->clks.dispclk_khz / 1000 / 7); 349 } 350 351 352 static void dcn3_notify_wm_ranges(struct clk_mgr *clk_mgr_base) 353 { 354 unsigned int i; 355 struct clk_mgr_internal *clk_mgr = TO_CLK_MGR_INTERNAL(clk_mgr_base); 356 WatermarksExternal_t *table = (WatermarksExternal_t *) clk_mgr->wm_range_table; 357 358 if (!clk_mgr->smu_present) 359 return; 360 361 if (!table) 362 // should log failure 363 return; 364 365 memset(table, 0, sizeof(*table)); 366 367 /* collect valid ranges, place in pmfw table */ 368 for (i = 0; i < WM_SET_COUNT; i++) 369 if (clk_mgr->base.bw_params->wm_table.nv_entries[i].valid) { 370 table->Watermarks.WatermarkRow[WM_DCEFCLK][i].MinClock = clk_mgr->base.bw_params->wm_table.nv_entries[i].pmfw_breakdown.min_dcfclk; 371 table->Watermarks.WatermarkRow[WM_DCEFCLK][i].MaxClock = clk_mgr->base.bw_params->wm_table.nv_entries[i].pmfw_breakdown.max_dcfclk; 372 table->Watermarks.WatermarkRow[WM_DCEFCLK][i].MinUclk = clk_mgr->base.bw_params->wm_table.nv_entries[i].pmfw_breakdown.min_uclk; 373 table->Watermarks.WatermarkRow[WM_DCEFCLK][i].MaxUclk = clk_mgr->base.bw_params->wm_table.nv_entries[i].pmfw_breakdown.max_uclk; 374 table->Watermarks.WatermarkRow[WM_DCEFCLK][i].WmSetting = i; 375 table->Watermarks.WatermarkRow[WM_DCEFCLK][i].Flags = clk_mgr->base.bw_params->wm_table.nv_entries[i].pmfw_breakdown.wm_type; 376 } 377 378 dcn30_smu_set_dram_addr_high(clk_mgr, clk_mgr->wm_range_table_addr >> 32); 379 dcn30_smu_set_dram_addr_low(clk_mgr, clk_mgr->wm_range_table_addr & 0xFFFFFFFF); 380 dcn30_smu_transfer_wm_table_dram_2_smu(clk_mgr); 381 } 382 383 /* Set min memclk to minimum, either constrained by the current mode or DPM0 */ 384 static void dcn3_set_hard_min_memclk(struct clk_mgr *clk_mgr_base, bool current_mode) 385 { 386 struct clk_mgr_internal *clk_mgr = TO_CLK_MGR_INTERNAL(clk_mgr_base); 387 388 if (!clk_mgr->smu_present) 389 return; 390 391 if (current_mode) 392 dcn30_smu_set_hard_min_by_freq(clk_mgr, PPCLK_UCLK, 393 clk_mgr_base->clks.dramclk_khz / 1000); 394 else 395 dcn30_smu_set_hard_min_by_freq(clk_mgr, PPCLK_UCLK, 396 clk_mgr_base->bw_params->clk_table.entries[0].memclk_mhz); 397 } 398 399 /* Set max memclk to highest DPM value */ 400 static void dcn3_set_hard_max_memclk(struct clk_mgr *clk_mgr_base) 401 { 402 struct clk_mgr_internal *clk_mgr = TO_CLK_MGR_INTERNAL(clk_mgr_base); 403 404 if (!clk_mgr->smu_present) 405 return; 406 407 dcn30_smu_set_hard_max_by_freq(clk_mgr, PPCLK_UCLK, 408 clk_mgr_base->bw_params->clk_table.entries[clk_mgr_base->bw_params->clk_table.num_entries - 1].memclk_mhz); 409 } 410 411 /* Get current memclk states, update bounding box */ 412 static void dcn3_get_memclk_states_from_smu(struct clk_mgr *clk_mgr_base) 413 { 414 struct clk_mgr_internal *clk_mgr = TO_CLK_MGR_INTERNAL(clk_mgr_base); 415 unsigned int num_levels; 416 417 if (!clk_mgr->smu_present) 418 return; 419 420 /* Refresh memclk states */ 421 dcn3_init_single_clock(clk_mgr, PPCLK_UCLK, 422 &clk_mgr_base->bw_params->clk_table.entries[0].memclk_mhz, 423 &num_levels); 424 clk_mgr_base->bw_params->clk_table.num_entries = num_levels ? num_levels : 1; 425 426 /* Refresh bounding box */ 427 clk_mgr_base->ctx->dc->res_pool->funcs->update_bw_bounding_box( 428 clk_mgr->base.ctx->dc, clk_mgr_base->bw_params); 429 } 430 431 static bool dcn3_are_clock_states_equal(struct dc_clocks *a, 432 struct dc_clocks *b) 433 { 434 if (a->dispclk_khz != b->dispclk_khz) 435 return false; 436 else if (a->dppclk_khz != b->dppclk_khz) 437 return false; 438 else if (a->dcfclk_khz != b->dcfclk_khz) 439 return false; 440 else if (a->dcfclk_deep_sleep_khz != b->dcfclk_deep_sleep_khz) 441 return false; 442 else if (a->dramclk_khz != b->dramclk_khz) 443 return false; 444 else if (a->p_state_change_support != b->p_state_change_support) 445 return false; 446 447 return true; 448 } 449 450 static void dcn3_enable_pme_wa(struct clk_mgr *clk_mgr_base) 451 { 452 struct clk_mgr_internal *clk_mgr = TO_CLK_MGR_INTERNAL(clk_mgr_base); 453 454 if (!clk_mgr->smu_present) 455 return; 456 457 dcn30_smu_set_pme_workaround(clk_mgr); 458 } 459 460 /* Notify clk_mgr of a change in link rate, update phyclk frequency if necessary */ 461 static void dcn30_notify_link_rate_change(struct clk_mgr *clk_mgr_base, struct dc_link *link) 462 { 463 struct clk_mgr_internal *clk_mgr = TO_CLK_MGR_INTERNAL(clk_mgr_base); 464 unsigned int i, max_phyclk_req = clk_mgr_base->bw_params->clk_table.entries[0].phyclk_mhz * 1000; 465 466 if (!clk_mgr->smu_present) 467 return; 468 469 clk_mgr->cur_phyclk_req_table[link->link_index] = link->cur_link_settings.link_rate * LINK_RATE_REF_FREQ_IN_KHZ; 470 471 for (i = 0; i < MAX_PIPES * 2; i++) { 472 if (clk_mgr->cur_phyclk_req_table[i] > max_phyclk_req) 473 max_phyclk_req = clk_mgr->cur_phyclk_req_table[i]; 474 } 475 476 if (max_phyclk_req != clk_mgr_base->clks.phyclk_khz) { 477 clk_mgr_base->clks.phyclk_khz = max_phyclk_req; 478 dcn30_smu_set_hard_min_by_freq(clk_mgr, PPCLK_PHYCLK, clk_mgr_base->clks.phyclk_khz / 1000); 479 } 480 } 481 482 static struct clk_mgr_funcs dcn3_funcs = { 483 .get_dp_ref_clk_frequency = dce12_get_dp_ref_freq_khz, 484 .update_clocks = dcn3_update_clocks, 485 .init_clocks = dcn3_init_clocks, 486 .notify_wm_ranges = dcn3_notify_wm_ranges, 487 .set_hard_min_memclk = dcn3_set_hard_min_memclk, 488 .set_hard_max_memclk = dcn3_set_hard_max_memclk, 489 .get_memclk_states_from_smu = dcn3_get_memclk_states_from_smu, 490 .are_clock_states_equal = dcn3_are_clock_states_equal, 491 .enable_pme_wa = dcn3_enable_pme_wa, 492 .notify_link_rate_change = dcn30_notify_link_rate_change, 493 }; 494 495 static void dcn3_init_clocks_fpga(struct clk_mgr *clk_mgr) 496 { 497 dcn2_init_clocks(clk_mgr); 498 499 /* TODO: Implement the functions and remove the ifndef guard */ 500 } 501 502 struct clk_mgr_funcs dcn3_fpga_funcs = { 503 .get_dp_ref_clk_frequency = dce12_get_dp_ref_freq_khz, 504 .update_clocks = dcn2_update_clocks_fpga, 505 .init_clocks = dcn3_init_clocks_fpga, 506 }; 507 508 /*todo for dcn30 for clk register offset*/ 509 void dcn3_clk_mgr_construct( 510 struct dc_context *ctx, 511 struct clk_mgr_internal *clk_mgr, 512 struct pp_smu_funcs *pp_smu, 513 struct dccg *dccg) 514 { 515 clk_mgr->base.ctx = ctx; 516 clk_mgr->base.funcs = &dcn3_funcs; 517 clk_mgr->regs = &clk_mgr_regs; 518 clk_mgr->clk_mgr_shift = &clk_mgr_shift; 519 clk_mgr->clk_mgr_mask = &clk_mgr_mask; 520 521 clk_mgr->dccg = dccg; 522 clk_mgr->dfs_bypass_disp_clk = 0; 523 524 clk_mgr->dprefclk_ss_percentage = 0; 525 clk_mgr->dprefclk_ss_divider = 1000; 526 clk_mgr->ss_on_dprefclk = false; 527 clk_mgr->dfs_ref_freq_khz = 100000; 528 529 clk_mgr->base.dprefclk_khz = 730000; // 700 MHz planned if VCO is 3.85 GHz, will be retrieved 530 531 if (IS_FPGA_MAXIMUS_DC(ctx->dce_environment)) { 532 clk_mgr->base.funcs = &dcn3_fpga_funcs; 533 clk_mgr->base.dentist_vco_freq_khz = 3650000; 534 535 } else { 536 struct clk_state_registers_and_bypass s = { 0 }; 537 538 /* integer part is now VCO frequency in kHz */ 539 clk_mgr->base.dentist_vco_freq_khz = dcn30_get_vco_frequency_from_reg(clk_mgr); 540 541 /* in case we don't get a value from the register, use default */ 542 if (clk_mgr->base.dentist_vco_freq_khz == 0) 543 clk_mgr->base.dentist_vco_freq_khz = 3650000; 544 /* Convert dprefclk units from MHz to KHz */ 545 /* Value already divided by 10, some resolution lost */ 546 547 /*TODO: uncomment assert once dcn3_dump_clk_registers is implemented */ 548 //ASSERT(s.dprefclk != 0); 549 if (s.dprefclk != 0) 550 clk_mgr->base.dprefclk_khz = s.dprefclk * 1000; 551 } 552 553 clk_mgr->dfs_bypass_enabled = false; 554 555 clk_mgr->smu_present = false; 556 557 dce_clock_read_ss_info(clk_mgr); 558 559 clk_mgr->base.bw_params = kzalloc(sizeof(*clk_mgr->base.bw_params), GFP_KERNEL); 560 561 /* need physical address of table to give to PMFW */ 562 clk_mgr->wm_range_table = dm_helpers_allocate_gpu_mem(clk_mgr->base.ctx, 563 DC_MEM_ALLOC_TYPE_GART, sizeof(WatermarksExternal_t), 564 &clk_mgr->wm_range_table_addr); 565 } 566 567 void dcn3_clk_mgr_destroy(struct clk_mgr_internal *clk_mgr) 568 { 569 kfree(clk_mgr->base.bw_params); 570 571 if (clk_mgr->wm_range_table) 572 dm_helpers_free_gpu_mem(clk_mgr->base.ctx, DC_MEM_ALLOC_TYPE_GART, 573 clk_mgr->wm_range_table); 574 } 575