1 /* 2 * Copyright 2012-16 Advanced Micro Devices, Inc. 3 * 4 * Permission is hereby granted, free of charge, to any person obtaining a 5 * copy of this software and associated documentation files (the "Software"), 6 * to deal in the Software without restriction, including without limitation 7 * the rights to use, copy, modify, merge, publish, distribute, sublicense, 8 * and/or sell copies of the Software, and to permit persons to whom the 9 * Software is furnished to do so, subject to the following conditions: 10 * 11 * The above copyright notice and this permission notice shall be included in 12 * all copies or substantial portions of the Software. 13 * 14 * THE SOFTWARE IS PROVIDED "AS IS", WITHOUT WARRANTY OF ANY KIND, EXPRESS OR 15 * IMPLIED, INCLUDING BUT NOT LIMITED TO THE WARRANTIES OF MERCHANTABILITY, 16 * FITNESS FOR A PARTICULAR PURPOSE AND NONINFRINGEMENT. IN NO EVENT SHALL 17 * THE COPYRIGHT HOLDER(S) OR AUTHOR(S) BE LIABLE FOR ANY CLAIM, DAMAGES OR 18 * OTHER LIABILITY, WHETHER IN AN ACTION OF CONTRACT, TORT OR OTHERWISE, 19 * ARISING FROM, OUT OF OR IN CONNECTION WITH THE SOFTWARE OR THE USE OR 20 * OTHER DEALINGS IN THE SOFTWARE. 21 * 22 * Authors: AMD 23 * 24 */ 25 26 #include "core_types.h" 27 #include "clk_mgr_internal.h" 28 #include "reg_helper.h" 29 #include <linux/delay.h> 30 31 #include "renoir_ip_offset.h" 32 33 #include "mp/mp_12_0_0_offset.h" 34 #include "mp/mp_12_0_0_sh_mask.h" 35 36 #include "rn_clk_mgr_vbios_smu.h" 37 38 #define REG(reg_name) \ 39 (MP0_BASE.instance[0].segment[mm ## reg_name ## _BASE_IDX] + mm ## reg_name) 40 41 #define FN(reg_name, field) \ 42 FD(reg_name##__##field) 43 44 #define VBIOSSMC_MSG_TestMessage 0x1 45 #define VBIOSSMC_MSG_GetSmuVersion 0x2 46 #define VBIOSSMC_MSG_PowerUpGfx 0x3 47 #define VBIOSSMC_MSG_SetDispclkFreq 0x4 48 #define VBIOSSMC_MSG_SetDprefclkFreq 0x5 49 #define VBIOSSMC_MSG_PowerDownGfx 0x6 50 #define VBIOSSMC_MSG_SetDppclkFreq 0x7 51 #define VBIOSSMC_MSG_SetHardMinDcfclkByFreq 0x8 52 #define VBIOSSMC_MSG_SetMinDeepSleepDcfclk 0x9 53 #define VBIOSSMC_MSG_SetPhyclkVoltageByFreq 0xA 54 #define VBIOSSMC_MSG_GetFclkFrequency 0xB 55 #define VBIOSSMC_MSG_SetDisplayCount 0xC 56 #define VBIOSSMC_MSG_EnableTmdp48MHzRefclkPwrDown 0xD 57 #define VBIOSSMC_MSG_UpdatePmeRestore 0xE 58 #define VBIOSSMC_MSG_IsPeriodicRetrainingDisabled 0xF 59 60 #define VBIOSSMC_Status_BUSY 0x0 61 #define VBIOSSMC_Result_OK 0x1 62 #define VBIOSSMC_Result_Failed 0xFF 63 #define VBIOSSMC_Result_UnknownCmd 0xFE 64 #define VBIOSSMC_Result_CmdRejectedPrereq 0xFD 65 #define VBIOSSMC_Result_CmdRejectedBusy 0xFC 66 67 /* 68 * Function to be used instead of REG_WAIT macro because the wait ends when 69 * the register is NOT EQUAL to zero, and because the translation in msg_if.h 70 * won't work with REG_WAIT. 71 */ 72 static uint32_t rn_smu_wait_for_response(struct clk_mgr_internal *clk_mgr, unsigned int delay_us, unsigned int max_retries) 73 { 74 uint32_t res_val = VBIOSSMC_Status_BUSY; 75 76 do { 77 res_val = REG_READ(MP1_SMN_C2PMSG_91); 78 if (res_val != VBIOSSMC_Status_BUSY) 79 break; 80 81 if (delay_us >= 1000) 82 msleep(delay_us/1000); 83 else if (delay_us > 0) 84 udelay(delay_us); 85 } while (max_retries--); 86 87 return res_val; 88 } 89 90 91 static int rn_vbios_smu_send_msg_with_param(struct clk_mgr_internal *clk_mgr, 92 unsigned int msg_id, 93 unsigned int param) 94 { 95 uint32_t result; 96 97 /* First clear response register */ 98 REG_WRITE(MP1_SMN_C2PMSG_91, VBIOSSMC_Status_BUSY); 99 100 /* Set the parameter register for the SMU message, unit is Mhz */ 101 REG_WRITE(MP1_SMN_C2PMSG_83, param); 102 103 /* Trigger the message transaction by writing the message ID */ 104 REG_WRITE(MP1_SMN_C2PMSG_67, msg_id); 105 106 result = rn_smu_wait_for_response(clk_mgr, 10, 200000); 107 108 ASSERT(result == VBIOSSMC_Result_OK || result == VBIOSSMC_Result_UnknownCmd); 109 110 /* Actual dispclk set is returned in the parameter register */ 111 return REG_READ(MP1_SMN_C2PMSG_83); 112 } 113 114 int rn_vbios_smu_get_smu_version(struct clk_mgr_internal *clk_mgr) 115 { 116 return rn_vbios_smu_send_msg_with_param( 117 clk_mgr, 118 VBIOSSMC_MSG_GetSmuVersion, 119 0); 120 } 121 122 123 int rn_vbios_smu_set_dispclk(struct clk_mgr_internal *clk_mgr, int requested_dispclk_khz) 124 { 125 int actual_dispclk_set_mhz = -1; 126 struct dc *dc = clk_mgr->base.ctx->dc; 127 struct dmcu *dmcu = dc->res_pool->dmcu; 128 129 /* Unit of SMU msg parameter is Mhz */ 130 actual_dispclk_set_mhz = rn_vbios_smu_send_msg_with_param( 131 clk_mgr, 132 VBIOSSMC_MSG_SetDispclkFreq, 133 khz_to_mhz_ceil(requested_dispclk_khz)); 134 135 if (!IS_FPGA_MAXIMUS_DC(dc->ctx->dce_environment)) { 136 if (dmcu && dmcu->funcs->is_dmcu_initialized(dmcu)) { 137 if (clk_mgr->dfs_bypass_disp_clk != actual_dispclk_set_mhz) 138 dmcu->funcs->set_psr_wait_loop(dmcu, 139 actual_dispclk_set_mhz / 7); 140 } 141 } 142 143 // pmfw always set clock more than or equal requested clock 144 if (!IS_DIAG_DC(dc->ctx->dce_environment)) 145 ASSERT(actual_dispclk_set_mhz >= khz_to_mhz_ceil(requested_dispclk_khz)); 146 147 return actual_dispclk_set_mhz * 1000; 148 } 149 150 int rn_vbios_smu_set_dprefclk(struct clk_mgr_internal *clk_mgr) 151 { 152 int actual_dprefclk_set_mhz = -1; 153 154 actual_dprefclk_set_mhz = rn_vbios_smu_send_msg_with_param( 155 clk_mgr, 156 VBIOSSMC_MSG_SetDprefclkFreq, 157 khz_to_mhz_ceil(clk_mgr->base.dprefclk_khz)); 158 159 /* TODO: add code for programing DP DTO, currently this is down by command table */ 160 161 return actual_dprefclk_set_mhz * 1000; 162 } 163 164 int rn_vbios_smu_set_hard_min_dcfclk(struct clk_mgr_internal *clk_mgr, int requested_dcfclk_khz) 165 { 166 int actual_dcfclk_set_mhz = -1; 167 168 if (clk_mgr->smu_ver < 0x370c00) 169 return actual_dcfclk_set_mhz; 170 171 actual_dcfclk_set_mhz = rn_vbios_smu_send_msg_with_param( 172 clk_mgr, 173 VBIOSSMC_MSG_SetHardMinDcfclkByFreq, 174 khz_to_mhz_ceil(requested_dcfclk_khz)); 175 176 return actual_dcfclk_set_mhz * 1000; 177 } 178 179 int rn_vbios_smu_set_min_deep_sleep_dcfclk(struct clk_mgr_internal *clk_mgr, int requested_min_ds_dcfclk_khz) 180 { 181 int actual_min_ds_dcfclk_mhz = -1; 182 183 if (clk_mgr->smu_ver < 0x370c00) 184 return actual_min_ds_dcfclk_mhz; 185 186 actual_min_ds_dcfclk_mhz = rn_vbios_smu_send_msg_with_param( 187 clk_mgr, 188 VBIOSSMC_MSG_SetMinDeepSleepDcfclk, 189 khz_to_mhz_ceil(requested_min_ds_dcfclk_khz)); 190 191 return actual_min_ds_dcfclk_mhz * 1000; 192 } 193 194 void rn_vbios_smu_set_phyclk(struct clk_mgr_internal *clk_mgr, int requested_phyclk_khz) 195 { 196 rn_vbios_smu_send_msg_with_param( 197 clk_mgr, 198 VBIOSSMC_MSG_SetPhyclkVoltageByFreq, 199 khz_to_mhz_ceil(requested_phyclk_khz)); 200 } 201 202 int rn_vbios_smu_set_dppclk(struct clk_mgr_internal *clk_mgr, int requested_dpp_khz) 203 { 204 int actual_dppclk_set_mhz = -1; 205 struct dc *dc = clk_mgr->base.ctx->dc; 206 207 actual_dppclk_set_mhz = rn_vbios_smu_send_msg_with_param( 208 clk_mgr, 209 VBIOSSMC_MSG_SetDppclkFreq, 210 khz_to_mhz_ceil(requested_dpp_khz)); 211 212 if (!IS_DIAG_DC(dc->ctx->dce_environment)) 213 ASSERT(actual_dppclk_set_mhz >= khz_to_mhz_ceil(requested_dpp_khz)); 214 215 return actual_dppclk_set_mhz * 1000; 216 } 217 218 void rn_vbios_smu_set_dcn_low_power_state(struct clk_mgr_internal *clk_mgr, enum dcn_pwr_state state) 219 { 220 int disp_count; 221 222 if (state == DCN_PWR_STATE_LOW_POWER) 223 disp_count = 0; 224 else 225 disp_count = 1; 226 227 rn_vbios_smu_send_msg_with_param( 228 clk_mgr, 229 VBIOSSMC_MSG_SetDisplayCount, 230 disp_count); 231 } 232 233 void rn_vbios_smu_enable_48mhz_tmdp_refclk_pwrdwn(struct clk_mgr_internal *clk_mgr, bool enable) 234 { 235 rn_vbios_smu_send_msg_with_param( 236 clk_mgr, 237 VBIOSSMC_MSG_EnableTmdp48MHzRefclkPwrDown, 238 enable); 239 } 240 241 void rn_vbios_smu_enable_pme_wa(struct clk_mgr_internal *clk_mgr) 242 { 243 rn_vbios_smu_send_msg_with_param( 244 clk_mgr, 245 VBIOSSMC_MSG_UpdatePmeRestore, 246 0); 247 } 248 249 int rn_vbios_smu_is_periodic_retraining_disabled(struct clk_mgr_internal *clk_mgr) 250 { 251 return rn_vbios_smu_send_msg_with_param( 252 clk_mgr, 253 VBIOSSMC_MSG_IsPeriodicRetrainingDisabled, 254 1); // if PMFW doesn't support this message, assume retraining is disabled 255 // so we only use most optimal watermark if we know retraining is enabled. 256 } 257