1 /* 2 * Copyright 2012-16 Advanced Micro Devices, Inc. 3 * 4 * Permission is hereby granted, free of charge, to any person obtaining a 5 * copy of this software and associated documentation files (the "Software"), 6 * to deal in the Software without restriction, including without limitation 7 * the rights to use, copy, modify, merge, publish, distribute, sublicense, 8 * and/or sell copies of the Software, and to permit persons to whom the 9 * Software is furnished to do so, subject to the following conditions: 10 * 11 * The above copyright notice and this permission notice shall be included in 12 * all copies or substantial portions of the Software. 13 * 14 * THE SOFTWARE IS PROVIDED "AS IS", WITHOUT WARRANTY OF ANY KIND, EXPRESS OR 15 * IMPLIED, INCLUDING BUT NOT LIMITED TO THE WARRANTIES OF MERCHANTABILITY, 16 * FITNESS FOR A PARTICULAR PURPOSE AND NONINFRINGEMENT. IN NO EVENT SHALL 17 * THE COPYRIGHT HOLDER(S) OR AUTHOR(S) BE LIABLE FOR ANY CLAIM, DAMAGES OR 18 * OTHER LIABILITY, WHETHER IN AN ACTION OF CONTRACT, TORT OR OTHERWISE, 19 * ARISING FROM, OUT OF OR IN CONNECTION WITH THE SOFTWARE OR THE USE OR 20 * OTHER DEALINGS IN THE SOFTWARE. 21 * 22 * Authors: AMD 23 * 24 */ 25 26 #include "core_types.h" 27 #include "clk_mgr_internal.h" 28 #include "reg_helper.h" 29 #include <linux/delay.h> 30 31 #include "renoir_ip_offset.h" 32 33 #include "mp/mp_12_0_0_offset.h" 34 #include "mp/mp_12_0_0_sh_mask.h" 35 36 #define REG(reg_name) \ 37 (MP0_BASE.instance[0].segment[mm ## reg_name ## _BASE_IDX] + mm ## reg_name) 38 39 #define FN(reg_name, field) \ 40 FD(reg_name##__##field) 41 42 #define VBIOSSMC_MSG_TestMessage 0x1 43 #define VBIOSSMC_MSG_GetSmuVersion 0x2 44 #define VBIOSSMC_MSG_PowerUpGfx 0x3 45 #define VBIOSSMC_MSG_SetDispclkFreq 0x4 46 #define VBIOSSMC_MSG_SetDprefclkFreq 0x5 47 #define VBIOSSMC_MSG_PowerDownGfx 0x6 48 #define VBIOSSMC_MSG_SetDppclkFreq 0x7 49 #define VBIOSSMC_MSG_SetHardMinDcfclkByFreq 0x8 50 #define VBIOSSMC_MSG_SetMinDeepSleepDcfclk 0x9 51 #define VBIOSSMC_MSG_SetPhyclkVoltageByFreq 0xA 52 #define VBIOSSMC_MSG_GetFclkFrequency 0xB 53 #define VBIOSSMC_MSG_SetDisplayCount 0xC 54 #define VBIOSSMC_MSG_EnableTmdp48MHzRefclkPwrDown 0xD 55 #define VBIOSSMC_MSG_UpdatePmeRestore 0xE 56 #define VBIOSSMC_MSG_IsPeriodicRetrainingDisabled 0xF 57 58 #define VBIOSSMC_Status_BUSY 0x0 59 #define VBIOSSMC_Result_OK 0x1 60 #define VBIOSSMC_Result_Failed 0xFF 61 #define VBIOSSMC_Result_UnknownCmd 0xFE 62 #define VBIOSSMC_Result_CmdRejectedPrereq 0xFD 63 #define VBIOSSMC_Result_CmdRejectedBusy 0xFC 64 65 /* 66 * Function to be used instead of REG_WAIT macro because the wait ends when 67 * the register is NOT EQUAL to zero, and because the translation in msg_if.h 68 * won't work with REG_WAIT. 69 */ 70 static uint32_t rn_smu_wait_for_response(struct clk_mgr_internal *clk_mgr, unsigned int delay_us, unsigned int max_retries) 71 { 72 uint32_t res_val = VBIOSSMC_Status_BUSY; 73 74 do { 75 res_val = REG_READ(MP1_SMN_C2PMSG_91); 76 if (res_val != VBIOSSMC_Status_BUSY) 77 break; 78 79 if (delay_us >= 1000) 80 msleep(delay_us/1000); 81 else if (delay_us > 0) 82 udelay(delay_us); 83 } while (max_retries--); 84 85 return res_val; 86 } 87 88 89 int rn_vbios_smu_send_msg_with_param(struct clk_mgr_internal *clk_mgr, unsigned int msg_id, unsigned int param) 90 { 91 uint32_t result; 92 93 /* First clear response register */ 94 REG_WRITE(MP1_SMN_C2PMSG_91, VBIOSSMC_Status_BUSY); 95 96 /* Set the parameter register for the SMU message, unit is Mhz */ 97 REG_WRITE(MP1_SMN_C2PMSG_83, param); 98 99 /* Trigger the message transaction by writing the message ID */ 100 REG_WRITE(MP1_SMN_C2PMSG_67, msg_id); 101 102 result = rn_smu_wait_for_response(clk_mgr, 10, 200000); 103 104 ASSERT(result == VBIOSSMC_Result_OK || result == VBIOSSMC_Result_UnknownCmd); 105 106 /* Actual dispclk set is returned in the parameter register */ 107 return REG_READ(MP1_SMN_C2PMSG_83); 108 } 109 110 int rn_vbios_smu_get_smu_version(struct clk_mgr_internal *clk_mgr) 111 { 112 return rn_vbios_smu_send_msg_with_param( 113 clk_mgr, 114 VBIOSSMC_MSG_GetSmuVersion, 115 0); 116 } 117 118 119 int rn_vbios_smu_set_dispclk(struct clk_mgr_internal *clk_mgr, int requested_dispclk_khz) 120 { 121 int actual_dispclk_set_mhz = -1; 122 struct dc *dc = clk_mgr->base.ctx->dc; 123 struct dmcu *dmcu = dc->res_pool->dmcu; 124 125 /* Unit of SMU msg parameter is Mhz */ 126 actual_dispclk_set_mhz = rn_vbios_smu_send_msg_with_param( 127 clk_mgr, 128 VBIOSSMC_MSG_SetDispclkFreq, 129 requested_dispclk_khz / 1000); 130 131 if (!IS_FPGA_MAXIMUS_DC(dc->ctx->dce_environment)) { 132 if (dmcu && dmcu->funcs->is_dmcu_initialized(dmcu)) { 133 if (clk_mgr->dfs_bypass_disp_clk != actual_dispclk_set_mhz) 134 dmcu->funcs->set_psr_wait_loop(dmcu, 135 actual_dispclk_set_mhz / 7); 136 } 137 } 138 139 // pmfw always set clock more than or equal requested clock 140 if (!IS_DIAG_DC(dc->ctx->dce_environment)) 141 ASSERT(actual_dispclk_set_mhz >= requested_dispclk_khz / 1000); 142 143 return actual_dispclk_set_mhz * 1000; 144 } 145 146 int rn_vbios_smu_set_dprefclk(struct clk_mgr_internal *clk_mgr) 147 { 148 int actual_dprefclk_set_mhz = -1; 149 150 actual_dprefclk_set_mhz = rn_vbios_smu_send_msg_with_param( 151 clk_mgr, 152 VBIOSSMC_MSG_SetDprefclkFreq, 153 clk_mgr->base.dprefclk_khz / 1000); 154 155 /* TODO: add code for programing DP DTO, currently this is down by command table */ 156 157 return actual_dprefclk_set_mhz * 1000; 158 } 159 160 int rn_vbios_smu_set_hard_min_dcfclk(struct clk_mgr_internal *clk_mgr, int requested_dcfclk_khz) 161 { 162 int actual_dcfclk_set_mhz = -1; 163 164 if (clk_mgr->smu_ver < 0x370c00) 165 return actual_dcfclk_set_mhz; 166 167 actual_dcfclk_set_mhz = rn_vbios_smu_send_msg_with_param( 168 clk_mgr, 169 VBIOSSMC_MSG_SetHardMinDcfclkByFreq, 170 requested_dcfclk_khz / 1000); 171 172 return actual_dcfclk_set_mhz * 1000; 173 } 174 175 int rn_vbios_smu_set_min_deep_sleep_dcfclk(struct clk_mgr_internal *clk_mgr, int requested_min_ds_dcfclk_khz) 176 { 177 int actual_min_ds_dcfclk_mhz = -1; 178 179 if (clk_mgr->smu_ver < 0x370c00) 180 return actual_min_ds_dcfclk_mhz; 181 182 actual_min_ds_dcfclk_mhz = rn_vbios_smu_send_msg_with_param( 183 clk_mgr, 184 VBIOSSMC_MSG_SetMinDeepSleepDcfclk, 185 requested_min_ds_dcfclk_khz / 1000); 186 187 return actual_min_ds_dcfclk_mhz * 1000; 188 } 189 190 void rn_vbios_smu_set_phyclk(struct clk_mgr_internal *clk_mgr, int requested_phyclk_khz) 191 { 192 rn_vbios_smu_send_msg_with_param( 193 clk_mgr, 194 VBIOSSMC_MSG_SetPhyclkVoltageByFreq, 195 requested_phyclk_khz / 1000); 196 } 197 198 int rn_vbios_smu_set_dppclk(struct clk_mgr_internal *clk_mgr, int requested_dpp_khz) 199 { 200 int actual_dppclk_set_mhz = -1; 201 struct dc *dc = clk_mgr->base.ctx->dc; 202 203 actual_dppclk_set_mhz = rn_vbios_smu_send_msg_with_param( 204 clk_mgr, 205 VBIOSSMC_MSG_SetDppclkFreq, 206 requested_dpp_khz / 1000); 207 208 if (!IS_DIAG_DC(dc->ctx->dce_environment)) 209 ASSERT(actual_dppclk_set_mhz >= requested_dpp_khz / 1000); 210 211 return actual_dppclk_set_mhz * 1000; 212 } 213 214 void rn_vbios_smu_set_dcn_low_power_state(struct clk_mgr_internal *clk_mgr, enum dcn_pwr_state state) 215 { 216 int disp_count; 217 218 if (state == DCN_PWR_STATE_LOW_POWER) 219 disp_count = 0; 220 else 221 disp_count = 1; 222 223 rn_vbios_smu_send_msg_with_param( 224 clk_mgr, 225 VBIOSSMC_MSG_SetDisplayCount, 226 disp_count); 227 } 228 229 void rn_vbios_smu_enable_48mhz_tmdp_refclk_pwrdwn(struct clk_mgr_internal *clk_mgr, bool enable) 230 { 231 rn_vbios_smu_send_msg_with_param( 232 clk_mgr, 233 VBIOSSMC_MSG_EnableTmdp48MHzRefclkPwrDown, 234 enable); 235 } 236 237 void rn_vbios_smu_enable_pme_wa(struct clk_mgr_internal *clk_mgr) 238 { 239 rn_vbios_smu_send_msg_with_param( 240 clk_mgr, 241 VBIOSSMC_MSG_UpdatePmeRestore, 242 0); 243 } 244 245 int rn_vbios_smu_is_periodic_retraining_disabled(struct clk_mgr_internal *clk_mgr) 246 { 247 return rn_vbios_smu_send_msg_with_param( 248 clk_mgr, 249 VBIOSSMC_MSG_IsPeriodicRetrainingDisabled, 250 1); // if PMFW doesn't support this message, assume retraining is disabled 251 // so we only use most optimal watermark if we know retraining is enabled. 252 } 253