1 /* 2 * Copyright 2018 Advanced Micro Devices, Inc. 3 * 4 * Permission is hereby granted, free of charge, to any person obtaining a 5 * copy of this software and associated documentation files (the "Software"), 6 * to deal in the Software without restriction, including without limitation 7 * the rights to use, copy, modify, merge, publish, distribute, sublicense, 8 * and/or sell copies of the Software, and to permit persons to whom the 9 * Software is furnished to do so, subject to the following conditions: 10 * 11 * The above copyright notice and this permission notice shall be included in 12 * all copies or substantial portions of the Software. 13 * 14 * THE SOFTWARE IS PROVIDED "AS IS", WITHOUT WARRANTY OF ANY KIND, EXPRESS OR 15 * IMPLIED, INCLUDING BUT NOT LIMITED TO THE WARRANTIES OF MERCHANTABILITY, 16 * FITNESS FOR A PARTICULAR PURPOSE AND NONINFRINGEMENT. IN NO EVENT SHALL 17 * THE COPYRIGHT HOLDER(S) OR AUTHOR(S) BE LIABLE FOR ANY CLAIM, DAMAGES OR 18 * OTHER LIABILITY, WHETHER IN AN ACTION OF CONTRACT, TORT OR OTHERWISE, 19 * ARISING FROM, OUT OF OR IN CONNECTION WITH THE SOFTWARE OR THE USE OR 20 * OTHER DEALINGS IN THE SOFTWARE. 21 * 22 * Authors: AMD 23 * 24 */ 25 26 #include "dccg.h" 27 #include "clk_mgr_internal.h" 28 29 30 #include "dcn20/dcn20_clk_mgr.h" 31 #include "rn_clk_mgr.h" 32 33 34 #include "dce100/dce_clk_mgr.h" 35 #include "rn_clk_mgr_vbios_smu.h" 36 #include "reg_helper.h" 37 #include "core_types.h" 38 #include "dm_helpers.h" 39 40 #include "atomfirmware.h" 41 #include "clk/clk_10_0_2_offset.h" 42 #include "clk/clk_10_0_2_sh_mask.h" 43 #include "renoir_ip_offset.h" 44 45 46 /* Constants */ 47 48 #define LPDDR_MEM_RETRAIN_LATENCY 4.977 /* Number obtained from LPDDR4 Training Counter Requirement doc */ 49 #define SMU_VER_55_51_0 0x373300 /* SMU Version that is able to set DISPCLK below 100MHz */ 50 51 /* Macros */ 52 53 #define REG(reg_name) \ 54 (CLK_BASE.instance[0].segment[mm ## reg_name ## _BASE_IDX] + mm ## reg_name) 55 56 57 /* TODO: evaluate how to lower or disable all dcn clocks in screen off case */ 58 int rn_get_active_display_cnt_wa( 59 struct dc *dc, 60 struct dc_state *context) 61 { 62 int i, display_count; 63 bool tmds_present = false; 64 65 display_count = 0; 66 for (i = 0; i < context->stream_count; i++) { 67 const struct dc_stream_state *stream = context->streams[i]; 68 69 if (stream->signal == SIGNAL_TYPE_HDMI_TYPE_A || 70 stream->signal == SIGNAL_TYPE_DVI_SINGLE_LINK || 71 stream->signal == SIGNAL_TYPE_DVI_DUAL_LINK) 72 tmds_present = true; 73 } 74 75 for (i = 0; i < dc->link_count; i++) { 76 const struct dc_link *link = dc->links[i]; 77 78 /* 79 * Only notify active stream or virtual stream. 80 * Need to notify virtual stream to work around 81 * headless case. HPD does not fire when system is in 82 * S0i2. 83 */ 84 /* abusing the fact that the dig and phy are coupled to see if the phy is enabled */ 85 if (link->connector_signal == SIGNAL_TYPE_VIRTUAL || 86 link->link_enc->funcs->is_dig_enabled(link->link_enc)) 87 display_count++; 88 } 89 90 /* WA for hang on HDMI after display off back back on*/ 91 if (display_count == 0 && tmds_present) 92 display_count = 1; 93 94 return display_count; 95 } 96 97 void rn_set_low_power_state(struct clk_mgr *clk_mgr_base) 98 { 99 struct clk_mgr_internal *clk_mgr = TO_CLK_MGR_INTERNAL(clk_mgr_base); 100 101 rn_vbios_smu_set_dcn_low_power_state(clk_mgr, DCN_PWR_STATE_LOW_POWER); 102 /* update power state */ 103 clk_mgr_base->clks.pwr_state = DCN_PWR_STATE_LOW_POWER; 104 } 105 106 void rn_update_clocks(struct clk_mgr *clk_mgr_base, 107 struct dc_state *context, 108 bool safe_to_lower) 109 { 110 struct clk_mgr_internal *clk_mgr = TO_CLK_MGR_INTERNAL(clk_mgr_base); 111 struct dc_clocks *new_clocks = &context->bw_ctx.bw.dcn.clk; 112 struct dc *dc = clk_mgr_base->ctx->dc; 113 int display_count; 114 bool update_dppclk = false; 115 bool update_dispclk = false; 116 bool dpp_clock_lowered = false; 117 118 struct dmcu *dmcu = clk_mgr_base->ctx->dc->res_pool->dmcu; 119 120 if (dc->work_arounds.skip_clock_update) 121 return; 122 123 /* 124 * if it is safe to lower, but we are already in the lower state, we don't have to do anything 125 * also if safe to lower is false, we just go in the higher state 126 */ 127 if (safe_to_lower) { 128 /* check that we're not already in lower */ 129 if (clk_mgr_base->clks.pwr_state != DCN_PWR_STATE_LOW_POWER) { 130 131 display_count = rn_get_active_display_cnt_wa(dc, context); 132 /* if we can go lower, go lower */ 133 if (display_count == 0) { 134 rn_vbios_smu_set_dcn_low_power_state(clk_mgr, DCN_PWR_STATE_LOW_POWER); 135 /* update power state */ 136 clk_mgr_base->clks.pwr_state = DCN_PWR_STATE_LOW_POWER; 137 } 138 } 139 } else { 140 /* check that we're not already in D0 */ 141 if (clk_mgr_base->clks.pwr_state != DCN_PWR_STATE_MISSION_MODE) { 142 rn_vbios_smu_set_dcn_low_power_state(clk_mgr, DCN_PWR_STATE_MISSION_MODE); 143 /* update power state */ 144 clk_mgr_base->clks.pwr_state = DCN_PWR_STATE_MISSION_MODE; 145 } 146 } 147 148 if (should_set_clock(safe_to_lower, new_clocks->dcfclk_khz, clk_mgr_base->clks.dcfclk_khz)) { 149 clk_mgr_base->clks.dcfclk_khz = new_clocks->dcfclk_khz; 150 rn_vbios_smu_set_hard_min_dcfclk(clk_mgr, clk_mgr_base->clks.dcfclk_khz); 151 } 152 153 if (should_set_clock(safe_to_lower, 154 new_clocks->dcfclk_deep_sleep_khz, clk_mgr_base->clks.dcfclk_deep_sleep_khz)) { 155 clk_mgr_base->clks.dcfclk_deep_sleep_khz = new_clocks->dcfclk_deep_sleep_khz; 156 rn_vbios_smu_set_min_deep_sleep_dcfclk(clk_mgr, clk_mgr_base->clks.dcfclk_deep_sleep_khz); 157 } 158 159 // workaround: Limit dppclk to 100Mhz to avoid lower eDP panel switch to plus 4K monitor underflow. 160 // Do not adjust dppclk if dppclk is 0 to avoid unexpected result 161 if (!IS_DIAG_DC(dc->ctx->dce_environment)) { 162 if (new_clocks->dppclk_khz < 100000 && new_clocks->dppclk_khz > 0) 163 new_clocks->dppclk_khz = 100000; 164 } 165 166 if (should_set_clock(safe_to_lower, new_clocks->dppclk_khz, clk_mgr->base.clks.dppclk_khz)) { 167 if (clk_mgr->base.clks.dppclk_khz > new_clocks->dppclk_khz) 168 dpp_clock_lowered = true; 169 clk_mgr_base->clks.dppclk_khz = new_clocks->dppclk_khz; 170 update_dppclk = true; 171 } 172 173 if (should_set_clock(safe_to_lower, new_clocks->dispclk_khz, clk_mgr_base->clks.dispclk_khz)) { 174 clk_mgr_base->clks.dispclk_khz = new_clocks->dispclk_khz; 175 rn_vbios_smu_set_dispclk(clk_mgr, clk_mgr_base->clks.dispclk_khz); 176 177 update_dispclk = true; 178 } 179 180 if (dpp_clock_lowered) { 181 // increase per DPP DTO before lowering global dppclk 182 dcn20_update_clocks_update_dpp_dto(clk_mgr, context, safe_to_lower); 183 rn_vbios_smu_set_dppclk(clk_mgr, clk_mgr_base->clks.dppclk_khz); 184 } else { 185 // increase global DPPCLK before lowering per DPP DTO 186 if (update_dppclk || update_dispclk) 187 rn_vbios_smu_set_dppclk(clk_mgr, clk_mgr_base->clks.dppclk_khz); 188 // always update dtos unless clock is lowered and not safe to lower 189 if (new_clocks->dppclk_khz >= dc->current_state->bw_ctx.bw.dcn.clk.dppclk_khz) 190 dcn20_update_clocks_update_dpp_dto(clk_mgr, context, safe_to_lower); 191 } 192 193 if (update_dispclk && 194 dmcu && dmcu->funcs->is_dmcu_initialized(dmcu)) { 195 /*update dmcu for wait_loop count*/ 196 dmcu->funcs->set_psr_wait_loop(dmcu, 197 clk_mgr_base->clks.dispclk_khz / 1000 / 7); 198 } 199 } 200 201 202 static int get_vco_frequency_from_reg(struct clk_mgr_internal *clk_mgr) 203 { 204 /* get FbMult value */ 205 struct fixed31_32 pll_req; 206 unsigned int fbmult_frac_val = 0; 207 unsigned int fbmult_int_val = 0; 208 209 210 /* 211 * Register value of fbmult is in 8.16 format, we are converting to 31.32 212 * to leverage the fix point operations available in driver 213 */ 214 215 REG_GET(CLK1_CLK_PLL_REQ, FbMult_frac, &fbmult_frac_val); /* 16 bit fractional part*/ 216 REG_GET(CLK1_CLK_PLL_REQ, FbMult_int, &fbmult_int_val); /* 8 bit integer part */ 217 218 pll_req = dc_fixpt_from_int(fbmult_int_val); 219 220 /* 221 * since fractional part is only 16 bit in register definition but is 32 bit 222 * in our fix point definiton, need to shift left by 16 to obtain correct value 223 */ 224 pll_req.value |= fbmult_frac_val << 16; 225 226 /* multiply by REFCLK period */ 227 pll_req = dc_fixpt_mul_int(pll_req, clk_mgr->dfs_ref_freq_khz); 228 229 /* integer part is now VCO frequency in kHz */ 230 return dc_fixpt_floor(pll_req); 231 } 232 233 static void rn_dump_clk_registers_internal(struct rn_clk_internal *internal, struct clk_mgr *clk_mgr_base) 234 { 235 struct clk_mgr_internal *clk_mgr = TO_CLK_MGR_INTERNAL(clk_mgr_base); 236 237 internal->CLK1_CLK3_CURRENT_CNT = REG_READ(CLK1_CLK3_CURRENT_CNT); 238 internal->CLK1_CLK3_BYPASS_CNTL = REG_READ(CLK1_CLK3_BYPASS_CNTL); 239 240 internal->CLK1_CLK3_DS_CNTL = REG_READ(CLK1_CLK3_DS_CNTL); //dcf deep sleep divider 241 internal->CLK1_CLK3_ALLOW_DS = REG_READ(CLK1_CLK3_ALLOW_DS); 242 243 internal->CLK1_CLK1_CURRENT_CNT = REG_READ(CLK1_CLK1_CURRENT_CNT); 244 internal->CLK1_CLK1_BYPASS_CNTL = REG_READ(CLK1_CLK1_BYPASS_CNTL); 245 246 internal->CLK1_CLK2_CURRENT_CNT = REG_READ(CLK1_CLK2_CURRENT_CNT); 247 internal->CLK1_CLK2_BYPASS_CNTL = REG_READ(CLK1_CLK2_BYPASS_CNTL); 248 249 internal->CLK1_CLK0_CURRENT_CNT = REG_READ(CLK1_CLK0_CURRENT_CNT); 250 internal->CLK1_CLK0_BYPASS_CNTL = REG_READ(CLK1_CLK0_BYPASS_CNTL); 251 } 252 253 /* This function collect raw clk register values */ 254 static void rn_dump_clk_registers(struct clk_state_registers_and_bypass *regs_and_bypass, 255 struct clk_mgr *clk_mgr_base, struct clk_log_info *log_info) 256 { 257 struct rn_clk_internal internal = {0}; 258 char *bypass_clks[5] = {"0x0 DFS", "0x1 REFCLK", "0x2 ERROR", "0x3 400 FCH", "0x4 600 FCH"}; 259 unsigned int chars_printed = 0; 260 unsigned int remaining_buffer = log_info->bufSize; 261 262 rn_dump_clk_registers_internal(&internal, clk_mgr_base); 263 264 regs_and_bypass->dcfclk = internal.CLK1_CLK3_CURRENT_CNT / 10; 265 regs_and_bypass->dcf_deep_sleep_divider = internal.CLK1_CLK3_DS_CNTL / 10; 266 regs_and_bypass->dcf_deep_sleep_allow = internal.CLK1_CLK3_ALLOW_DS; 267 regs_and_bypass->dprefclk = internal.CLK1_CLK2_CURRENT_CNT / 10; 268 regs_and_bypass->dispclk = internal.CLK1_CLK0_CURRENT_CNT / 10; 269 regs_and_bypass->dppclk = internal.CLK1_CLK1_CURRENT_CNT / 10; 270 271 regs_and_bypass->dppclk_bypass = internal.CLK1_CLK1_BYPASS_CNTL & 0x0007; 272 if (regs_and_bypass->dppclk_bypass < 0 || regs_and_bypass->dppclk_bypass > 4) 273 regs_and_bypass->dppclk_bypass = 0; 274 regs_and_bypass->dcfclk_bypass = internal.CLK1_CLK3_BYPASS_CNTL & 0x0007; 275 if (regs_and_bypass->dcfclk_bypass < 0 || regs_and_bypass->dcfclk_bypass > 4) 276 regs_and_bypass->dcfclk_bypass = 0; 277 regs_and_bypass->dispclk_bypass = internal.CLK1_CLK0_BYPASS_CNTL & 0x0007; 278 if (regs_and_bypass->dispclk_bypass < 0 || regs_and_bypass->dispclk_bypass > 4) 279 regs_and_bypass->dispclk_bypass = 0; 280 regs_and_bypass->dprefclk_bypass = internal.CLK1_CLK2_BYPASS_CNTL & 0x0007; 281 if (regs_and_bypass->dprefclk_bypass < 0 || regs_and_bypass->dprefclk_bypass > 4) 282 regs_and_bypass->dprefclk_bypass = 0; 283 284 if (log_info->enabled) { 285 chars_printed = snprintf_count(log_info->pBuf, remaining_buffer, "clk_type,clk_value,deepsleep_cntl,deepsleep_allow,bypass\n"); 286 remaining_buffer -= chars_printed; 287 *log_info->sum_chars_printed += chars_printed; 288 log_info->pBuf += chars_printed; 289 290 chars_printed = snprintf_count(log_info->pBuf, remaining_buffer, "dcfclk,%d,%d,%d,%s\n", 291 regs_and_bypass->dcfclk, 292 regs_and_bypass->dcf_deep_sleep_divider, 293 regs_and_bypass->dcf_deep_sleep_allow, 294 bypass_clks[(int) regs_and_bypass->dcfclk_bypass]); 295 remaining_buffer -= chars_printed; 296 *log_info->sum_chars_printed += chars_printed; 297 log_info->pBuf += chars_printed; 298 299 chars_printed = snprintf_count(log_info->pBuf, remaining_buffer, "dprefclk,%d,N/A,N/A,%s\n", 300 regs_and_bypass->dprefclk, 301 bypass_clks[(int) regs_and_bypass->dprefclk_bypass]); 302 remaining_buffer -= chars_printed; 303 *log_info->sum_chars_printed += chars_printed; 304 log_info->pBuf += chars_printed; 305 306 chars_printed = snprintf_count(log_info->pBuf, remaining_buffer, "dispclk,%d,N/A,N/A,%s\n", 307 regs_and_bypass->dispclk, 308 bypass_clks[(int) regs_and_bypass->dispclk_bypass]); 309 remaining_buffer -= chars_printed; 310 *log_info->sum_chars_printed += chars_printed; 311 log_info->pBuf += chars_printed; 312 313 //split 314 chars_printed = snprintf_count(log_info->pBuf, remaining_buffer, "SPLIT\n"); 315 remaining_buffer -= chars_printed; 316 *log_info->sum_chars_printed += chars_printed; 317 log_info->pBuf += chars_printed; 318 319 // REGISTER VALUES 320 chars_printed = snprintf_count(log_info->pBuf, remaining_buffer, "reg_name,value,clk_type\n"); 321 remaining_buffer -= chars_printed; 322 *log_info->sum_chars_printed += chars_printed; 323 log_info->pBuf += chars_printed; 324 325 chars_printed = snprintf_count(log_info->pBuf, remaining_buffer, "CLK1_CLK3_CURRENT_CNT,%d,dcfclk\n", 326 internal.CLK1_CLK3_CURRENT_CNT); 327 remaining_buffer -= chars_printed; 328 *log_info->sum_chars_printed += chars_printed; 329 log_info->pBuf += chars_printed; 330 331 chars_printed = snprintf_count(log_info->pBuf, remaining_buffer, "CLK1_CLK3_DS_CNTL,%d,dcf_deep_sleep_divider\n", 332 internal.CLK1_CLK3_DS_CNTL); 333 remaining_buffer -= chars_printed; 334 *log_info->sum_chars_printed += chars_printed; 335 log_info->pBuf += chars_printed; 336 337 chars_printed = snprintf_count(log_info->pBuf, remaining_buffer, "CLK1_CLK3_ALLOW_DS,%d,dcf_deep_sleep_allow\n", 338 internal.CLK1_CLK3_ALLOW_DS); 339 remaining_buffer -= chars_printed; 340 *log_info->sum_chars_printed += chars_printed; 341 log_info->pBuf += chars_printed; 342 343 chars_printed = snprintf_count(log_info->pBuf, remaining_buffer, "CLK1_CLK2_CURRENT_CNT,%d,dprefclk\n", 344 internal.CLK1_CLK2_CURRENT_CNT); 345 remaining_buffer -= chars_printed; 346 *log_info->sum_chars_printed += chars_printed; 347 log_info->pBuf += chars_printed; 348 349 chars_printed = snprintf_count(log_info->pBuf, remaining_buffer, "CLK1_CLK0_CURRENT_CNT,%d,dispclk\n", 350 internal.CLK1_CLK0_CURRENT_CNT); 351 remaining_buffer -= chars_printed; 352 *log_info->sum_chars_printed += chars_printed; 353 log_info->pBuf += chars_printed; 354 355 chars_printed = snprintf_count(log_info->pBuf, remaining_buffer, "CLK1_CLK1_CURRENT_CNT,%d,dppclk\n", 356 internal.CLK1_CLK1_CURRENT_CNT); 357 remaining_buffer -= chars_printed; 358 *log_info->sum_chars_printed += chars_printed; 359 log_info->pBuf += chars_printed; 360 361 chars_printed = snprintf_count(log_info->pBuf, remaining_buffer, "CLK1_CLK3_BYPASS_CNTL,%d,dcfclk_bypass\n", 362 internal.CLK1_CLK3_BYPASS_CNTL); 363 remaining_buffer -= chars_printed; 364 *log_info->sum_chars_printed += chars_printed; 365 log_info->pBuf += chars_printed; 366 367 chars_printed = snprintf_count(log_info->pBuf, remaining_buffer, "CLK1_CLK2_BYPASS_CNTL,%d,dprefclk_bypass\n", 368 internal.CLK1_CLK2_BYPASS_CNTL); 369 remaining_buffer -= chars_printed; 370 *log_info->sum_chars_printed += chars_printed; 371 log_info->pBuf += chars_printed; 372 373 chars_printed = snprintf_count(log_info->pBuf, remaining_buffer, "CLK1_CLK0_BYPASS_CNTL,%d,dispclk_bypass\n", 374 internal.CLK1_CLK0_BYPASS_CNTL); 375 remaining_buffer -= chars_printed; 376 *log_info->sum_chars_printed += chars_printed; 377 log_info->pBuf += chars_printed; 378 379 chars_printed = snprintf_count(log_info->pBuf, remaining_buffer, "CLK1_CLK1_BYPASS_CNTL,%d,dppclk_bypass\n", 380 internal.CLK1_CLK1_BYPASS_CNTL); 381 remaining_buffer -= chars_printed; 382 *log_info->sum_chars_printed += chars_printed; 383 log_info->pBuf += chars_printed; 384 } 385 } 386 387 /* This function produce translated logical clk state values*/ 388 void rn_get_clk_states(struct clk_mgr *clk_mgr_base, struct clk_states *s) 389 { 390 struct clk_state_registers_and_bypass sb = { 0 }; 391 struct clk_log_info log_info = { 0 }; 392 393 rn_dump_clk_registers(&sb, clk_mgr_base, &log_info); 394 395 s->dprefclk_khz = sb.dprefclk * 1000; 396 } 397 398 void rn_enable_pme_wa(struct clk_mgr *clk_mgr_base) 399 { 400 struct clk_mgr_internal *clk_mgr = TO_CLK_MGR_INTERNAL(clk_mgr_base); 401 402 rn_vbios_smu_enable_pme_wa(clk_mgr); 403 } 404 405 void rn_init_clocks(struct clk_mgr *clk_mgr) 406 { 407 memset(&(clk_mgr->clks), 0, sizeof(struct dc_clocks)); 408 // Assumption is that boot state always supports pstate 409 clk_mgr->clks.p_state_change_support = true; 410 clk_mgr->clks.prev_p_state_change_support = true; 411 clk_mgr->clks.pwr_state = DCN_PWR_STATE_UNKNOWN; 412 } 413 414 static void build_watermark_ranges(struct clk_bw_params *bw_params, struct pp_smu_wm_range_sets *ranges) 415 { 416 int i, num_valid_sets; 417 418 num_valid_sets = 0; 419 420 for (i = 0; i < WM_SET_COUNT; i++) { 421 /* skip empty entries, the smu array has no holes*/ 422 if (!bw_params->wm_table.entries[i].valid) 423 continue; 424 425 ranges->reader_wm_sets[num_valid_sets].wm_inst = bw_params->wm_table.entries[i].wm_inst; 426 ranges->reader_wm_sets[num_valid_sets].wm_type = bw_params->wm_table.entries[i].wm_type; 427 /* We will not select WM based on fclk, so leave it as unconstrained */ 428 ranges->reader_wm_sets[num_valid_sets].min_fill_clk_mhz = PP_SMU_WM_SET_RANGE_CLK_UNCONSTRAINED_MIN; 429 ranges->reader_wm_sets[num_valid_sets].max_fill_clk_mhz = PP_SMU_WM_SET_RANGE_CLK_UNCONSTRAINED_MAX; 430 /* dcfclk wil be used to select WM*/ 431 432 if (ranges->reader_wm_sets[num_valid_sets].wm_type == WM_TYPE_PSTATE_CHG) { 433 if (i == 0) 434 ranges->reader_wm_sets[num_valid_sets].min_drain_clk_mhz = 0; 435 else { 436 /* add 1 to make it non-overlapping with next lvl */ 437 ranges->reader_wm_sets[num_valid_sets].min_drain_clk_mhz = bw_params->clk_table.entries[i - 1].dcfclk_mhz + 1; 438 } 439 ranges->reader_wm_sets[num_valid_sets].max_drain_clk_mhz = bw_params->clk_table.entries[i].dcfclk_mhz; 440 441 } else { 442 /* unconstrained for memory retraining */ 443 ranges->reader_wm_sets[num_valid_sets].min_fill_clk_mhz = PP_SMU_WM_SET_RANGE_CLK_UNCONSTRAINED_MIN; 444 ranges->reader_wm_sets[num_valid_sets].max_fill_clk_mhz = PP_SMU_WM_SET_RANGE_CLK_UNCONSTRAINED_MAX; 445 446 /* Modify previous watermark range to cover up to max */ 447 ranges->reader_wm_sets[num_valid_sets - 1].max_fill_clk_mhz = PP_SMU_WM_SET_RANGE_CLK_UNCONSTRAINED_MAX; 448 } 449 num_valid_sets++; 450 } 451 452 ASSERT(num_valid_sets != 0); /* Must have at least one set of valid watermarks */ 453 ranges->num_reader_wm_sets = num_valid_sets; 454 455 /* modify the min and max to make sure we cover the whole range*/ 456 ranges->reader_wm_sets[0].min_drain_clk_mhz = PP_SMU_WM_SET_RANGE_CLK_UNCONSTRAINED_MIN; 457 ranges->reader_wm_sets[0].min_fill_clk_mhz = PP_SMU_WM_SET_RANGE_CLK_UNCONSTRAINED_MIN; 458 ranges->reader_wm_sets[ranges->num_reader_wm_sets - 1].max_drain_clk_mhz = PP_SMU_WM_SET_RANGE_CLK_UNCONSTRAINED_MAX; 459 ranges->reader_wm_sets[ranges->num_reader_wm_sets - 1].max_fill_clk_mhz = PP_SMU_WM_SET_RANGE_CLK_UNCONSTRAINED_MAX; 460 461 /* This is for writeback only, does not matter currently as no writeback support*/ 462 ranges->num_writer_wm_sets = 1; 463 ranges->writer_wm_sets[0].wm_inst = WM_A; 464 ranges->writer_wm_sets[0].min_fill_clk_mhz = PP_SMU_WM_SET_RANGE_CLK_UNCONSTRAINED_MIN; 465 ranges->writer_wm_sets[0].max_fill_clk_mhz = PP_SMU_WM_SET_RANGE_CLK_UNCONSTRAINED_MAX; 466 ranges->writer_wm_sets[0].min_drain_clk_mhz = PP_SMU_WM_SET_RANGE_CLK_UNCONSTRAINED_MIN; 467 ranges->writer_wm_sets[0].max_drain_clk_mhz = PP_SMU_WM_SET_RANGE_CLK_UNCONSTRAINED_MAX; 468 469 } 470 471 static void rn_notify_wm_ranges(struct clk_mgr *clk_mgr_base) 472 { 473 struct dc_debug_options *debug = &clk_mgr_base->ctx->dc->debug; 474 struct clk_mgr_internal *clk_mgr = TO_CLK_MGR_INTERNAL(clk_mgr_base); 475 struct pp_smu_funcs *pp_smu = clk_mgr->pp_smu; 476 477 if (!debug->disable_pplib_wm_range) { 478 build_watermark_ranges(clk_mgr_base->bw_params, &clk_mgr_base->ranges); 479 480 /* Notify PP Lib/SMU which Watermarks to use for which clock ranges */ 481 if (pp_smu && pp_smu->rn_funcs.set_wm_ranges) 482 pp_smu->rn_funcs.set_wm_ranges(&pp_smu->rn_funcs.pp_smu, &clk_mgr_base->ranges); 483 } 484 485 } 486 487 static bool rn_are_clock_states_equal(struct dc_clocks *a, 488 struct dc_clocks *b) 489 { 490 if (a->dispclk_khz != b->dispclk_khz) 491 return false; 492 else if (a->dppclk_khz != b->dppclk_khz) 493 return false; 494 else if (a->dcfclk_khz != b->dcfclk_khz) 495 return false; 496 else if (a->dcfclk_deep_sleep_khz != b->dcfclk_deep_sleep_khz) 497 return false; 498 499 return true; 500 } 501 502 503 /* Notify clk_mgr of a change in link rate, update phyclk frequency if necessary */ 504 static void rn_notify_link_rate_change(struct clk_mgr *clk_mgr_base, struct dc_link *link) 505 { 506 struct clk_mgr_internal *clk_mgr = TO_CLK_MGR_INTERNAL(clk_mgr_base); 507 unsigned int i, max_phyclk_req = 0; 508 509 clk_mgr->cur_phyclk_req_table[link->link_index] = link->cur_link_settings.link_rate * LINK_RATE_REF_FREQ_IN_KHZ; 510 511 for (i = 0; i < MAX_PIPES * 2; i++) { 512 if (clk_mgr->cur_phyclk_req_table[i] > max_phyclk_req) 513 max_phyclk_req = clk_mgr->cur_phyclk_req_table[i]; 514 } 515 516 if (max_phyclk_req != clk_mgr_base->clks.phyclk_khz) { 517 clk_mgr_base->clks.phyclk_khz = max_phyclk_req; 518 rn_vbios_smu_set_phyclk(clk_mgr, clk_mgr_base->clks.phyclk_khz); 519 } 520 } 521 522 static struct clk_mgr_funcs dcn21_funcs = { 523 .get_dp_ref_clk_frequency = dce12_get_dp_ref_freq_khz, 524 .update_clocks = rn_update_clocks, 525 .init_clocks = rn_init_clocks, 526 .enable_pme_wa = rn_enable_pme_wa, 527 .are_clock_states_equal = rn_are_clock_states_equal, 528 .set_low_power_state = rn_set_low_power_state, 529 .notify_wm_ranges = rn_notify_wm_ranges, 530 .notify_link_rate_change = rn_notify_link_rate_change, 531 }; 532 533 static struct clk_bw_params rn_bw_params = { 534 .vram_type = Ddr4MemType, 535 .num_channels = 1, 536 .clk_table = { 537 .entries = { 538 { 539 .voltage = 0, 540 .dcfclk_mhz = 400, 541 .fclk_mhz = 400, 542 .memclk_mhz = 800, 543 .socclk_mhz = 0, 544 }, 545 { 546 .voltage = 0, 547 .dcfclk_mhz = 483, 548 .fclk_mhz = 800, 549 .memclk_mhz = 1600, 550 .socclk_mhz = 0, 551 }, 552 { 553 .voltage = 0, 554 .dcfclk_mhz = 602, 555 .fclk_mhz = 1067, 556 .memclk_mhz = 1067, 557 .socclk_mhz = 0, 558 }, 559 { 560 .voltage = 0, 561 .dcfclk_mhz = 738, 562 .fclk_mhz = 1333, 563 .memclk_mhz = 1600, 564 .socclk_mhz = 0, 565 }, 566 }, 567 568 .num_entries = 4, 569 }, 570 571 }; 572 573 static struct wm_table ddr4_wm_table = { 574 .entries = { 575 { 576 .wm_inst = WM_A, 577 .wm_type = WM_TYPE_PSTATE_CHG, 578 .pstate_latency_us = 11.72, 579 .sr_exit_time_us = 6.09, 580 .sr_enter_plus_exit_time_us = 7.14, 581 .valid = true, 582 }, 583 { 584 .wm_inst = WM_B, 585 .wm_type = WM_TYPE_PSTATE_CHG, 586 .pstate_latency_us = 11.72, 587 .sr_exit_time_us = 10.12, 588 .sr_enter_plus_exit_time_us = 11.48, 589 .valid = true, 590 }, 591 { 592 .wm_inst = WM_C, 593 .wm_type = WM_TYPE_PSTATE_CHG, 594 .pstate_latency_us = 11.72, 595 .sr_exit_time_us = 10.12, 596 .sr_enter_plus_exit_time_us = 11.48, 597 .valid = true, 598 }, 599 { 600 .wm_inst = WM_D, 601 .wm_type = WM_TYPE_PSTATE_CHG, 602 .pstate_latency_us = 11.72, 603 .sr_exit_time_us = 10.12, 604 .sr_enter_plus_exit_time_us = 11.48, 605 .valid = true, 606 }, 607 } 608 }; 609 610 static struct wm_table lpddr4_wm_table = { 611 .entries = { 612 { 613 .wm_inst = WM_A, 614 .wm_type = WM_TYPE_PSTATE_CHG, 615 .pstate_latency_us = 11.65333, 616 .sr_exit_time_us = 5.32, 617 .sr_enter_plus_exit_time_us = 6.38, 618 .valid = true, 619 }, 620 { 621 .wm_inst = WM_B, 622 .wm_type = WM_TYPE_PSTATE_CHG, 623 .pstate_latency_us = 11.65333, 624 .sr_exit_time_us = 9.82, 625 .sr_enter_plus_exit_time_us = 11.196, 626 .valid = true, 627 }, 628 { 629 .wm_inst = WM_C, 630 .wm_type = WM_TYPE_PSTATE_CHG, 631 .pstate_latency_us = 11.65333, 632 .sr_exit_time_us = 9.89, 633 .sr_enter_plus_exit_time_us = 11.24, 634 .valid = true, 635 }, 636 { 637 .wm_inst = WM_D, 638 .wm_type = WM_TYPE_PSTATE_CHG, 639 .pstate_latency_us = 11.65333, 640 .sr_exit_time_us = 9.748, 641 .sr_enter_plus_exit_time_us = 11.102, 642 .valid = true, 643 }, 644 } 645 }; 646 647 static struct wm_table lpddr4_wm_table_with_disabled_ppt = { 648 .entries = { 649 { 650 .wm_inst = WM_A, 651 .wm_type = WM_TYPE_PSTATE_CHG, 652 .pstate_latency_us = 11.65333, 653 .sr_exit_time_us = 8.32, 654 .sr_enter_plus_exit_time_us = 9.38, 655 .valid = true, 656 }, 657 { 658 .wm_inst = WM_B, 659 .wm_type = WM_TYPE_PSTATE_CHG, 660 .pstate_latency_us = 11.65333, 661 .sr_exit_time_us = 9.82, 662 .sr_enter_plus_exit_time_us = 11.196, 663 .valid = true, 664 }, 665 { 666 .wm_inst = WM_C, 667 .wm_type = WM_TYPE_PSTATE_CHG, 668 .pstate_latency_us = 11.65333, 669 .sr_exit_time_us = 9.89, 670 .sr_enter_plus_exit_time_us = 11.24, 671 .valid = true, 672 }, 673 { 674 .wm_inst = WM_D, 675 .wm_type = WM_TYPE_PSTATE_CHG, 676 .pstate_latency_us = 11.65333, 677 .sr_exit_time_us = 9.748, 678 .sr_enter_plus_exit_time_us = 11.102, 679 .valid = true, 680 }, 681 } 682 }; 683 684 static unsigned int find_dcfclk_for_voltage(struct dpm_clocks *clock_table, unsigned int voltage) 685 { 686 int i; 687 688 for (i = 0; i < PP_SMU_NUM_DCFCLK_DPM_LEVELS; i++) { 689 if (clock_table->DcfClocks[i].Vol == voltage) 690 return clock_table->DcfClocks[i].Freq; 691 } 692 693 ASSERT(0); 694 return 0; 695 } 696 697 static void rn_clk_mgr_helper_populate_bw_params(struct clk_bw_params *bw_params, struct dpm_clocks *clock_table, struct integrated_info *bios_info) 698 { 699 int i, j = 0; 700 701 j = -1; 702 703 ASSERT(PP_SMU_NUM_FCLK_DPM_LEVELS <= MAX_NUM_DPM_LVL); 704 705 /* Find lowest DPM, FCLK is filled in reverse order*/ 706 707 for (i = PP_SMU_NUM_FCLK_DPM_LEVELS - 1; i >= 0; i--) { 708 if (clock_table->FClocks[i].Freq != 0 && clock_table->FClocks[i].Vol != 0) { 709 j = i; 710 break; 711 } 712 } 713 714 if (j == -1) { 715 /* clock table is all 0s, just use our own hardcode */ 716 ASSERT(0); 717 return; 718 } 719 720 bw_params->clk_table.num_entries = j + 1; 721 722 for (i = 0; i < bw_params->clk_table.num_entries; i++, j--) { 723 bw_params->clk_table.entries[i].fclk_mhz = clock_table->FClocks[j].Freq; 724 bw_params->clk_table.entries[i].memclk_mhz = clock_table->MemClocks[j].Freq; 725 bw_params->clk_table.entries[i].voltage = clock_table->FClocks[j].Vol; 726 bw_params->clk_table.entries[i].dcfclk_mhz = find_dcfclk_for_voltage(clock_table, clock_table->FClocks[j].Vol); 727 } 728 729 bw_params->vram_type = bios_info->memory_type; 730 bw_params->num_channels = bios_info->ma_channel_number; 731 732 for (i = 0; i < WM_SET_COUNT; i++) { 733 bw_params->wm_table.entries[i].wm_inst = i; 734 735 if (i >= bw_params->clk_table.num_entries) { 736 bw_params->wm_table.entries[i].valid = false; 737 continue; 738 } 739 740 bw_params->wm_table.entries[i].wm_type = WM_TYPE_PSTATE_CHG; 741 bw_params->wm_table.entries[i].valid = true; 742 } 743 744 if (bw_params->vram_type == LpDdr4MemType) { 745 /* 746 * WM set D will be re-purposed for memory retraining 747 */ 748 bw_params->wm_table.entries[WM_D].pstate_latency_us = LPDDR_MEM_RETRAIN_LATENCY; 749 bw_params->wm_table.entries[WM_D].wm_inst = WM_D; 750 bw_params->wm_table.entries[WM_D].wm_type = WM_TYPE_RETRAINING; 751 bw_params->wm_table.entries[WM_D].valid = true; 752 } 753 754 } 755 756 void rn_clk_mgr_construct( 757 struct dc_context *ctx, 758 struct clk_mgr_internal *clk_mgr, 759 struct pp_smu_funcs *pp_smu, 760 struct dccg *dccg) 761 { 762 struct dc_debug_options *debug = &ctx->dc->debug; 763 struct dpm_clocks clock_table = { 0 }; 764 765 clk_mgr->base.ctx = ctx; 766 clk_mgr->base.funcs = &dcn21_funcs; 767 768 clk_mgr->pp_smu = pp_smu; 769 770 clk_mgr->dccg = dccg; 771 clk_mgr->dfs_bypass_disp_clk = 0; 772 773 clk_mgr->dprefclk_ss_percentage = 0; 774 clk_mgr->dprefclk_ss_divider = 1000; 775 clk_mgr->ss_on_dprefclk = false; 776 clk_mgr->dfs_ref_freq_khz = 48000; 777 778 clk_mgr->smu_ver = rn_vbios_smu_get_smu_version(clk_mgr); 779 780 if (IS_FPGA_MAXIMUS_DC(ctx->dce_environment)) { 781 dcn21_funcs.update_clocks = dcn2_update_clocks_fpga; 782 clk_mgr->base.dentist_vco_freq_khz = 3600000; 783 } else { 784 struct clk_log_info log_info = {0}; 785 786 clk_mgr->smu_ver = rn_vbios_smu_get_smu_version(clk_mgr); 787 clk_mgr->periodic_retraining_disabled = rn_vbios_smu_is_periodic_retraining_disabled(clk_mgr); 788 789 /* SMU Version 55.51.0 and up no longer have an issue 790 * that needs to limit minimum dispclk */ 791 if (clk_mgr->smu_ver >= SMU_VER_55_51_0) 792 debug->min_disp_clk_khz = 0; 793 794 /* TODO: Check we get what we expect during bringup */ 795 clk_mgr->base.dentist_vco_freq_khz = get_vco_frequency_from_reg(clk_mgr); 796 797 /* in case we don't get a value from the register, use default */ 798 if (clk_mgr->base.dentist_vco_freq_khz == 0) 799 clk_mgr->base.dentist_vco_freq_khz = 3600000; 800 801 if (ctx->dc_bios->integrated_info->memory_type == LpDdr4MemType) { 802 if (clk_mgr->periodic_retraining_disabled) { 803 rn_bw_params.wm_table = lpddr4_wm_table_with_disabled_ppt; 804 } else { 805 rn_bw_params.wm_table = lpddr4_wm_table; 806 } 807 } else { 808 rn_bw_params.wm_table = ddr4_wm_table; 809 } 810 /* Saved clocks configured at boot for debug purposes */ 811 rn_dump_clk_registers(&clk_mgr->base.boot_snapshot, &clk_mgr->base, &log_info); 812 } 813 814 clk_mgr->base.dprefclk_khz = 600000; 815 dce_clock_read_ss_info(clk_mgr); 816 817 818 clk_mgr->base.bw_params = &rn_bw_params; 819 820 if (pp_smu && pp_smu->rn_funcs.get_dpm_clock_table) { 821 pp_smu->rn_funcs.get_dpm_clock_table(&pp_smu->rn_funcs.pp_smu, &clock_table); 822 if (ctx->dc_bios && ctx->dc_bios->integrated_info) { 823 rn_clk_mgr_helper_populate_bw_params (clk_mgr->base.bw_params, &clock_table, ctx->dc_bios->integrated_info); 824 } 825 } 826 827 if (!IS_FPGA_MAXIMUS_DC(ctx->dce_environment) && clk_mgr->smu_ver >= 0x00371500) { 828 /* enable powerfeatures when displaycount goes to 0 */ 829 rn_vbios_smu_enable_48mhz_tmdp_refclk_pwrdwn(clk_mgr, !debug->disable_48mhz_pwrdwn); 830 } 831 } 832 833