1 /* 2 * Copyright 2018 Advanced Micro Devices, Inc. 3 * 4 * Permission is hereby granted, free of charge, to any person obtaining a 5 * copy of this software and associated documentation files (the "Software"), 6 * to deal in the Software without restriction, including without limitation 7 * the rights to use, copy, modify, merge, publish, distribute, sublicense, 8 * and/or sell copies of the Software, and to permit persons to whom the 9 * Software is furnished to do so, subject to the following conditions: 10 * 11 * The above copyright notice and this permission notice shall be included in 12 * all copies or substantial portions of the Software. 13 * 14 * THE SOFTWARE IS PROVIDED "AS IS", WITHOUT WARRANTY OF ANY KIND, EXPRESS OR 15 * IMPLIED, INCLUDING BUT NOT LIMITED TO THE WARRANTIES OF MERCHANTABILITY, 16 * FITNESS FOR A PARTICULAR PURPOSE AND NONINFRINGEMENT. IN NO EVENT SHALL 17 * THE COPYRIGHT HOLDER(S) OR AUTHOR(S) BE LIABLE FOR ANY CLAIM, DAMAGES OR 18 * OTHER LIABILITY, WHETHER IN AN ACTION OF CONTRACT, TORT OR OTHERWISE, 19 * ARISING FROM, OUT OF OR IN CONNECTION WITH THE SOFTWARE OR THE USE OR 20 * OTHER DEALINGS IN THE SOFTWARE. 21 * 22 * Authors: AMD 23 * 24 */ 25 26 #include "dccg.h" 27 #include "clk_mgr_internal.h" 28 29 #include "dce100/dce_clk_mgr.h" 30 #include "dcn20_clk_mgr.h" 31 #include "reg_helper.h" 32 #include "core_types.h" 33 #include "dm_helpers.h" 34 35 #include "navi10_ip_offset.h" 36 #include "dcn/dcn_2_0_0_offset.h" 37 #include "dcn/dcn_2_0_0_sh_mask.h" 38 #include "clk/clk_11_0_0_offset.h" 39 #include "clk/clk_11_0_0_sh_mask.h" 40 41 #undef FN 42 #define FN(reg_name, field_name) \ 43 clk_mgr->clk_mgr_shift->field_name, clk_mgr->clk_mgr_mask->field_name 44 45 #define REG(reg) \ 46 (clk_mgr->regs->reg) 47 48 #define BASE_INNER(seg) DCN_BASE__INST0_SEG ## seg 49 50 #define BASE(seg) BASE_INNER(seg) 51 52 #define SR(reg_name)\ 53 .reg_name = BASE(mm ## reg_name ## _BASE_IDX) + \ 54 mm ## reg_name 55 56 #define CLK_BASE_INNER(seg) \ 57 CLK_BASE__INST0_SEG ## seg 58 59 60 static const struct clk_mgr_registers clk_mgr_regs = { 61 CLK_REG_LIST_NV10() 62 }; 63 64 static const struct clk_mgr_shift clk_mgr_shift = { 65 CLK_MASK_SH_LIST_NV10(__SHIFT) 66 }; 67 68 static const struct clk_mgr_mask clk_mgr_mask = { 69 CLK_MASK_SH_LIST_NV10(_MASK) 70 }; 71 72 uint32_t dentist_get_did_from_divider(int divider) 73 { 74 uint32_t divider_id; 75 76 /* we want to floor here to get higher clock than required rather than lower */ 77 if (divider < DENTIST_DIVIDER_RANGE_2_START) { 78 if (divider < DENTIST_DIVIDER_RANGE_1_START) 79 divider_id = DENTIST_BASE_DID_1; 80 else 81 divider_id = DENTIST_BASE_DID_1 82 + (divider - DENTIST_DIVIDER_RANGE_1_START) 83 / DENTIST_DIVIDER_RANGE_1_STEP; 84 } else if (divider < DENTIST_DIVIDER_RANGE_3_START) { 85 divider_id = DENTIST_BASE_DID_2 86 + (divider - DENTIST_DIVIDER_RANGE_2_START) 87 / DENTIST_DIVIDER_RANGE_2_STEP; 88 } else if (divider < DENTIST_DIVIDER_RANGE_4_START) { 89 divider_id = DENTIST_BASE_DID_3 90 + (divider - DENTIST_DIVIDER_RANGE_3_START) 91 / DENTIST_DIVIDER_RANGE_3_STEP; 92 } else { 93 divider_id = DENTIST_BASE_DID_4 94 + (divider - DENTIST_DIVIDER_RANGE_4_START) 95 / DENTIST_DIVIDER_RANGE_4_STEP; 96 if (divider_id > DENTIST_MAX_DID) 97 divider_id = DENTIST_MAX_DID; 98 } 99 100 return divider_id; 101 } 102 103 void dcn20_update_clocks_update_dpp_dto(struct clk_mgr_internal *clk_mgr, 104 struct dc_state *context, bool safe_to_lower) 105 { 106 int i; 107 108 clk_mgr->dccg->ref_dppclk = clk_mgr->base.clks.dppclk_khz; 109 for (i = 0; i < clk_mgr->base.ctx->dc->res_pool->pipe_count; i++) { 110 int dpp_inst, dppclk_khz, prev_dppclk_khz; 111 112 /* Loop index will match dpp->inst if resource exists, 113 * and we want to avoid dependency on dpp object 114 */ 115 dpp_inst = i; 116 dppclk_khz = context->res_ctx.pipe_ctx[i].plane_res.bw.dppclk_khz; 117 118 prev_dppclk_khz = clk_mgr->dccg->pipe_dppclk_khz[i]; 119 120 if (safe_to_lower || prev_dppclk_khz < dppclk_khz) 121 clk_mgr->dccg->funcs->update_dpp_dto( 122 clk_mgr->dccg, dpp_inst, dppclk_khz); 123 } 124 } 125 126 void dcn20_update_clocks_update_dentist(struct clk_mgr_internal *clk_mgr) 127 { 128 int dpp_divider = DENTIST_DIVIDER_RANGE_SCALE_FACTOR 129 * clk_mgr->base.dentist_vco_freq_khz / clk_mgr->base.clks.dppclk_khz; 130 int disp_divider = DENTIST_DIVIDER_RANGE_SCALE_FACTOR 131 * clk_mgr->base.dentist_vco_freq_khz / clk_mgr->base.clks.dispclk_khz; 132 133 uint32_t dppclk_wdivider = dentist_get_did_from_divider(dpp_divider); 134 uint32_t dispclk_wdivider = dentist_get_did_from_divider(disp_divider); 135 136 REG_UPDATE(DENTIST_DISPCLK_CNTL, 137 DENTIST_DISPCLK_WDIVIDER, dispclk_wdivider); 138 // REG_WAIT(DENTIST_DISPCLK_CNTL, DENTIST_DISPCLK_CHG_DONE, 1, 5, 100); 139 REG_UPDATE(DENTIST_DISPCLK_CNTL, 140 DENTIST_DPPCLK_WDIVIDER, dppclk_wdivider); 141 REG_WAIT(DENTIST_DISPCLK_CNTL, DENTIST_DPPCLK_CHG_DONE, 1, 5, 100); 142 } 143 144 145 void dcn2_update_clocks(struct clk_mgr *clk_mgr_base, 146 struct dc_state *context, 147 bool safe_to_lower) 148 { 149 struct clk_mgr_internal *clk_mgr = TO_CLK_MGR_INTERNAL(clk_mgr_base); 150 struct dc_clocks *new_clocks = &context->bw_ctx.bw.dcn.clk; 151 struct dc *dc = clk_mgr_base->ctx->dc; 152 struct pp_smu_funcs_nv *pp_smu = NULL; 153 int display_count; 154 bool update_dppclk = false; 155 bool update_dispclk = false; 156 bool enter_display_off = false; 157 bool dpp_clock_lowered = false; 158 struct dmcu *dmcu = clk_mgr_base->ctx->dc->res_pool->dmcu; 159 bool force_reset = false; 160 bool p_state_change_support; 161 int total_plane_count; 162 163 if (dc->work_arounds.skip_clock_update) 164 return; 165 166 if (clk_mgr_base->clks.dispclk_khz == 0 || 167 dc->debug.force_clock_mode & 0x1) { 168 //this is from resume or boot up, if forced_clock cfg option used, we bypass program dispclk and DPPCLK, but need set them for S3. 169 force_reset = true; 170 171 dcn2_read_clocks_from_hw_dentist(clk_mgr_base); 172 173 //force_clock_mode 0x1: force reset the clock even it is the same clock as long as it is in Passive level. 174 } 175 display_count = clk_mgr_helper_get_active_display_cnt(dc, context); 176 if (dc->res_pool->pp_smu) 177 pp_smu = &dc->res_pool->pp_smu->nv_funcs; 178 179 if (display_count == 0) 180 enter_display_off = true; 181 182 if (enter_display_off == safe_to_lower) { 183 if (pp_smu && pp_smu->set_display_count) 184 pp_smu->set_display_count(&pp_smu->pp_smu, display_count); 185 } 186 187 if (dc->debug.force_min_dcfclk_mhz > 0) 188 new_clocks->dcfclk_khz = (new_clocks->dcfclk_khz > (dc->debug.force_min_dcfclk_mhz * 1000)) ? 189 new_clocks->dcfclk_khz : (dc->debug.force_min_dcfclk_mhz * 1000); 190 191 if (should_set_clock(safe_to_lower, new_clocks->dcfclk_khz, clk_mgr_base->clks.dcfclk_khz)) { 192 clk_mgr_base->clks.dcfclk_khz = new_clocks->dcfclk_khz; 193 if (pp_smu && pp_smu->set_hard_min_dcfclk_by_freq) 194 pp_smu->set_hard_min_dcfclk_by_freq(&pp_smu->pp_smu, clk_mgr_base->clks.dcfclk_khz / 1000); 195 } 196 197 if (should_set_clock(safe_to_lower, 198 new_clocks->dcfclk_deep_sleep_khz, clk_mgr_base->clks.dcfclk_deep_sleep_khz)) { 199 clk_mgr_base->clks.dcfclk_deep_sleep_khz = new_clocks->dcfclk_deep_sleep_khz; 200 if (pp_smu && pp_smu->set_min_deep_sleep_dcfclk) 201 pp_smu->set_min_deep_sleep_dcfclk(&pp_smu->pp_smu, clk_mgr_base->clks.dcfclk_deep_sleep_khz / 1000); 202 } 203 204 if (should_set_clock(safe_to_lower, new_clocks->socclk_khz, clk_mgr_base->clks.socclk_khz)) { 205 clk_mgr_base->clks.socclk_khz = new_clocks->socclk_khz; 206 if (pp_smu && pp_smu->set_hard_min_socclk_by_freq) 207 pp_smu->set_hard_min_socclk_by_freq(&pp_smu->pp_smu, clk_mgr_base->clks.socclk_khz / 1000); 208 } 209 210 total_plane_count = clk_mgr_helper_get_active_plane_cnt(dc, context); 211 p_state_change_support = new_clocks->p_state_change_support || (total_plane_count == 0); 212 if (should_update_pstate_support(safe_to_lower, p_state_change_support, clk_mgr_base->clks.p_state_change_support)) { 213 clk_mgr_base->clks.prev_p_state_change_support = clk_mgr_base->clks.p_state_change_support; 214 clk_mgr_base->clks.p_state_change_support = p_state_change_support; 215 if (pp_smu && pp_smu->set_pstate_handshake_support) 216 pp_smu->set_pstate_handshake_support(&pp_smu->pp_smu, clk_mgr_base->clks.p_state_change_support); 217 } 218 219 if (should_set_clock(safe_to_lower, new_clocks->dramclk_khz, clk_mgr_base->clks.dramclk_khz)) { 220 clk_mgr_base->clks.dramclk_khz = new_clocks->dramclk_khz; 221 if (pp_smu && pp_smu->set_hard_min_uclk_by_freq) 222 pp_smu->set_hard_min_uclk_by_freq(&pp_smu->pp_smu, clk_mgr_base->clks.dramclk_khz / 1000); 223 } 224 225 if (should_set_clock(safe_to_lower, new_clocks->dppclk_khz, clk_mgr->base.clks.dppclk_khz)) { 226 if (clk_mgr->base.clks.dppclk_khz > new_clocks->dppclk_khz) 227 dpp_clock_lowered = true; 228 clk_mgr->base.clks.dppclk_khz = new_clocks->dppclk_khz; 229 230 update_dppclk = true; 231 } 232 233 if (should_set_clock(safe_to_lower, new_clocks->dispclk_khz, clk_mgr_base->clks.dispclk_khz)) { 234 clk_mgr_base->clks.dispclk_khz = new_clocks->dispclk_khz; 235 236 update_dispclk = true; 237 } 238 239 if (update_dppclk || update_dispclk) { 240 new_clocks->disp_dpp_voltage_level_khz = new_clocks->dppclk_khz; 241 242 if (update_dispclk) 243 new_clocks->disp_dpp_voltage_level_khz = new_clocks->dispclk_khz > new_clocks->dppclk_khz ? new_clocks->dispclk_khz : new_clocks->dppclk_khz; 244 245 clk_mgr_base->clks.disp_dpp_voltage_level_khz = new_clocks->disp_dpp_voltage_level_khz; 246 if (pp_smu && pp_smu->set_voltage_by_freq) 247 pp_smu->set_voltage_by_freq(&pp_smu->pp_smu, PP_SMU_NV_DISPCLK, clk_mgr_base->clks.disp_dpp_voltage_level_khz / 1000); 248 } 249 250 if (dc->config.forced_clocks == false || (force_reset && safe_to_lower)) { 251 if (dpp_clock_lowered) { 252 // if clock is being lowered, increase DTO before lowering refclk 253 dcn20_update_clocks_update_dpp_dto(clk_mgr, context, safe_to_lower); 254 dcn20_update_clocks_update_dentist(clk_mgr); 255 } else { 256 // if clock is being raised, increase refclk before lowering DTO 257 if (update_dppclk || update_dispclk) 258 dcn20_update_clocks_update_dentist(clk_mgr); 259 // always update dtos unless clock is lowered and not safe to lower 260 dcn20_update_clocks_update_dpp_dto(clk_mgr, context, safe_to_lower); 261 } 262 } 263 264 if (update_dispclk && 265 dmcu && dmcu->funcs->is_dmcu_initialized(dmcu)) { 266 /*update dmcu for wait_loop count*/ 267 dmcu->funcs->set_psr_wait_loop(dmcu, 268 clk_mgr_base->clks.dispclk_khz / 1000 / 7); 269 } 270 } 271 272 void dcn2_update_clocks_fpga(struct clk_mgr *clk_mgr, 273 struct dc_state *context, 274 bool safe_to_lower) 275 { 276 struct clk_mgr_internal *clk_mgr_int = TO_CLK_MGR_INTERNAL(clk_mgr); 277 278 struct dc_clocks *new_clocks = &context->bw_ctx.bw.dcn.clk; 279 /* Min fclk = 1.2GHz since all the extra scemi logic seems to run off of it */ 280 int fclk_adj = new_clocks->fclk_khz > 1200000 ? new_clocks->fclk_khz : 1200000; 281 282 if (should_set_clock(safe_to_lower, new_clocks->phyclk_khz, clk_mgr->clks.phyclk_khz)) { 283 clk_mgr->clks.phyclk_khz = new_clocks->phyclk_khz; 284 } 285 286 if (should_set_clock(safe_to_lower, new_clocks->dcfclk_khz, clk_mgr->clks.dcfclk_khz)) { 287 clk_mgr->clks.dcfclk_khz = new_clocks->dcfclk_khz; 288 } 289 290 if (should_set_clock(safe_to_lower, 291 new_clocks->dcfclk_deep_sleep_khz, clk_mgr->clks.dcfclk_deep_sleep_khz)) { 292 clk_mgr->clks.dcfclk_deep_sleep_khz = new_clocks->dcfclk_deep_sleep_khz; 293 } 294 295 if (should_set_clock(safe_to_lower, new_clocks->socclk_khz, clk_mgr->clks.socclk_khz)) { 296 clk_mgr->clks.socclk_khz = new_clocks->socclk_khz; 297 } 298 299 if (should_set_clock(safe_to_lower, new_clocks->dramclk_khz, clk_mgr->clks.dramclk_khz)) { 300 clk_mgr->clks.dramclk_khz = new_clocks->dramclk_khz; 301 } 302 303 if (should_set_clock(safe_to_lower, new_clocks->dppclk_khz, clk_mgr->clks.dppclk_khz)) { 304 clk_mgr->clks.dppclk_khz = new_clocks->dppclk_khz; 305 } 306 307 if (should_set_clock(safe_to_lower, fclk_adj, clk_mgr->clks.fclk_khz)) { 308 clk_mgr->clks.fclk_khz = fclk_adj; 309 } 310 311 if (should_set_clock(safe_to_lower, new_clocks->dispclk_khz, clk_mgr->clks.dispclk_khz)) { 312 clk_mgr->clks.dispclk_khz = new_clocks->dispclk_khz; 313 } 314 315 /* Both fclk and ref_dppclk run on the same scemi clock. 316 * So take the higher value since the DPP DTO is typically programmed 317 * such that max dppclk is 1:1 with ref_dppclk. 318 */ 319 if (clk_mgr->clks.fclk_khz > clk_mgr->clks.dppclk_khz) 320 clk_mgr->clks.dppclk_khz = clk_mgr->clks.fclk_khz; 321 if (clk_mgr->clks.dppclk_khz > clk_mgr->clks.fclk_khz) 322 clk_mgr->clks.fclk_khz = clk_mgr->clks.dppclk_khz; 323 324 // Both fclk and ref_dppclk run on the same scemi clock. 325 clk_mgr_int->dccg->ref_dppclk = clk_mgr->clks.fclk_khz; 326 327 dm_set_dcn_clocks(clk_mgr->ctx, &clk_mgr->clks); 328 } 329 330 void dcn2_init_clocks(struct clk_mgr *clk_mgr) 331 { 332 memset(&(clk_mgr->clks), 0, sizeof(struct dc_clocks)); 333 // Assumption is that boot state always supports pstate 334 clk_mgr->clks.p_state_change_support = true; 335 clk_mgr->clks.prev_p_state_change_support = true; 336 } 337 338 void dcn2_enable_pme_wa(struct clk_mgr *clk_mgr_base) 339 { 340 struct clk_mgr_internal *clk_mgr = TO_CLK_MGR_INTERNAL(clk_mgr_base); 341 struct pp_smu_funcs_nv *pp_smu = NULL; 342 343 if (clk_mgr->pp_smu) { 344 pp_smu = &clk_mgr->pp_smu->nv_funcs; 345 346 if (pp_smu->set_pme_wa_enable) 347 pp_smu->set_pme_wa_enable(&pp_smu->pp_smu); 348 } 349 } 350 351 352 void dcn2_read_clocks_from_hw_dentist(struct clk_mgr *clk_mgr_base) 353 { 354 struct clk_mgr_internal *clk_mgr = TO_CLK_MGR_INTERNAL(clk_mgr_base); 355 uint32_t dispclk_wdivider; 356 uint32_t dppclk_wdivider; 357 int disp_divider; 358 int dpp_divider; 359 360 REG_GET(DENTIST_DISPCLK_CNTL, DENTIST_DISPCLK_WDIVIDER, &dispclk_wdivider); 361 REG_GET(DENTIST_DISPCLK_CNTL, DENTIST_DPPCLK_WDIVIDER, &dppclk_wdivider); 362 363 disp_divider = dentist_get_divider_from_did(dispclk_wdivider); 364 dpp_divider = dentist_get_divider_from_did(dispclk_wdivider); 365 366 if (disp_divider && dpp_divider) { 367 /* Calculate the current DFS clock, in kHz.*/ 368 clk_mgr_base->clks.dispclk_khz = (DENTIST_DIVIDER_RANGE_SCALE_FACTOR 369 * clk_mgr->base.dentist_vco_freq_khz) / disp_divider; 370 371 clk_mgr_base->clks.dppclk_khz = (DENTIST_DIVIDER_RANGE_SCALE_FACTOR 372 * clk_mgr->base.dentist_vco_freq_khz) / dpp_divider; 373 } 374 375 } 376 377 void dcn2_get_clock(struct clk_mgr *clk_mgr, 378 struct dc_state *context, 379 enum dc_clock_type clock_type, 380 struct dc_clock_config *clock_cfg) 381 { 382 383 if (clock_type == DC_CLOCK_TYPE_DISPCLK) { 384 clock_cfg->max_clock_khz = context->bw_ctx.bw.dcn.clk.max_supported_dispclk_khz; 385 clock_cfg->min_clock_khz = DCN_MINIMUM_DISPCLK_Khz; 386 clock_cfg->current_clock_khz = clk_mgr->clks.dispclk_khz; 387 clock_cfg->bw_requirequired_clock_khz = context->bw_ctx.bw.dcn.clk.bw_dispclk_khz; 388 } 389 if (clock_type == DC_CLOCK_TYPE_DPPCLK) { 390 clock_cfg->max_clock_khz = context->bw_ctx.bw.dcn.clk.max_supported_dppclk_khz; 391 clock_cfg->min_clock_khz = DCN_MINIMUM_DPPCLK_Khz; 392 clock_cfg->current_clock_khz = clk_mgr->clks.dppclk_khz; 393 clock_cfg->bw_requirequired_clock_khz = context->bw_ctx.bw.dcn.clk.bw_dppclk_khz; 394 } 395 } 396 397 static bool dcn2_are_clock_states_equal(struct dc_clocks *a, 398 struct dc_clocks *b) 399 { 400 if (a->dispclk_khz != b->dispclk_khz) 401 return false; 402 else if (a->dppclk_khz != b->dppclk_khz) 403 return false; 404 else if (a->disp_dpp_voltage_level_khz != b->disp_dpp_voltage_level_khz) 405 return false; 406 else if (a->dcfclk_khz != b->dcfclk_khz) 407 return false; 408 else if (a->socclk_khz != b->socclk_khz) 409 return false; 410 else if (a->dcfclk_deep_sleep_khz != b->dcfclk_deep_sleep_khz) 411 return false; 412 else if (a->dramclk_khz != b->dramclk_khz) 413 return false; 414 else if (a->p_state_change_support != b->p_state_change_support) 415 return false; 416 417 return true; 418 } 419 420 /* Notify clk_mgr of a change in link rate, update phyclk frequency if necessary */ 421 static void dcn2_notify_link_rate_change(struct clk_mgr *clk_mgr_base, struct dc_link *link) 422 { 423 struct clk_mgr_internal *clk_mgr = TO_CLK_MGR_INTERNAL(clk_mgr_base); 424 unsigned int i, max_phyclk_req = 0; 425 struct pp_smu_funcs_nv *pp_smu = NULL; 426 427 if (!clk_mgr->pp_smu || !clk_mgr->pp_smu->nv_funcs.set_voltage_by_freq) 428 return; 429 430 pp_smu = &clk_mgr->pp_smu->nv_funcs; 431 432 clk_mgr->cur_phyclk_req_table[link->link_index] = link->cur_link_settings.link_rate * LINK_RATE_REF_FREQ_IN_KHZ; 433 434 for (i = 0; i < MAX_PIPES * 2; i++) { 435 if (clk_mgr->cur_phyclk_req_table[i] > max_phyclk_req) 436 max_phyclk_req = clk_mgr->cur_phyclk_req_table[i]; 437 } 438 439 if (max_phyclk_req != clk_mgr_base->clks.phyclk_khz) { 440 clk_mgr_base->clks.phyclk_khz = max_phyclk_req; 441 pp_smu->set_voltage_by_freq(&pp_smu->pp_smu, PP_SMU_NV_PHYCLK, clk_mgr_base->clks.phyclk_khz / 1000); 442 } 443 } 444 445 static struct clk_mgr_funcs dcn2_funcs = { 446 .get_dp_ref_clk_frequency = dce12_get_dp_ref_freq_khz, 447 .update_clocks = dcn2_update_clocks, 448 .init_clocks = dcn2_init_clocks, 449 .enable_pme_wa = dcn2_enable_pme_wa, 450 .get_clock = dcn2_get_clock, 451 .are_clock_states_equal = dcn2_are_clock_states_equal, 452 .notify_link_rate_change = dcn2_notify_link_rate_change, 453 }; 454 455 456 void dcn20_clk_mgr_construct( 457 struct dc_context *ctx, 458 struct clk_mgr_internal *clk_mgr, 459 struct pp_smu_funcs *pp_smu, 460 struct dccg *dccg) 461 { 462 clk_mgr->base.ctx = ctx; 463 clk_mgr->pp_smu = pp_smu; 464 clk_mgr->base.funcs = &dcn2_funcs; 465 clk_mgr->regs = &clk_mgr_regs; 466 clk_mgr->clk_mgr_shift = &clk_mgr_shift; 467 clk_mgr->clk_mgr_mask = &clk_mgr_mask; 468 469 clk_mgr->dccg = dccg; 470 clk_mgr->dfs_bypass_disp_clk = 0; 471 472 clk_mgr->dprefclk_ss_percentage = 0; 473 clk_mgr->dprefclk_ss_divider = 1000; 474 clk_mgr->ss_on_dprefclk = false; 475 476 clk_mgr->base.dprefclk_khz = 700000; // 700 MHz planned if VCO is 3.85 GHz, will be retrieved 477 478 if (IS_FPGA_MAXIMUS_DC(ctx->dce_environment)) { 479 dcn2_funcs.update_clocks = dcn2_update_clocks_fpga; 480 clk_mgr->base.dentist_vco_freq_khz = 3850000; 481 482 } else { 483 /* DFS Slice 2 should be used for DPREFCLK */ 484 int dprefclk_did = REG_READ(CLK3_CLK2_DFS_CNTL); 485 /* Convert DPREFCLK DFS Slice DID to actual divider*/ 486 int target_div = dentist_get_divider_from_did(dprefclk_did); 487 488 /* get FbMult value */ 489 uint32_t pll_req_reg = REG_READ(CLK3_CLK_PLL_REQ); 490 struct fixed31_32 pll_req; 491 492 /* set up a fixed-point number 493 * this works because the int part is on the right edge of the register 494 * and the frac part is on the left edge 495 */ 496 497 pll_req = dc_fixpt_from_int(pll_req_reg & clk_mgr->clk_mgr_mask->FbMult_int); 498 pll_req.value |= pll_req_reg & clk_mgr->clk_mgr_mask->FbMult_frac; 499 500 /* multiply by REFCLK period */ 501 pll_req = dc_fixpt_mul_int(pll_req, 100000); 502 503 /* integer part is now VCO frequency in kHz */ 504 clk_mgr->base.dentist_vco_freq_khz = dc_fixpt_floor(pll_req); 505 506 /* in case we don't get a value from the register, use default */ 507 if (clk_mgr->base.dentist_vco_freq_khz == 0) 508 clk_mgr->base.dentist_vco_freq_khz = 3850000; 509 510 /* Calculate the DPREFCLK in kHz.*/ 511 clk_mgr->base.dprefclk_khz = (DENTIST_DIVIDER_RANGE_SCALE_FACTOR 512 * clk_mgr->base.dentist_vco_freq_khz) / target_div; 513 } 514 //Integrated_info table does not exist on dGPU projects so should not be referenced 515 //anywhere in code for dGPUs. 516 //Also there is no plan for now that DFS BYPASS will be used on NV10/12/14. 517 clk_mgr->dfs_bypass_enabled = false; 518 519 dce_clock_read_ss_info(clk_mgr); 520 } 521 522