1 /* 2 * Copyright 2018 Advanced Micro Devices, Inc. 3 * 4 * Permission is hereby granted, free of charge, to any person obtaining a 5 * copy of this software and associated documentation files (the "Software"), 6 * to deal in the Software without restriction, including without limitation 7 * the rights to use, copy, modify, merge, publish, distribute, sublicense, 8 * and/or sell copies of the Software, and to permit persons to whom the 9 * Software is furnished to do so, subject to the following conditions: 10 * 11 * The above copyright notice and this permission notice shall be included in 12 * all copies or substantial portions of the Software. 13 * 14 * THE SOFTWARE IS PROVIDED "AS IS", WITHOUT WARRANTY OF ANY KIND, EXPRESS OR 15 * IMPLIED, INCLUDING BUT NOT LIMITED TO THE WARRANTIES OF MERCHANTABILITY, 16 * FITNESS FOR A PARTICULAR PURPOSE AND NONINFRINGEMENT. IN NO EVENT SHALL 17 * THE COPYRIGHT HOLDER(S) OR AUTHOR(S) BE LIABLE FOR ANY CLAIM, DAMAGES OR 18 * OTHER LIABILITY, WHETHER IN AN ACTION OF CONTRACT, TORT OR OTHERWISE, 19 * ARISING FROM, OUT OF OR IN CONNECTION WITH THE SOFTWARE OR THE USE OR 20 * OTHER DEALINGS IN THE SOFTWARE. 21 * 22 * Authors: AMD 23 * 24 */ 25 26 #include "dccg.h" 27 #include "clk_mgr_internal.h" 28 29 #include "dce100/dce_clk_mgr.h" 30 #include "dcn20_clk_mgr.h" 31 #include "reg_helper.h" 32 #include "core_types.h" 33 #include "dm_helpers.h" 34 35 #include "navi10_ip_offset.h" 36 #include "dcn/dcn_2_0_0_offset.h" 37 #include "dcn/dcn_2_0_0_sh_mask.h" 38 #include "clk/clk_11_0_0_offset.h" 39 #include "clk/clk_11_0_0_sh_mask.h" 40 41 #undef FN 42 #define FN(reg_name, field_name) \ 43 clk_mgr->clk_mgr_shift->field_name, clk_mgr->clk_mgr_mask->field_name 44 45 #define REG(reg) \ 46 (clk_mgr->regs->reg) 47 48 #define BASE_INNER(seg) DCN_BASE__INST0_SEG ## seg 49 50 #define BASE(seg) BASE_INNER(seg) 51 52 #define SR(reg_name)\ 53 .reg_name = BASE(mm ## reg_name ## _BASE_IDX) + \ 54 mm ## reg_name 55 56 #define CLK_BASE_INNER(seg) \ 57 CLK_BASE__INST0_SEG ## seg 58 59 60 static const struct clk_mgr_registers clk_mgr_regs = { 61 CLK_REG_LIST_NV10() 62 }; 63 64 static const struct clk_mgr_shift clk_mgr_shift = { 65 CLK_MASK_SH_LIST_NV10(__SHIFT) 66 }; 67 68 static const struct clk_mgr_mask clk_mgr_mask = { 69 CLK_MASK_SH_LIST_NV10(_MASK) 70 }; 71 72 uint32_t dentist_get_did_from_divider(int divider) 73 { 74 uint32_t divider_id; 75 76 /* we want to floor here to get higher clock than required rather than lower */ 77 if (divider < DENTIST_DIVIDER_RANGE_2_START) { 78 if (divider < DENTIST_DIVIDER_RANGE_1_START) 79 divider_id = DENTIST_BASE_DID_1; 80 else 81 divider_id = DENTIST_BASE_DID_1 82 + (divider - DENTIST_DIVIDER_RANGE_1_START) 83 / DENTIST_DIVIDER_RANGE_1_STEP; 84 } else if (divider < DENTIST_DIVIDER_RANGE_3_START) { 85 divider_id = DENTIST_BASE_DID_2 86 + (divider - DENTIST_DIVIDER_RANGE_2_START) 87 / DENTIST_DIVIDER_RANGE_2_STEP; 88 } else if (divider < DENTIST_DIVIDER_RANGE_4_START) { 89 divider_id = DENTIST_BASE_DID_3 90 + (divider - DENTIST_DIVIDER_RANGE_3_START) 91 / DENTIST_DIVIDER_RANGE_3_STEP; 92 } else { 93 divider_id = DENTIST_BASE_DID_4 94 + (divider - DENTIST_DIVIDER_RANGE_4_START) 95 / DENTIST_DIVIDER_RANGE_4_STEP; 96 if (divider_id > DENTIST_MAX_DID) 97 divider_id = DENTIST_MAX_DID; 98 } 99 100 return divider_id; 101 } 102 103 void dcn20_update_clocks_update_dpp_dto(struct clk_mgr_internal *clk_mgr, 104 struct dc_state *context, bool safe_to_lower) 105 { 106 int i; 107 108 clk_mgr->dccg->ref_dppclk = clk_mgr->base.clks.dppclk_khz; 109 for (i = 0; i < clk_mgr->base.ctx->dc->res_pool->pipe_count; i++) { 110 int dpp_inst, dppclk_khz, prev_dppclk_khz; 111 112 /* Loop index will match dpp->inst if resource exists, 113 * and we want to avoid dependency on dpp object 114 */ 115 dpp_inst = i; 116 dppclk_khz = context->res_ctx.pipe_ctx[i].plane_res.bw.dppclk_khz; 117 118 prev_dppclk_khz = clk_mgr->base.ctx->dc->current_state->res_ctx.pipe_ctx[i].plane_res.bw.dppclk_khz; 119 120 if (safe_to_lower || prev_dppclk_khz < dppclk_khz) { 121 clk_mgr->dccg->funcs->update_dpp_dto( 122 clk_mgr->dccg, dpp_inst, dppclk_khz); 123 } 124 } 125 } 126 127 void dcn20_update_clocks_update_dentist(struct clk_mgr_internal *clk_mgr) 128 { 129 int dpp_divider = DENTIST_DIVIDER_RANGE_SCALE_FACTOR 130 * clk_mgr->base.dentist_vco_freq_khz / clk_mgr->base.clks.dppclk_khz; 131 int disp_divider = DENTIST_DIVIDER_RANGE_SCALE_FACTOR 132 * clk_mgr->base.dentist_vco_freq_khz / clk_mgr->base.clks.dispclk_khz; 133 134 uint32_t dppclk_wdivider = dentist_get_did_from_divider(dpp_divider); 135 uint32_t dispclk_wdivider = dentist_get_did_from_divider(disp_divider); 136 137 REG_UPDATE(DENTIST_DISPCLK_CNTL, 138 DENTIST_DISPCLK_WDIVIDER, dispclk_wdivider); 139 // REG_WAIT(DENTIST_DISPCLK_CNTL, DENTIST_DISPCLK_CHG_DONE, 1, 5, 100); 140 REG_UPDATE(DENTIST_DISPCLK_CNTL, 141 DENTIST_DPPCLK_WDIVIDER, dppclk_wdivider); 142 REG_WAIT(DENTIST_DISPCLK_CNTL, DENTIST_DPPCLK_CHG_DONE, 1, 5, 100); 143 } 144 145 146 void dcn2_update_clocks(struct clk_mgr *clk_mgr_base, 147 struct dc_state *context, 148 bool safe_to_lower) 149 { 150 struct clk_mgr_internal *clk_mgr = TO_CLK_MGR_INTERNAL(clk_mgr_base); 151 struct dc_clocks *new_clocks = &context->bw_ctx.bw.dcn.clk; 152 struct dc *dc = clk_mgr_base->ctx->dc; 153 struct pp_smu_funcs_nv *pp_smu = NULL; 154 int display_count; 155 bool update_dppclk = false; 156 bool update_dispclk = false; 157 bool enter_display_off = false; 158 bool dpp_clock_lowered = false; 159 struct dmcu *dmcu = clk_mgr_base->ctx->dc->res_pool->dmcu; 160 bool force_reset = false; 161 bool p_state_change_support; 162 int total_plane_count; 163 164 if (dc->work_arounds.skip_clock_update) 165 return; 166 167 if (clk_mgr_base->clks.dispclk_khz == 0 || 168 dc->debug.force_clock_mode & 0x1) { 169 //this is from resume or boot up, if forced_clock cfg option used, we bypass program dispclk and DPPCLK, but need set them for S3. 170 force_reset = true; 171 172 dcn2_read_clocks_from_hw_dentist(clk_mgr_base); 173 174 //force_clock_mode 0x1: force reset the clock even it is the same clock as long as it is in Passive level. 175 } 176 display_count = clk_mgr_helper_get_active_display_cnt(dc, context); 177 if (dc->res_pool->pp_smu) 178 pp_smu = &dc->res_pool->pp_smu->nv_funcs; 179 180 if (display_count == 0) 181 enter_display_off = true; 182 183 if (enter_display_off == safe_to_lower) { 184 if (pp_smu && pp_smu->set_display_count) 185 pp_smu->set_display_count(&pp_smu->pp_smu, display_count); 186 } 187 188 if (should_set_clock(safe_to_lower, new_clocks->phyclk_khz, clk_mgr_base->clks.phyclk_khz)) { 189 clk_mgr_base->clks.phyclk_khz = new_clocks->phyclk_khz; 190 if (pp_smu && pp_smu->set_voltage_by_freq) 191 pp_smu->set_voltage_by_freq(&pp_smu->pp_smu, PP_SMU_NV_PHYCLK, clk_mgr_base->clks.phyclk_khz / 1000); 192 } 193 194 195 if (dc->debug.force_min_dcfclk_mhz > 0) 196 new_clocks->dcfclk_khz = (new_clocks->dcfclk_khz > (dc->debug.force_min_dcfclk_mhz * 1000)) ? 197 new_clocks->dcfclk_khz : (dc->debug.force_min_dcfclk_mhz * 1000); 198 199 if (should_set_clock(safe_to_lower, new_clocks->dcfclk_khz, clk_mgr_base->clks.dcfclk_khz)) { 200 clk_mgr_base->clks.dcfclk_khz = new_clocks->dcfclk_khz; 201 if (pp_smu && pp_smu->set_hard_min_dcfclk_by_freq) 202 pp_smu->set_hard_min_dcfclk_by_freq(&pp_smu->pp_smu, clk_mgr_base->clks.dcfclk_khz / 1000); 203 } 204 205 if (should_set_clock(safe_to_lower, 206 new_clocks->dcfclk_deep_sleep_khz, clk_mgr_base->clks.dcfclk_deep_sleep_khz)) { 207 clk_mgr_base->clks.dcfclk_deep_sleep_khz = new_clocks->dcfclk_deep_sleep_khz; 208 if (pp_smu && pp_smu->set_min_deep_sleep_dcfclk) 209 pp_smu->set_min_deep_sleep_dcfclk(&pp_smu->pp_smu, clk_mgr_base->clks.dcfclk_deep_sleep_khz / 1000); 210 } 211 212 if (should_set_clock(safe_to_lower, new_clocks->socclk_khz, clk_mgr_base->clks.socclk_khz)) { 213 clk_mgr_base->clks.socclk_khz = new_clocks->socclk_khz; 214 if (pp_smu && pp_smu->set_hard_min_socclk_by_freq) 215 pp_smu->set_hard_min_socclk_by_freq(&pp_smu->pp_smu, clk_mgr_base->clks.socclk_khz / 1000); 216 } 217 218 total_plane_count = clk_mgr_helper_get_active_plane_cnt(dc, context); 219 p_state_change_support = new_clocks->p_state_change_support || (total_plane_count == 0); 220 if (should_update_pstate_support(safe_to_lower, p_state_change_support, clk_mgr_base->clks.p_state_change_support)) { 221 clk_mgr_base->clks.prev_p_state_change_support = clk_mgr_base->clks.p_state_change_support; 222 clk_mgr_base->clks.p_state_change_support = p_state_change_support; 223 if (pp_smu && pp_smu->set_pstate_handshake_support) 224 pp_smu->set_pstate_handshake_support(&pp_smu->pp_smu, clk_mgr_base->clks.p_state_change_support); 225 } 226 227 if (should_set_clock(safe_to_lower, new_clocks->dramclk_khz, clk_mgr_base->clks.dramclk_khz)) { 228 clk_mgr_base->clks.dramclk_khz = new_clocks->dramclk_khz; 229 if (pp_smu && pp_smu->set_hard_min_uclk_by_freq) 230 pp_smu->set_hard_min_uclk_by_freq(&pp_smu->pp_smu, clk_mgr_base->clks.dramclk_khz / 1000); 231 } 232 233 if (should_set_clock(safe_to_lower, new_clocks->dppclk_khz, clk_mgr->base.clks.dppclk_khz)) { 234 if (clk_mgr->base.clks.dppclk_khz > new_clocks->dppclk_khz) 235 dpp_clock_lowered = true; 236 clk_mgr->base.clks.dppclk_khz = new_clocks->dppclk_khz; 237 238 if (pp_smu && pp_smu->set_voltage_by_freq) 239 pp_smu->set_voltage_by_freq(&pp_smu->pp_smu, PP_SMU_NV_PIXELCLK, clk_mgr_base->clks.dppclk_khz / 1000); 240 241 update_dppclk = true; 242 } 243 244 if (should_set_clock(safe_to_lower, new_clocks->dispclk_khz, clk_mgr_base->clks.dispclk_khz)) { 245 clk_mgr_base->clks.dispclk_khz = new_clocks->dispclk_khz; 246 if (pp_smu && pp_smu->set_voltage_by_freq) 247 pp_smu->set_voltage_by_freq(&pp_smu->pp_smu, PP_SMU_NV_DISPCLK, clk_mgr_base->clks.dispclk_khz / 1000); 248 249 update_dispclk = true; 250 } 251 252 if (dc->config.forced_clocks == false || (force_reset && safe_to_lower)) { 253 if (dpp_clock_lowered) { 254 // if clock is being lowered, increase DTO before lowering refclk 255 dcn20_update_clocks_update_dpp_dto(clk_mgr, context, safe_to_lower); 256 dcn20_update_clocks_update_dentist(clk_mgr); 257 } else { 258 // if clock is being raised, increase refclk before lowering DTO 259 if (update_dppclk || update_dispclk) 260 dcn20_update_clocks_update_dentist(clk_mgr); 261 // always update dtos unless clock is lowered and not safe to lower 262 if (new_clocks->dppclk_khz >= dc->current_state->bw_ctx.bw.dcn.clk.dppclk_khz) 263 dcn20_update_clocks_update_dpp_dto(clk_mgr, context, safe_to_lower); 264 } 265 } 266 267 if (update_dispclk && 268 dmcu && dmcu->funcs->is_dmcu_initialized(dmcu)) { 269 /*update dmcu for wait_loop count*/ 270 dmcu->funcs->set_psr_wait_loop(dmcu, 271 clk_mgr_base->clks.dispclk_khz / 1000 / 7); 272 } 273 } 274 275 void dcn2_update_clocks_fpga(struct clk_mgr *clk_mgr, 276 struct dc_state *context, 277 bool safe_to_lower) 278 { 279 struct clk_mgr_internal *clk_mgr_int = TO_CLK_MGR_INTERNAL(clk_mgr); 280 281 struct dc_clocks *new_clocks = &context->bw_ctx.bw.dcn.clk; 282 /* Min fclk = 1.2GHz since all the extra scemi logic seems to run off of it */ 283 int fclk_adj = new_clocks->fclk_khz > 1200000 ? new_clocks->fclk_khz : 1200000; 284 285 if (should_set_clock(safe_to_lower, new_clocks->phyclk_khz, clk_mgr->clks.phyclk_khz)) { 286 clk_mgr->clks.phyclk_khz = new_clocks->phyclk_khz; 287 } 288 289 if (should_set_clock(safe_to_lower, new_clocks->dcfclk_khz, clk_mgr->clks.dcfclk_khz)) { 290 clk_mgr->clks.dcfclk_khz = new_clocks->dcfclk_khz; 291 } 292 293 if (should_set_clock(safe_to_lower, 294 new_clocks->dcfclk_deep_sleep_khz, clk_mgr->clks.dcfclk_deep_sleep_khz)) { 295 clk_mgr->clks.dcfclk_deep_sleep_khz = new_clocks->dcfclk_deep_sleep_khz; 296 } 297 298 if (should_set_clock(safe_to_lower, new_clocks->socclk_khz, clk_mgr->clks.socclk_khz)) { 299 clk_mgr->clks.socclk_khz = new_clocks->socclk_khz; 300 } 301 302 if (should_set_clock(safe_to_lower, new_clocks->dramclk_khz, clk_mgr->clks.dramclk_khz)) { 303 clk_mgr->clks.dramclk_khz = new_clocks->dramclk_khz; 304 } 305 306 if (should_set_clock(safe_to_lower, new_clocks->dppclk_khz, clk_mgr->clks.dppclk_khz)) { 307 clk_mgr->clks.dppclk_khz = new_clocks->dppclk_khz; 308 } 309 310 if (should_set_clock(safe_to_lower, fclk_adj, clk_mgr->clks.fclk_khz)) { 311 clk_mgr->clks.fclk_khz = fclk_adj; 312 } 313 314 if (should_set_clock(safe_to_lower, new_clocks->dispclk_khz, clk_mgr->clks.dispclk_khz)) { 315 clk_mgr->clks.dispclk_khz = new_clocks->dispclk_khz; 316 } 317 318 /* Both fclk and ref_dppclk run on the same scemi clock. 319 * So take the higher value since the DPP DTO is typically programmed 320 * such that max dppclk is 1:1 with ref_dppclk. 321 */ 322 if (clk_mgr->clks.fclk_khz > clk_mgr->clks.dppclk_khz) 323 clk_mgr->clks.dppclk_khz = clk_mgr->clks.fclk_khz; 324 if (clk_mgr->clks.dppclk_khz > clk_mgr->clks.fclk_khz) 325 clk_mgr->clks.fclk_khz = clk_mgr->clks.dppclk_khz; 326 327 // Both fclk and ref_dppclk run on the same scemi clock. 328 clk_mgr_int->dccg->ref_dppclk = clk_mgr->clks.fclk_khz; 329 330 dm_set_dcn_clocks(clk_mgr->ctx, &clk_mgr->clks); 331 } 332 333 void dcn2_init_clocks(struct clk_mgr *clk_mgr) 334 { 335 memset(&(clk_mgr->clks), 0, sizeof(struct dc_clocks)); 336 // Assumption is that boot state always supports pstate 337 clk_mgr->clks.p_state_change_support = true; 338 clk_mgr->clks.prev_p_state_change_support = true; 339 } 340 341 void dcn2_enable_pme_wa(struct clk_mgr *clk_mgr_base) 342 { 343 struct clk_mgr_internal *clk_mgr = TO_CLK_MGR_INTERNAL(clk_mgr_base); 344 struct pp_smu_funcs_nv *pp_smu = NULL; 345 346 if (clk_mgr->pp_smu) { 347 pp_smu = &clk_mgr->pp_smu->nv_funcs; 348 349 if (pp_smu->set_pme_wa_enable) 350 pp_smu->set_pme_wa_enable(&pp_smu->pp_smu); 351 } 352 } 353 354 355 void dcn2_read_clocks_from_hw_dentist(struct clk_mgr *clk_mgr_base) 356 { 357 struct clk_mgr_internal *clk_mgr = TO_CLK_MGR_INTERNAL(clk_mgr_base); 358 uint32_t dispclk_wdivider; 359 uint32_t dppclk_wdivider; 360 int disp_divider; 361 int dpp_divider; 362 363 REG_GET(DENTIST_DISPCLK_CNTL, DENTIST_DISPCLK_WDIVIDER, &dispclk_wdivider); 364 REG_GET(DENTIST_DISPCLK_CNTL, DENTIST_DPPCLK_WDIVIDER, &dppclk_wdivider); 365 366 disp_divider = dentist_get_divider_from_did(dispclk_wdivider); 367 dpp_divider = dentist_get_divider_from_did(dispclk_wdivider); 368 369 if (disp_divider && dpp_divider) { 370 /* Calculate the current DFS clock, in kHz.*/ 371 clk_mgr_base->clks.dispclk_khz = (DENTIST_DIVIDER_RANGE_SCALE_FACTOR 372 * clk_mgr->base.dentist_vco_freq_khz) / disp_divider; 373 374 clk_mgr_base->clks.dppclk_khz = (DENTIST_DIVIDER_RANGE_SCALE_FACTOR 375 * clk_mgr->base.dentist_vco_freq_khz) / dpp_divider; 376 } 377 378 } 379 380 void dcn2_get_clock(struct clk_mgr *clk_mgr, 381 struct dc_state *context, 382 enum dc_clock_type clock_type, 383 struct dc_clock_config *clock_cfg) 384 { 385 386 if (clock_type == DC_CLOCK_TYPE_DISPCLK) { 387 clock_cfg->max_clock_khz = context->bw_ctx.bw.dcn.clk.max_supported_dispclk_khz; 388 clock_cfg->min_clock_khz = DCN_MINIMUM_DISPCLK_Khz; 389 clock_cfg->current_clock_khz = clk_mgr->clks.dispclk_khz; 390 clock_cfg->bw_requirequired_clock_khz = context->bw_ctx.bw.dcn.clk.bw_dispclk_khz; 391 } 392 if (clock_type == DC_CLOCK_TYPE_DPPCLK) { 393 clock_cfg->max_clock_khz = context->bw_ctx.bw.dcn.clk.max_supported_dppclk_khz; 394 clock_cfg->min_clock_khz = DCN_MINIMUM_DPPCLK_Khz; 395 clock_cfg->current_clock_khz = clk_mgr->clks.dppclk_khz; 396 clock_cfg->bw_requirequired_clock_khz = context->bw_ctx.bw.dcn.clk.bw_dppclk_khz; 397 } 398 } 399 400 static bool dcn2_are_clock_states_equal(struct dc_clocks *a, 401 struct dc_clocks *b) 402 { 403 if (a->dispclk_khz != b->dispclk_khz) 404 return false; 405 else if (a->dppclk_khz != b->dppclk_khz) 406 return false; 407 else if (a->dcfclk_khz != b->dcfclk_khz) 408 return false; 409 else if (a->socclk_khz != b->socclk_khz) 410 return false; 411 else if (a->dcfclk_deep_sleep_khz != b->dcfclk_deep_sleep_khz) 412 return false; 413 else if (a->phyclk_khz != b->phyclk_khz) 414 return false; 415 else if (a->dramclk_khz != b->dramclk_khz) 416 return false; 417 else if (a->p_state_change_support != b->p_state_change_support) 418 return false; 419 420 return true; 421 } 422 423 static struct clk_mgr_funcs dcn2_funcs = { 424 .get_dp_ref_clk_frequency = dce12_get_dp_ref_freq_khz, 425 .update_clocks = dcn2_update_clocks, 426 .init_clocks = dcn2_init_clocks, 427 .enable_pme_wa = dcn2_enable_pme_wa, 428 .get_clock = dcn2_get_clock, 429 .are_clock_states_equal = dcn2_are_clock_states_equal, 430 }; 431 432 433 void dcn20_clk_mgr_construct( 434 struct dc_context *ctx, 435 struct clk_mgr_internal *clk_mgr, 436 struct pp_smu_funcs *pp_smu, 437 struct dccg *dccg) 438 { 439 clk_mgr->base.ctx = ctx; 440 clk_mgr->pp_smu = pp_smu; 441 clk_mgr->base.funcs = &dcn2_funcs; 442 clk_mgr->regs = &clk_mgr_regs; 443 clk_mgr->clk_mgr_shift = &clk_mgr_shift; 444 clk_mgr->clk_mgr_mask = &clk_mgr_mask; 445 446 clk_mgr->dccg = dccg; 447 clk_mgr->dfs_bypass_disp_clk = 0; 448 449 clk_mgr->dprefclk_ss_percentage = 0; 450 clk_mgr->dprefclk_ss_divider = 1000; 451 clk_mgr->ss_on_dprefclk = false; 452 453 clk_mgr->base.dprefclk_khz = 700000; // 700 MHz planned if VCO is 3.85 GHz, will be retrieved 454 455 if (IS_FPGA_MAXIMUS_DC(ctx->dce_environment)) { 456 dcn2_funcs.update_clocks = dcn2_update_clocks_fpga; 457 clk_mgr->base.dentist_vco_freq_khz = 3850000; 458 459 } else { 460 /* DFS Slice 2 should be used for DPREFCLK */ 461 int dprefclk_did = REG_READ(CLK3_CLK2_DFS_CNTL); 462 /* Convert DPREFCLK DFS Slice DID to actual divider*/ 463 int target_div = dentist_get_divider_from_did(dprefclk_did); 464 465 /* get FbMult value */ 466 uint32_t pll_req_reg = REG_READ(CLK3_CLK_PLL_REQ); 467 struct fixed31_32 pll_req; 468 469 /* set up a fixed-point number 470 * this works because the int part is on the right edge of the register 471 * and the frac part is on the left edge 472 */ 473 474 pll_req = dc_fixpt_from_int(pll_req_reg & clk_mgr->clk_mgr_mask->FbMult_int); 475 pll_req.value |= pll_req_reg & clk_mgr->clk_mgr_mask->FbMult_frac; 476 477 /* multiply by REFCLK period */ 478 pll_req = dc_fixpt_mul_int(pll_req, 100000); 479 480 /* integer part is now VCO frequency in kHz */ 481 clk_mgr->base.dentist_vco_freq_khz = dc_fixpt_floor(pll_req); 482 483 /* in case we don't get a value from the register, use default */ 484 if (clk_mgr->base.dentist_vco_freq_khz == 0) 485 clk_mgr->base.dentist_vco_freq_khz = 3850000; 486 487 /* Calculate the DPREFCLK in kHz.*/ 488 clk_mgr->base.dprefclk_khz = (DENTIST_DIVIDER_RANGE_SCALE_FACTOR 489 * clk_mgr->base.dentist_vco_freq_khz) / target_div; 490 } 491 //Integrated_info table does not exist on dGPU projects so should not be referenced 492 //anywhere in code for dGPUs. 493 //Also there is no plan for now that DFS BYPASS will be used on NV10/12/14. 494 clk_mgr->dfs_bypass_enabled = false; 495 496 dce_clock_read_ss_info(clk_mgr); 497 } 498 499