1 /* 2 * Copyright 2012-16 Advanced Micro Devices, Inc. 3 * 4 * Permission is hereby granted, free of charge, to any person obtaining a 5 * copy of this software and associated documentation files (the "Software"), 6 * to deal in the Software without restriction, including without limitation 7 * the rights to use, copy, modify, merge, publish, distribute, sublicense, 8 * and/or sell copies of the Software, and to permit persons to whom the 9 * Software is furnished to do so, subject to the following conditions: 10 * 11 * The above copyright notice and this permission notice shall be included in 12 * all copies or substantial portions of the Software. 13 * 14 * THE SOFTWARE IS PROVIDED "AS IS", WITHOUT WARRANTY OF ANY KIND, EXPRESS OR 15 * IMPLIED, INCLUDING BUT NOT LIMITED TO THE WARRANTIES OF MERCHANTABILITY, 16 * FITNESS FOR A PARTICULAR PURPOSE AND NONINFRINGEMENT. IN NO EVENT SHALL 17 * THE COPYRIGHT HOLDER(S) OR AUTHOR(S) BE LIABLE FOR ANY CLAIM, DAMAGES OR 18 * OTHER LIABILITY, WHETHER IN AN ACTION OF CONTRACT, TORT OR OTHERWISE, 19 * ARISING FROM, OUT OF OR IN CONNECTION WITH THE SOFTWARE OR THE USE OR 20 * OTHER DEALINGS IN THE SOFTWARE. 21 * 22 * Authors: AMD 23 * 24 */ 25 26 #include "reg_helper.h" 27 #include "clk_mgr_internal.h" 28 #include "rv1_clk_mgr_clk.h" 29 30 #include "ip/Discovery/hwid.h" 31 #include "ip/Discovery/v1/ip_offset_1.h" 32 #include "ip/CLK/clk_10_0_default.h" 33 #include "ip/CLK/clk_10_0_offset.h" 34 #include "ip/CLK/clk_10_0_reg.h" 35 #include "ip/CLK/clk_10_0_sh_mask.h" 36 37 #include "dce100/dce_clk_mgr.h" 38 39 #define CLK_BASE_INNER(inst) \ 40 CLK_BASE__INST ## inst ## _SEG0 41 42 43 #define CLK_REG(reg_name, block, inst)\ 44 CLK_BASE(mm ## block ## _ ## inst ## _ ## reg_name ## _BASE_IDX) + \ 45 mm ## block ## _ ## inst ## _ ## reg_name 46 47 #define REG(reg_name) \ 48 CLK_REG(reg_name, CLK0, 0) 49 50 51 /* Only used by testing framework*/ 52 void rv1_dump_clk_registers(struct clk_state_registers *regs, struct clk_bypass *bypass, struct clk_mgr *clk_mgr_base) 53 { 54 struct clk_mgr_internal *clk_mgr = TO_CLK_MGR_INTERNAL(clk_mgr_base); 55 56 regs->CLK0_CLK8_CURRENT_CNT = REG_READ(CLK0_CLK8_CURRENT_CNT) / 10; //dcf clk 57 58 bypass->dcfclk_bypass = REG_READ(CLK0_CLK8_BYPASS_CNTL) & 0x0007; 59 if (bypass->dcfclk_bypass < 0 || bypass->dcfclk_bypass > 4) 60 bypass->dcfclk_bypass = 0; 61 62 63 regs->CLK0_CLK8_DS_CNTL = REG_READ(CLK0_CLK8_DS_CNTL) / 10; //dcf deep sleep divider 64 65 regs->CLK0_CLK8_ALLOW_DS = REG_READ(CLK0_CLK8_ALLOW_DS); //dcf deep sleep allow 66 67 regs->CLK0_CLK10_CURRENT_CNT = REG_READ(CLK0_CLK10_CURRENT_CNT) / 10; //dpref clk 68 69 bypass->dispclk_pypass = REG_READ(CLK0_CLK10_BYPASS_CNTL) & 0x0007; 70 if (bypass->dispclk_pypass < 0 || bypass->dispclk_pypass > 4) 71 bypass->dispclk_pypass = 0; 72 73 regs->CLK0_CLK11_CURRENT_CNT = REG_READ(CLK0_CLK11_CURRENT_CNT) / 10; //disp clk 74 75 bypass->dprefclk_bypass = REG_READ(CLK0_CLK11_BYPASS_CNTL) & 0x0007; 76 if (bypass->dprefclk_bypass < 0 || bypass->dprefclk_bypass > 4) 77 bypass->dprefclk_bypass = 0; 78 79 } 80