1 /* 2 * Copyright 2018 Advanced Micro Devices, Inc. 3 * 4 * Permission is hereby granted, free of charge, to any person obtaining a 5 * copy of this software and associated documentation files (the "Software"), 6 * to deal in the Software without restriction, including without limitation 7 * the rights to use, copy, modify, merge, publish, distribute, sublicense, 8 * and/or sell copies of the Software, and to permit persons to whom the 9 * Software is furnished to do so, subject to the following conditions: 10 * 11 * The above copyright notice and this permission notice shall be included in 12 * all copies or substantial portions of the Software. 13 * 14 * THE SOFTWARE IS PROVIDED "AS IS", WITHOUT WARRANTY OF ANY KIND, EXPRESS OR 15 * IMPLIED, INCLUDING BUT NOT LIMITED TO THE WARRANTIES OF MERCHANTABILITY, 16 * FITNESS FOR A PARTICULAR PURPOSE AND NONINFRINGEMENT. IN NO EVENT SHALL 17 * THE COPYRIGHT HOLDER(S) OR AUTHOR(S) BE LIABLE FOR ANY CLAIM, DAMAGES OR 18 * OTHER LIABILITY, WHETHER IN AN ACTION OF CONTRACT, TORT OR OTHERWISE, 19 * ARISING FROM, OUT OF OR IN CONNECTION WITH THE SOFTWARE OR THE USE OR 20 * OTHER DEALINGS IN THE SOFTWARE. 21 * 22 * Authors: AMD 23 * 24 */ 25 26 #include <linux/slab.h> 27 28 #include "reg_helper.h" 29 #include "core_types.h" 30 #include "clk_mgr_internal.h" 31 #include "rv1_clk_mgr.h" 32 #include "dce100/dce_clk_mgr.h" 33 #include "dce112/dce112_clk_mgr.h" 34 #include "rv1_clk_mgr_vbios_smu.h" 35 #include "rv1_clk_mgr_clk.h" 36 37 static void rv1_init_clocks(struct clk_mgr *clk_mgr) 38 { 39 memset(&(clk_mgr->clks), 0, sizeof(struct dc_clocks)); 40 } 41 42 static int rv1_determine_dppclk_threshold(struct clk_mgr_internal *clk_mgr, struct dc_clocks *new_clocks) 43 { 44 bool request_dpp_div = new_clocks->dispclk_khz > new_clocks->dppclk_khz; 45 bool dispclk_increase = new_clocks->dispclk_khz > clk_mgr->base.clks.dispclk_khz; 46 int disp_clk_threshold = new_clocks->max_supported_dppclk_khz; 47 bool cur_dpp_div = clk_mgr->base.clks.dispclk_khz > clk_mgr->base.clks.dppclk_khz; 48 49 /* increase clock, looking for div is 0 for current, request div is 1*/ 50 if (dispclk_increase) { 51 /* already divided by 2, no need to reach target clk with 2 steps*/ 52 if (cur_dpp_div) 53 return new_clocks->dispclk_khz; 54 55 /* request disp clk is lower than maximum supported dpp clk, 56 * no need to reach target clk with two steps. 57 */ 58 if (new_clocks->dispclk_khz <= disp_clk_threshold) 59 return new_clocks->dispclk_khz; 60 61 /* target dpp clk not request divided by 2, still within threshold */ 62 if (!request_dpp_div) 63 return new_clocks->dispclk_khz; 64 65 } else { 66 /* decrease clock, looking for current dppclk divided by 2, 67 * request dppclk not divided by 2. 68 */ 69 70 /* current dpp clk not divided by 2, no need to ramp*/ 71 if (!cur_dpp_div) 72 return new_clocks->dispclk_khz; 73 74 /* current disp clk is lower than current maximum dpp clk, 75 * no need to ramp 76 */ 77 if (clk_mgr->base.clks.dispclk_khz <= disp_clk_threshold) 78 return new_clocks->dispclk_khz; 79 80 /* request dpp clk need to be divided by 2 */ 81 if (request_dpp_div) 82 return new_clocks->dispclk_khz; 83 } 84 85 return disp_clk_threshold; 86 } 87 88 static void ramp_up_dispclk_with_dpp( 89 struct clk_mgr_internal *clk_mgr, 90 struct dc *dc, 91 struct dc_clocks *new_clocks, 92 bool safe_to_lower) 93 { 94 int i; 95 int dispclk_to_dpp_threshold = rv1_determine_dppclk_threshold(clk_mgr, new_clocks); 96 bool request_dpp_div = new_clocks->dispclk_khz > new_clocks->dppclk_khz; 97 98 /* this function is to change dispclk, dppclk and dprefclk according to 99 * bandwidth requirement. Its call stack is rv1_update_clocks --> 100 * update_clocks --> dcn10_prepare_bandwidth / dcn10_optimize_bandwidth 101 * --> prepare_bandwidth / optimize_bandwidth. before change dcn hw, 102 * prepare_bandwidth will be called first to allow enough clock, 103 * watermark for change, after end of dcn hw change, optimize_bandwidth 104 * is executed to lower clock to save power for new dcn hw settings. 105 * 106 * below is sequence of commit_planes_for_stream: 107 * 108 * step 1: prepare_bandwidth - raise clock to have enough bandwidth 109 * step 2: lock_doublebuffer_enable 110 * step 3: pipe_control_lock(true) - make dchubp register change will 111 * not take effect right way 112 * step 4: apply_ctx_for_surface - program dchubp 113 * step 5: pipe_control_lock(false) - dchubp register change take effect 114 * step 6: optimize_bandwidth --> dc_post_update_surfaces_to_stream 115 * for full_date, optimize clock to save power 116 * 117 * at end of step 1, dcn clocks (dprefclk, dispclk, dppclk) may be 118 * changed for new dchubp configuration. but real dcn hub dchubps are 119 * still running with old configuration until end of step 5. this need 120 * clocks settings at step 1 should not less than that before step 1. 121 * this is checked by two conditions: 1. if (should_set_clock(safe_to_lower 122 * , new_clocks->dispclk_khz, clk_mgr_base->clks.dispclk_khz) || 123 * new_clocks->dispclk_khz == clk_mgr_base->clks.dispclk_khz) 124 * 2. request_dpp_div = new_clocks->dispclk_khz > new_clocks->dppclk_khz 125 * 126 * the second condition is based on new dchubp configuration. dppclk 127 * for new dchubp may be different from dppclk before step 1. 128 * for example, before step 1, dchubps are as below: 129 * pipe 0: recout=(0,40,1920,980) viewport=(0,0,1920,979) 130 * pipe 1: recout=(0,0,1920,1080) viewport=(0,0,1920,1080) 131 * for dppclk for pipe0 need dppclk = dispclk 132 * 133 * new dchubp pipe split configuration: 134 * pipe 0: recout=(0,0,960,1080) viewport=(0,0,960,1080) 135 * pipe 1: recout=(960,0,960,1080) viewport=(960,0,960,1080) 136 * dppclk only needs dppclk = dispclk /2. 137 * 138 * dispclk, dppclk are not lock by otg master lock. they take effect 139 * after step 1. during this transition, dispclk are the same, but 140 * dppclk is changed to half of previous clock for old dchubp 141 * configuration between step 1 and step 6. This may cause p-state 142 * warning intermittently. 143 * 144 * for new_clocks->dispclk_khz == clk_mgr_base->clks.dispclk_khz, we 145 * need make sure dppclk are not changed to less between step 1 and 6. 146 * for new_clocks->dispclk_khz > clk_mgr_base->clks.dispclk_khz, 147 * new display clock is raised, but we do not know ratio of 148 * new_clocks->dispclk_khz and clk_mgr_base->clks.dispclk_khz, 149 * new_clocks->dispclk_khz /2 does not guarantee equal or higher than 150 * old dppclk. we could ignore power saving different between 151 * dppclk = displck and dppclk = dispclk / 2 between step 1 and step 6. 152 * as long as safe_to_lower = false, set dpclk = dispclk to simplify 153 * condition check. 154 * todo: review this change for other asic. 155 **/ 156 if (!safe_to_lower) 157 request_dpp_div = false; 158 159 /* set disp clk to dpp clk threshold */ 160 161 clk_mgr->funcs->set_dispclk(clk_mgr, dispclk_to_dpp_threshold); 162 clk_mgr->funcs->set_dprefclk(clk_mgr); 163 164 165 /* update request dpp clk division option */ 166 for (i = 0; i < dc->res_pool->pipe_count; i++) { 167 struct pipe_ctx *pipe_ctx = &dc->current_state->res_ctx.pipe_ctx[i]; 168 169 if (!pipe_ctx->plane_state) 170 continue; 171 172 pipe_ctx->plane_res.dpp->funcs->dpp_dppclk_control( 173 pipe_ctx->plane_res.dpp, 174 request_dpp_div, 175 true); 176 } 177 178 /* If target clk not same as dppclk threshold, set to target clock */ 179 if (dispclk_to_dpp_threshold != new_clocks->dispclk_khz) { 180 clk_mgr->funcs->set_dispclk(clk_mgr, new_clocks->dispclk_khz); 181 clk_mgr->funcs->set_dprefclk(clk_mgr); 182 } 183 184 185 clk_mgr->base.clks.dispclk_khz = new_clocks->dispclk_khz; 186 clk_mgr->base.clks.dppclk_khz = new_clocks->dppclk_khz; 187 clk_mgr->base.clks.max_supported_dppclk_khz = new_clocks->max_supported_dppclk_khz; 188 } 189 190 static void rv1_update_clocks(struct clk_mgr *clk_mgr_base, 191 struct dc_state *context, 192 bool safe_to_lower) 193 { 194 struct clk_mgr_internal *clk_mgr = TO_CLK_MGR_INTERNAL(clk_mgr_base); 195 struct dc *dc = clk_mgr_base->ctx->dc; 196 struct dc_debug_options *debug = &dc->debug; 197 struct dc_clocks *new_clocks = &context->bw_ctx.bw.dcn.clk; 198 struct pp_smu_funcs_rv *pp_smu = NULL; 199 bool send_request_to_increase = false; 200 bool send_request_to_lower = false; 201 int display_count; 202 203 bool enter_display_off = false; 204 205 ASSERT(clk_mgr->pp_smu); 206 207 if (dc->work_arounds.skip_clock_update) 208 return; 209 210 pp_smu = &clk_mgr->pp_smu->rv_funcs; 211 212 display_count = clk_mgr_helper_get_active_display_cnt(dc, context); 213 214 if (display_count == 0) 215 enter_display_off = true; 216 217 if (enter_display_off == safe_to_lower) { 218 /* 219 * Notify SMU active displays 220 * if function pointer not set up, this message is 221 * sent as part of pplib_apply_display_requirements. 222 */ 223 if (pp_smu->set_display_count) 224 pp_smu->set_display_count(&pp_smu->pp_smu, display_count); 225 } 226 227 if (new_clocks->dispclk_khz > clk_mgr_base->clks.dispclk_khz 228 || new_clocks->phyclk_khz > clk_mgr_base->clks.phyclk_khz 229 || new_clocks->fclk_khz > clk_mgr_base->clks.fclk_khz 230 || new_clocks->dcfclk_khz > clk_mgr_base->clks.dcfclk_khz) 231 send_request_to_increase = true; 232 233 if (should_set_clock(safe_to_lower, new_clocks->phyclk_khz, clk_mgr_base->clks.phyclk_khz)) { 234 clk_mgr_base->clks.phyclk_khz = new_clocks->phyclk_khz; 235 send_request_to_lower = true; 236 } 237 238 // F Clock 239 if (debug->force_fclk_khz != 0) 240 new_clocks->fclk_khz = debug->force_fclk_khz; 241 242 if (should_set_clock(safe_to_lower, new_clocks->fclk_khz, clk_mgr_base->clks.fclk_khz)) { 243 clk_mgr_base->clks.fclk_khz = new_clocks->fclk_khz; 244 send_request_to_lower = true; 245 } 246 247 //DCF Clock 248 if (should_set_clock(safe_to_lower, new_clocks->dcfclk_khz, clk_mgr_base->clks.dcfclk_khz)) { 249 clk_mgr_base->clks.dcfclk_khz = new_clocks->dcfclk_khz; 250 send_request_to_lower = true; 251 } 252 253 if (should_set_clock(safe_to_lower, 254 new_clocks->dcfclk_deep_sleep_khz, clk_mgr_base->clks.dcfclk_deep_sleep_khz)) { 255 clk_mgr_base->clks.dcfclk_deep_sleep_khz = new_clocks->dcfclk_deep_sleep_khz; 256 send_request_to_lower = true; 257 } 258 259 /* make sure dcf clk is before dpp clk to 260 * make sure we have enough voltage to run dpp clk 261 */ 262 if (send_request_to_increase) { 263 /*use dcfclk to request voltage*/ 264 if (pp_smu->set_hard_min_fclk_by_freq && 265 pp_smu->set_hard_min_dcfclk_by_freq && 266 pp_smu->set_min_deep_sleep_dcfclk) { 267 pp_smu->set_hard_min_fclk_by_freq(&pp_smu->pp_smu, khz_to_mhz_ceil(new_clocks->fclk_khz)); 268 pp_smu->set_hard_min_dcfclk_by_freq(&pp_smu->pp_smu, khz_to_mhz_ceil(new_clocks->dcfclk_khz)); 269 pp_smu->set_min_deep_sleep_dcfclk(&pp_smu->pp_smu, khz_to_mhz_ceil(new_clocks->dcfclk_deep_sleep_khz)); 270 } 271 } 272 273 /* dcn1 dppclk is tied to dispclk */ 274 /* program dispclk on = as a w/a for sleep resume clock ramping issues */ 275 if (should_set_clock(safe_to_lower, new_clocks->dispclk_khz, clk_mgr_base->clks.dispclk_khz) 276 || new_clocks->dispclk_khz == clk_mgr_base->clks.dispclk_khz) { 277 ramp_up_dispclk_with_dpp(clk_mgr, dc, new_clocks, safe_to_lower); 278 clk_mgr_base->clks.dispclk_khz = new_clocks->dispclk_khz; 279 send_request_to_lower = true; 280 } 281 282 if (!send_request_to_increase && send_request_to_lower) { 283 /*use dcfclk to request voltage*/ 284 if (pp_smu->set_hard_min_fclk_by_freq && 285 pp_smu->set_hard_min_dcfclk_by_freq && 286 pp_smu->set_min_deep_sleep_dcfclk) { 287 pp_smu->set_hard_min_fclk_by_freq(&pp_smu->pp_smu, khz_to_mhz_ceil(new_clocks->fclk_khz)); 288 pp_smu->set_hard_min_dcfclk_by_freq(&pp_smu->pp_smu, khz_to_mhz_ceil(new_clocks->dcfclk_khz)); 289 pp_smu->set_min_deep_sleep_dcfclk(&pp_smu->pp_smu, khz_to_mhz_ceil(new_clocks->dcfclk_deep_sleep_khz)); 290 } 291 } 292 } 293 294 static void rv1_enable_pme_wa(struct clk_mgr *clk_mgr_base) 295 { 296 struct clk_mgr_internal *clk_mgr = TO_CLK_MGR_INTERNAL(clk_mgr_base); 297 struct pp_smu_funcs_rv *pp_smu = NULL; 298 299 if (clk_mgr->pp_smu) { 300 pp_smu = &clk_mgr->pp_smu->rv_funcs; 301 302 if (pp_smu->set_pme_wa_enable) 303 pp_smu->set_pme_wa_enable(&pp_smu->pp_smu); 304 } 305 } 306 307 static struct clk_mgr_funcs rv1_clk_funcs = { 308 .init_clocks = rv1_init_clocks, 309 .get_dp_ref_clk_frequency = dce12_get_dp_ref_freq_khz, 310 .update_clocks = rv1_update_clocks, 311 .enable_pme_wa = rv1_enable_pme_wa, 312 }; 313 314 static struct clk_mgr_internal_funcs rv1_clk_internal_funcs = { 315 .set_dispclk = rv1_vbios_smu_set_dispclk, 316 .set_dprefclk = dce112_set_dprefclk 317 }; 318 319 void rv1_clk_mgr_construct(struct dc_context *ctx, struct clk_mgr_internal *clk_mgr, struct pp_smu_funcs *pp_smu) 320 { 321 struct dc_debug_options *debug = &ctx->dc->debug; 322 struct dc_bios *bp = ctx->dc_bios; 323 324 clk_mgr->base.ctx = ctx; 325 clk_mgr->pp_smu = pp_smu; 326 clk_mgr->base.funcs = &rv1_clk_funcs; 327 clk_mgr->funcs = &rv1_clk_internal_funcs; 328 329 clk_mgr->dfs_bypass_disp_clk = 0; 330 331 clk_mgr->dprefclk_ss_percentage = 0; 332 clk_mgr->dprefclk_ss_divider = 1000; 333 clk_mgr->ss_on_dprefclk = false; 334 clk_mgr->base.dprefclk_khz = 600000; 335 336 if (bp->integrated_info) 337 clk_mgr->base.dentist_vco_freq_khz = bp->integrated_info->dentist_vco_freq; 338 if (bp->fw_info_valid && clk_mgr->base.dentist_vco_freq_khz == 0) { 339 clk_mgr->base.dentist_vco_freq_khz = bp->fw_info.smu_gpu_pll_output_freq; 340 if (clk_mgr->base.dentist_vco_freq_khz == 0) 341 clk_mgr->base.dentist_vco_freq_khz = 3600000; 342 } 343 344 if (!debug->disable_dfs_bypass && bp->integrated_info) 345 if (bp->integrated_info->gpu_cap_info & DFS_BYPASS_ENABLE) 346 clk_mgr->dfs_bypass_enabled = true; 347 348 dce_clock_read_ss_info(clk_mgr); 349 } 350 351 352