1 /* 2 * Copyright 2012-15 Advanced Micro Devices, Inc. 3 * 4 * Permission is hereby granted, free of charge, to any person obtaining a 5 * copy of this software and associated documentation files (the "Software"), 6 * to deal in the Software without restriction, including without limitation 7 * the rights to use, copy, modify, merge, publish, distribute, sublicense, 8 * and/or sell copies of the Software, and to permit persons to whom the 9 * Software is furnished to do so, subject to the following conditions: 10 * 11 * The above copyright notice and this permission notice shall be included in 12 * all copies or substantial portions of the Software. 13 * 14 * THE SOFTWARE IS PROVIDED "AS IS", WITHOUT WARRANTY OF ANY KIND, EXPRESS OR 15 * IMPLIED, INCLUDING BUT NOT LIMITED TO THE WARRANTIES OF MERCHANTABILITY, 16 * FITNESS FOR A PARTICULAR PURPOSE AND NONINFRINGEMENT. IN NO EVENT SHALL 17 * THE COPYRIGHT HOLDER(S) OR AUTHOR(S) BE LIABLE FOR ANY CLAIM, DAMAGES OR 18 * OTHER LIABILITY, WHETHER IN AN ACTION OF CONTRACT, TORT OR OTHERWISE, 19 * ARISING FROM, OUT OF OR IN CONNECTION WITH THE SOFTWARE OR THE USE OR 20 * OTHER DEALINGS IN THE SOFTWARE. 21 * 22 * Authors: AMD 23 * 24 */ 25 26 #include "dm_services.h" 27 28 #include "ObjectID.h" 29 #include "atomfirmware.h" 30 31 #include "include/bios_parser_types.h" 32 33 #include "command_table_helper2.h" 34 35 bool dal_bios_parser_init_cmd_tbl_helper2( 36 const struct command_table_helper **h, 37 enum dce_version dce) 38 { 39 switch (dce) { 40 case DCE_VERSION_8_0: 41 case DCE_VERSION_8_1: 42 case DCE_VERSION_8_3: 43 *h = dal_cmd_tbl_helper_dce80_get_table(); 44 return true; 45 46 case DCE_VERSION_10_0: 47 *h = dal_cmd_tbl_helper_dce110_get_table(); 48 return true; 49 50 case DCE_VERSION_11_0: 51 *h = dal_cmd_tbl_helper_dce110_get_table(); 52 return true; 53 54 case DCE_VERSION_11_2: 55 case DCE_VERSION_11_22: 56 case DCE_VERSION_12_0: 57 case DCE_VERSION_12_1: 58 *h = dal_cmd_tbl_helper_dce112_get_table2(); 59 return true; 60 #if defined(CONFIG_DRM_AMD_DC_DCN) 61 case DCN_VERSION_1_0: 62 case DCN_VERSION_1_01: 63 case DCN_VERSION_2_0: 64 case DCN_VERSION_2_1: 65 *h = dal_cmd_tbl_helper_dce112_get_table2(); 66 return true; 67 #endif 68 #if defined(CONFIG_DRM_AMD_DC_DCN3_0) 69 case DCN_VERSION_3_0: 70 *h = dal_cmd_tbl_helper_dce112_get_table2(); 71 return true; 72 #endif 73 74 default: 75 /* Unsupported DCE */ 76 BREAK_TO_DEBUGGER(); 77 return false; 78 } 79 } 80 81 /* real implementations */ 82 83 bool dal_cmd_table_helper_controller_id_to_atom2( 84 enum controller_id id, 85 uint8_t *atom_id) 86 { 87 if (atom_id == NULL) { 88 BREAK_TO_DEBUGGER(); 89 return false; 90 } 91 92 switch (id) { 93 case CONTROLLER_ID_D0: 94 *atom_id = ATOM_CRTC1; 95 return true; 96 case CONTROLLER_ID_D1: 97 *atom_id = ATOM_CRTC2; 98 return true; 99 case CONTROLLER_ID_D2: 100 *atom_id = ATOM_CRTC3; 101 return true; 102 case CONTROLLER_ID_D3: 103 *atom_id = ATOM_CRTC4; 104 return true; 105 case CONTROLLER_ID_D4: 106 *atom_id = ATOM_CRTC5; 107 return true; 108 case CONTROLLER_ID_D5: 109 *atom_id = ATOM_CRTC6; 110 return true; 111 /* TODO :case CONTROLLER_ID_UNDERLAY0: 112 *atom_id = ATOM_UNDERLAY_PIPE0; 113 return true; 114 */ 115 case CONTROLLER_ID_UNDEFINED: 116 *atom_id = ATOM_CRTC_INVALID; 117 return true; 118 default: 119 /* Wrong controller id */ 120 BREAK_TO_DEBUGGER(); 121 return false; 122 } 123 } 124 125 /** 126 * translate_transmitter_bp_to_atom 127 * 128 * @brief 129 * Translate the Transmitter to the corresponding ATOM BIOS value 130 * 131 * @param 132 * input transmitter 133 * output digitalTransmitter 134 * // =00: Digital Transmitter1 ( UNIPHY linkAB ) 135 * // =01: Digital Transmitter2 ( UNIPHY linkCD ) 136 * // =02: Digital Transmitter3 ( UNIPHY linkEF ) 137 */ 138 uint8_t dal_cmd_table_helper_transmitter_bp_to_atom2( 139 enum transmitter t) 140 { 141 switch (t) { 142 case TRANSMITTER_UNIPHY_A: 143 case TRANSMITTER_UNIPHY_B: 144 case TRANSMITTER_TRAVIS_LCD: 145 return 0; 146 case TRANSMITTER_UNIPHY_C: 147 case TRANSMITTER_UNIPHY_D: 148 return 1; 149 case TRANSMITTER_UNIPHY_E: 150 case TRANSMITTER_UNIPHY_F: 151 return 2; 152 default: 153 /* Invalid Transmitter Type! */ 154 BREAK_TO_DEBUGGER(); 155 return 0; 156 } 157 } 158 159 uint32_t dal_cmd_table_helper_encoder_mode_bp_to_atom2( 160 enum signal_type s, 161 bool enable_dp_audio) 162 { 163 switch (s) { 164 case SIGNAL_TYPE_DVI_SINGLE_LINK: 165 case SIGNAL_TYPE_DVI_DUAL_LINK: 166 return ATOM_ENCODER_MODE_DVI; 167 case SIGNAL_TYPE_HDMI_TYPE_A: 168 return ATOM_ENCODER_MODE_HDMI; 169 case SIGNAL_TYPE_LVDS: 170 return ATOM_ENCODER_MODE_LVDS; 171 case SIGNAL_TYPE_EDP: 172 case SIGNAL_TYPE_DISPLAY_PORT_MST: 173 case SIGNAL_TYPE_DISPLAY_PORT: 174 case SIGNAL_TYPE_VIRTUAL: 175 if (enable_dp_audio) 176 return ATOM_ENCODER_MODE_DP_AUDIO; 177 else 178 return ATOM_ENCODER_MODE_DP; 179 case SIGNAL_TYPE_RGB: 180 return ATOM_ENCODER_MODE_CRT; 181 default: 182 return ATOM_ENCODER_MODE_CRT; 183 } 184 } 185 186 bool dal_cmd_table_helper_clock_source_id_to_ref_clk_src2( 187 enum clock_source_id id, 188 uint32_t *ref_clk_src_id) 189 { 190 if (ref_clk_src_id == NULL) { 191 BREAK_TO_DEBUGGER(); 192 return false; 193 } 194 195 switch (id) { 196 case CLOCK_SOURCE_ID_PLL1: 197 *ref_clk_src_id = ENCODER_REFCLK_SRC_P1PLL; 198 return true; 199 case CLOCK_SOURCE_ID_PLL2: 200 *ref_clk_src_id = ENCODER_REFCLK_SRC_P2PLL; 201 return true; 202 /*TODO:case CLOCK_SOURCE_ID_DCPLL: 203 *ref_clk_src_id = ENCODER_REFCLK_SRC_DCPLL; 204 return true; 205 */ 206 case CLOCK_SOURCE_ID_EXTERNAL: 207 *ref_clk_src_id = ENCODER_REFCLK_SRC_EXTCLK; 208 return true; 209 case CLOCK_SOURCE_ID_UNDEFINED: 210 *ref_clk_src_id = ENCODER_REFCLK_SRC_INVALID; 211 return true; 212 default: 213 /* Unsupported clock source id */ 214 BREAK_TO_DEBUGGER(); 215 return false; 216 } 217 } 218 219 uint8_t dal_cmd_table_helper_encoder_id_to_atom2( 220 enum encoder_id id) 221 { 222 switch (id) { 223 case ENCODER_ID_INTERNAL_LVDS: 224 return ENCODER_OBJECT_ID_INTERNAL_LVDS; 225 case ENCODER_ID_INTERNAL_TMDS1: 226 return ENCODER_OBJECT_ID_INTERNAL_TMDS1; 227 case ENCODER_ID_INTERNAL_TMDS2: 228 return ENCODER_OBJECT_ID_INTERNAL_TMDS2; 229 case ENCODER_ID_INTERNAL_DAC1: 230 return ENCODER_OBJECT_ID_INTERNAL_DAC1; 231 case ENCODER_ID_INTERNAL_DAC2: 232 return ENCODER_OBJECT_ID_INTERNAL_DAC2; 233 case ENCODER_ID_INTERNAL_LVTM1: 234 return ENCODER_OBJECT_ID_INTERNAL_LVTM1; 235 case ENCODER_ID_INTERNAL_HDMI: 236 return ENCODER_OBJECT_ID_HDMI_INTERNAL; 237 case ENCODER_ID_EXTERNAL_TRAVIS: 238 return ENCODER_OBJECT_ID_TRAVIS; 239 case ENCODER_ID_EXTERNAL_NUTMEG: 240 return ENCODER_OBJECT_ID_NUTMEG; 241 case ENCODER_ID_INTERNAL_KLDSCP_TMDS1: 242 return ENCODER_OBJECT_ID_INTERNAL_KLDSCP_TMDS1; 243 case ENCODER_ID_INTERNAL_KLDSCP_DAC1: 244 return ENCODER_OBJECT_ID_INTERNAL_KLDSCP_DAC1; 245 case ENCODER_ID_INTERNAL_KLDSCP_DAC2: 246 return ENCODER_OBJECT_ID_INTERNAL_KLDSCP_DAC2; 247 case ENCODER_ID_EXTERNAL_MVPU_FPGA: 248 return ENCODER_OBJECT_ID_MVPU_FPGA; 249 case ENCODER_ID_INTERNAL_DDI: 250 return ENCODER_OBJECT_ID_INTERNAL_DDI; 251 case ENCODER_ID_INTERNAL_UNIPHY: 252 return ENCODER_OBJECT_ID_INTERNAL_UNIPHY; 253 case ENCODER_ID_INTERNAL_KLDSCP_LVTMA: 254 return ENCODER_OBJECT_ID_INTERNAL_KLDSCP_LVTMA; 255 case ENCODER_ID_INTERNAL_UNIPHY1: 256 return ENCODER_OBJECT_ID_INTERNAL_UNIPHY1; 257 case ENCODER_ID_INTERNAL_UNIPHY2: 258 return ENCODER_OBJECT_ID_INTERNAL_UNIPHY2; 259 case ENCODER_ID_INTERNAL_UNIPHY3: 260 return ENCODER_OBJECT_ID_INTERNAL_UNIPHY3; 261 case ENCODER_ID_INTERNAL_WIRELESS: 262 return ENCODER_OBJECT_ID_INTERNAL_VCE; 263 case ENCODER_ID_INTERNAL_VIRTUAL: 264 return ENCODER_OBJECT_ID_NONE; 265 case ENCODER_ID_UNKNOWN: 266 return ENCODER_OBJECT_ID_NONE; 267 default: 268 /* Invalid encoder id */ 269 BREAK_TO_DEBUGGER(); 270 return ENCODER_OBJECT_ID_NONE; 271 } 272 } 273