1 /* 2 * Copyright 2012-15 Advanced Micro Devices, Inc. 3 * 4 * Permission is hereby granted, free of charge, to any person obtaining a 5 * copy of this software and associated documentation files (the "Software"), 6 * to deal in the Software without restriction, including without limitation 7 * the rights to use, copy, modify, merge, publish, distribute, sublicense, 8 * and/or sell copies of the Software, and to permit persons to whom the 9 * Software is furnished to do so, subject to the following conditions: 10 * 11 * The above copyright notice and this permission notice shall be included in 12 * all copies or substantial portions of the Software. 13 * 14 * THE SOFTWARE IS PROVIDED "AS IS", WITHOUT WARRANTY OF ANY KIND, EXPRESS OR 15 * IMPLIED, INCLUDING BUT NOT LIMITED TO THE WARRANTIES OF MERCHANTABILITY, 16 * FITNESS FOR A PARTICULAR PURPOSE AND NONINFRINGEMENT. IN NO EVENT SHALL 17 * THE COPYRIGHT HOLDER(S) OR AUTHOR(S) BE LIABLE FOR ANY CLAIM, DAMAGES OR 18 * OTHER LIABILITY, WHETHER IN AN ACTION OF CONTRACT, TORT OR OTHERWISE, 19 * ARISING FROM, OUT OF OR IN CONNECTION WITH THE SOFTWARE OR THE USE OR 20 * OTHER DEALINGS IN THE SOFTWARE. 21 * 22 * Authors: AMD 23 * 24 */ 25 26 #include "dm_services.h" 27 28 #include "ObjectID.h" 29 #include "atomfirmware.h" 30 31 #include "include/bios_parser_interface.h" 32 33 #include "command_table2.h" 34 #include "command_table_helper2.h" 35 #include "bios_parser_helper.h" 36 #include "bios_parser_types_internal2.h" 37 38 #define GET_INDEX_INTO_MASTER_TABLE(MasterOrData, FieldName)\ 39 (((char *)(&((\ 40 struct atom_master_list_of_##MasterOrData##_functions_v2_1 *)0)\ 41 ->FieldName)-(char *)0)/sizeof(uint16_t)) 42 43 #define EXEC_BIOS_CMD_TABLE(fname, params)\ 44 (cgs_atom_exec_cmd_table(bp->base.ctx->cgs_device, \ 45 GET_INDEX_INTO_MASTER_TABLE(command, fname), \ 46 ¶ms) == 0) 47 48 #define BIOS_CMD_TABLE_REVISION(fname, frev, crev)\ 49 cgs_atom_get_cmd_table_revs(bp->base.ctx->cgs_device, \ 50 GET_INDEX_INTO_MASTER_TABLE(command, fname), &frev, &crev) 51 52 #define BIOS_CMD_TABLE_PARA_REVISION(fname)\ 53 bios_cmd_table_para_revision(bp->base.ctx->cgs_device, \ 54 GET_INDEX_INTO_MASTER_TABLE(command, fname)) 55 56 static void init_dig_encoder_control(struct bios_parser *bp); 57 static void init_transmitter_control(struct bios_parser *bp); 58 static void init_set_pixel_clock(struct bios_parser *bp); 59 60 static void init_set_crtc_timing(struct bios_parser *bp); 61 62 static void init_select_crtc_source(struct bios_parser *bp); 63 static void init_enable_crtc(struct bios_parser *bp); 64 65 static void init_external_encoder_control(struct bios_parser *bp); 66 static void init_enable_disp_power_gating(struct bios_parser *bp); 67 static void init_set_dce_clock(struct bios_parser *bp); 68 static void init_get_smu_clock_info(struct bios_parser *bp); 69 70 void dal_firmware_parser_init_cmd_tbl(struct bios_parser *bp) 71 { 72 init_dig_encoder_control(bp); 73 init_transmitter_control(bp); 74 init_set_pixel_clock(bp); 75 76 init_set_crtc_timing(bp); 77 78 init_select_crtc_source(bp); 79 init_enable_crtc(bp); 80 81 init_external_encoder_control(bp); 82 init_enable_disp_power_gating(bp); 83 init_set_dce_clock(bp); 84 init_get_smu_clock_info(bp); 85 } 86 87 static uint32_t bios_cmd_table_para_revision(void *cgs_device, 88 uint32_t index) 89 { 90 uint8_t frev, crev; 91 92 if (cgs_atom_get_cmd_table_revs(cgs_device, 93 index, 94 &frev, &crev) != 0) 95 return 0; 96 return crev; 97 } 98 99 /****************************************************************************** 100 ****************************************************************************** 101 ** 102 ** D I G E N C O D E R C O N T R O L 103 ** 104 ****************************************************************************** 105 *****************************************************************************/ 106 107 static enum bp_result encoder_control_digx_v1_5( 108 struct bios_parser *bp, 109 struct bp_encoder_control *cntl); 110 111 static void init_dig_encoder_control(struct bios_parser *bp) 112 { 113 uint32_t version = 114 BIOS_CMD_TABLE_PARA_REVISION(digxencodercontrol); 115 116 switch (version) { 117 case 5: 118 bp->cmd_tbl.dig_encoder_control = encoder_control_digx_v1_5; 119 break; 120 default: 121 dm_output_to_console("Don't have dig_encoder_control for v%d\n", version); 122 bp->cmd_tbl.dig_encoder_control = NULL; 123 break; 124 } 125 } 126 127 static enum bp_result encoder_control_digx_v1_5( 128 struct bios_parser *bp, 129 struct bp_encoder_control *cntl) 130 { 131 enum bp_result result = BP_RESULT_FAILURE; 132 struct dig_encoder_stream_setup_parameters_v1_5 params = {0}; 133 134 params.digid = (uint8_t)(cntl->engine_id); 135 params.action = bp->cmd_helper->encoder_action_to_atom(cntl->action); 136 137 params.pclk_10khz = cntl->pixel_clock / 10; 138 params.digmode = 139 (uint8_t)(bp->cmd_helper->encoder_mode_bp_to_atom( 140 cntl->signal, 141 cntl->enable_dp_audio)); 142 params.lanenum = (uint8_t)(cntl->lanes_number); 143 144 switch (cntl->color_depth) { 145 case COLOR_DEPTH_888: 146 params.bitpercolor = PANEL_8BIT_PER_COLOR; 147 break; 148 case COLOR_DEPTH_101010: 149 params.bitpercolor = PANEL_10BIT_PER_COLOR; 150 break; 151 case COLOR_DEPTH_121212: 152 params.bitpercolor = PANEL_12BIT_PER_COLOR; 153 break; 154 case COLOR_DEPTH_161616: 155 params.bitpercolor = PANEL_16BIT_PER_COLOR; 156 break; 157 default: 158 break; 159 } 160 161 if (cntl->signal == SIGNAL_TYPE_HDMI_TYPE_A) 162 switch (cntl->color_depth) { 163 case COLOR_DEPTH_101010: 164 params.pclk_10khz = 165 (params.pclk_10khz * 30) / 24; 166 break; 167 case COLOR_DEPTH_121212: 168 params.pclk_10khz = 169 (params.pclk_10khz * 36) / 24; 170 break; 171 case COLOR_DEPTH_161616: 172 params.pclk_10khz = 173 (params.pclk_10khz * 48) / 24; 174 break; 175 default: 176 break; 177 } 178 179 if (EXEC_BIOS_CMD_TABLE(digxencodercontrol, params)) 180 result = BP_RESULT_OK; 181 182 return result; 183 } 184 185 /***************************************************************************** 186 ****************************************************************************** 187 ** 188 ** TRANSMITTER CONTROL 189 ** 190 ****************************************************************************** 191 *****************************************************************************/ 192 193 static enum bp_result transmitter_control_v1_6( 194 struct bios_parser *bp, 195 struct bp_transmitter_control *cntl); 196 197 static void init_transmitter_control(struct bios_parser *bp) 198 { 199 uint8_t frev; 200 uint8_t crev; 201 202 if (BIOS_CMD_TABLE_REVISION(dig1transmittercontrol, frev, crev) != 0) 203 BREAK_TO_DEBUGGER(); 204 switch (crev) { 205 case 6: 206 bp->cmd_tbl.transmitter_control = transmitter_control_v1_6; 207 break; 208 default: 209 dm_output_to_console("Don't have transmitter_control for v%d\n", crev); 210 bp->cmd_tbl.transmitter_control = NULL; 211 break; 212 } 213 } 214 215 static enum bp_result transmitter_control_v1_6( 216 struct bios_parser *bp, 217 struct bp_transmitter_control *cntl) 218 { 219 enum bp_result result = BP_RESULT_FAILURE; 220 const struct command_table_helper *cmd = bp->cmd_helper; 221 struct dig_transmitter_control_ps_allocation_v1_6 ps = { { 0 } }; 222 223 ps.param.phyid = cmd->phy_id_to_atom(cntl->transmitter); 224 ps.param.action = (uint8_t)cntl->action; 225 226 if (cntl->action == TRANSMITTER_CONTROL_SET_VOLTAGE_AND_PREEMPASIS) 227 ps.param.mode_laneset.dplaneset = (uint8_t)cntl->lane_settings; 228 else 229 ps.param.mode_laneset.digmode = 230 cmd->signal_type_to_atom_dig_mode(cntl->signal); 231 232 ps.param.lanenum = (uint8_t)cntl->lanes_number; 233 ps.param.hpdsel = cmd->hpd_sel_to_atom(cntl->hpd_sel); 234 ps.param.digfe_sel = cmd->dig_encoder_sel_to_atom(cntl->engine_id); 235 ps.param.connobj_id = (uint8_t)cntl->connector_obj_id.id; 236 ps.param.symclk_10khz = cntl->pixel_clock/10; 237 238 239 if (cntl->action == TRANSMITTER_CONTROL_ENABLE || 240 cntl->action == TRANSMITTER_CONTROL_ACTIAVATE || 241 cntl->action == TRANSMITTER_CONTROL_DEACTIVATE) { 242 dm_logger_write(bp->base.ctx->logger, LOG_BIOS,\ 243 "%s:ps.param.symclk_10khz = %d\n",\ 244 __func__, ps.param.symclk_10khz); 245 } 246 247 248 /*color_depth not used any more, driver has deep color factor in the Phyclk*/ 249 if (EXEC_BIOS_CMD_TABLE(dig1transmittercontrol, ps)) 250 result = BP_RESULT_OK; 251 return result; 252 } 253 254 /****************************************************************************** 255 ****************************************************************************** 256 ** 257 ** SET PIXEL CLOCK 258 ** 259 ****************************************************************************** 260 *****************************************************************************/ 261 262 static enum bp_result set_pixel_clock_v7( 263 struct bios_parser *bp, 264 struct bp_pixel_clock_parameters *bp_params); 265 266 static void init_set_pixel_clock(struct bios_parser *bp) 267 { 268 switch (BIOS_CMD_TABLE_PARA_REVISION(setpixelclock)) { 269 case 7: 270 bp->cmd_tbl.set_pixel_clock = set_pixel_clock_v7; 271 break; 272 default: 273 dm_output_to_console("Don't have set_pixel_clock for v%d\n", 274 BIOS_CMD_TABLE_PARA_REVISION(setpixelclock)); 275 bp->cmd_tbl.set_pixel_clock = NULL; 276 break; 277 } 278 } 279 280 281 282 static enum bp_result set_pixel_clock_v7( 283 struct bios_parser *bp, 284 struct bp_pixel_clock_parameters *bp_params) 285 { 286 enum bp_result result = BP_RESULT_FAILURE; 287 struct set_pixel_clock_parameter_v1_7 clk; 288 uint8_t controller_id; 289 uint32_t pll_id; 290 291 memset(&clk, 0, sizeof(clk)); 292 293 if (bp->cmd_helper->clock_source_id_to_atom(bp_params->pll_id, &pll_id) 294 && bp->cmd_helper->controller_id_to_atom(bp_params-> 295 controller_id, &controller_id)) { 296 /* Note: VBIOS still wants to use ucCRTC name which is now 297 * 1 byte in ULONG 298 *typedef struct _CRTC_PIXEL_CLOCK_FREQ 299 *{ 300 * target the pixel clock to drive the CRTC timing. 301 * ULONG ulPixelClock:24; 302 * 0 means disable PPLL/DCPLL. Expanded to 24 bits comparing to 303 * previous version. 304 * ATOM_CRTC1~6, indicate the CRTC controller to 305 * ULONG ucCRTC:8; 306 * drive the pixel clock. not used for DCPLL case. 307 *}CRTC_PIXEL_CLOCK_FREQ; 308 *union 309 *{ 310 * pixel clock and CRTC id frequency 311 * CRTC_PIXEL_CLOCK_FREQ ulCrtcPclkFreq; 312 * ULONG ulDispEngClkFreq; dispclk frequency 313 *}; 314 */ 315 clk.crtc_id = controller_id; 316 clk.pll_id = (uint8_t) pll_id; 317 clk.encoderobjid = 318 bp->cmd_helper->encoder_id_to_atom( 319 dal_graphics_object_id_get_encoder_id( 320 bp_params->encoder_object_id)); 321 322 clk.encoder_mode = (uint8_t) bp-> 323 cmd_helper->encoder_mode_bp_to_atom( 324 bp_params->signal_type, false); 325 326 /* We need to convert from KHz units into 10KHz units */ 327 clk.pixclk_100hz = cpu_to_le32(bp_params->target_pixel_clock * 328 10); 329 330 clk.deep_color_ratio = 331 (uint8_t) bp->cmd_helper-> 332 transmitter_color_depth_to_atom( 333 bp_params->color_depth); 334 dm_logger_write(bp->base.ctx->logger, LOG_BIOS,\ 335 "%s:program display clock = %d"\ 336 "colorDepth = %d\n", __func__,\ 337 bp_params->target_pixel_clock, bp_params->color_depth); 338 339 if (bp_params->flags.FORCE_PROGRAMMING_OF_PLL) 340 clk.miscinfo |= PIXEL_CLOCK_V7_MISC_FORCE_PROG_PPLL; 341 342 if (bp_params->flags.PROGRAM_PHY_PLL_ONLY) 343 clk.miscinfo |= PIXEL_CLOCK_V7_MISC_PROG_PHYPLL; 344 345 if (bp_params->flags.SUPPORT_YUV_420) 346 clk.miscinfo |= PIXEL_CLOCK_V7_MISC_YUV420_MODE; 347 348 if (bp_params->flags.SET_XTALIN_REF_SRC) 349 clk.miscinfo |= PIXEL_CLOCK_V7_MISC_REF_DIV_SRC_XTALIN; 350 351 if (bp_params->flags.SET_GENLOCK_REF_DIV_SRC) 352 clk.miscinfo |= PIXEL_CLOCK_V7_MISC_REF_DIV_SRC_GENLK; 353 354 if (bp_params->signal_type == SIGNAL_TYPE_DVI_DUAL_LINK) 355 clk.miscinfo |= PIXEL_CLOCK_V7_MISC_DVI_DUALLINK_EN; 356 357 if (EXEC_BIOS_CMD_TABLE(setpixelclock, clk)) 358 result = BP_RESULT_OK; 359 } 360 return result; 361 } 362 363 /****************************************************************************** 364 ****************************************************************************** 365 ** 366 ** SET CRTC TIMING 367 ** 368 ****************************************************************************** 369 *****************************************************************************/ 370 371 static enum bp_result set_crtc_using_dtd_timing_v3( 372 struct bios_parser *bp, 373 struct bp_hw_crtc_timing_parameters *bp_params); 374 375 static void init_set_crtc_timing(struct bios_parser *bp) 376 { 377 uint32_t dtd_version = 378 BIOS_CMD_TABLE_PARA_REVISION(setcrtc_usingdtdtiming); 379 380 switch (dtd_version) { 381 case 3: 382 bp->cmd_tbl.set_crtc_timing = 383 set_crtc_using_dtd_timing_v3; 384 break; 385 default: 386 dm_output_to_console("Don't have set_crtc_timing for v%d\n", dtd_version); 387 bp->cmd_tbl.set_crtc_timing = NULL; 388 break; 389 } 390 } 391 392 static enum bp_result set_crtc_using_dtd_timing_v3( 393 struct bios_parser *bp, 394 struct bp_hw_crtc_timing_parameters *bp_params) 395 { 396 enum bp_result result = BP_RESULT_FAILURE; 397 struct set_crtc_using_dtd_timing_parameters params = {0}; 398 uint8_t atom_controller_id; 399 400 if (bp->cmd_helper->controller_id_to_atom( 401 bp_params->controller_id, &atom_controller_id)) 402 params.crtc_id = atom_controller_id; 403 404 /* bios usH_Size wants h addressable size */ 405 params.h_size = cpu_to_le16((uint16_t)bp_params->h_addressable); 406 /* bios usH_Blanking_Time wants borders included in blanking */ 407 params.h_blanking_time = 408 cpu_to_le16((uint16_t)(bp_params->h_total - 409 bp_params->h_addressable)); 410 /* bios usV_Size wants v addressable size */ 411 params.v_size = cpu_to_le16((uint16_t)bp_params->v_addressable); 412 /* bios usV_Blanking_Time wants borders included in blanking */ 413 params.v_blanking_time = 414 cpu_to_le16((uint16_t)(bp_params->v_total - 415 bp_params->v_addressable)); 416 /* bios usHSyncOffset is the offset from the end of h addressable, 417 * our horizontalSyncStart is the offset from the beginning 418 * of h addressable 419 */ 420 params.h_syncoffset = 421 cpu_to_le16((uint16_t)(bp_params->h_sync_start - 422 bp_params->h_addressable)); 423 params.h_syncwidth = cpu_to_le16((uint16_t)bp_params->h_sync_width); 424 /* bios usHSyncOffset is the offset from the end of v addressable, 425 * our verticalSyncStart is the offset from the beginning of 426 * v addressable 427 */ 428 params.v_syncoffset = 429 cpu_to_le16((uint16_t)(bp_params->v_sync_start - 430 bp_params->v_addressable)); 431 params.v_syncwidth = cpu_to_le16((uint16_t)bp_params->v_sync_width); 432 433 /* we assume that overscan from original timing does not get bigger 434 * than 255 435 * we will program all the borders in the Set CRTC Overscan call below 436 */ 437 438 if (bp_params->flags.HSYNC_POSITIVE_POLARITY == 0) 439 params.modemiscinfo = 440 cpu_to_le16(le16_to_cpu(params.modemiscinfo) | 441 ATOM_HSYNC_POLARITY); 442 443 if (bp_params->flags.VSYNC_POSITIVE_POLARITY == 0) 444 params.modemiscinfo = 445 cpu_to_le16(le16_to_cpu(params.modemiscinfo) | 446 ATOM_VSYNC_POLARITY); 447 448 if (bp_params->flags.INTERLACE) { 449 params.modemiscinfo = 450 cpu_to_le16(le16_to_cpu(params.modemiscinfo) | 451 ATOM_INTERLACE); 452 453 /* original DAL code has this condition to apply this 454 * for non-TV/CV only 455 * due to complex MV testing for possible impact 456 * if ( pACParameters->signal != SignalType_YPbPr && 457 * pACParameters->signal != SignalType_Composite && 458 * pACParameters->signal != SignalType_SVideo) 459 */ 460 { 461 /* HW will deduct 0.5 line from 2nd feild. 462 * i.e. for 1080i, it is 2 lines for 1st field, 463 * 2.5 lines for the 2nd feild. we need input as 5 464 * instead of 4. 465 * but it is 4 either from Edid data (spec CEA 861) 466 * or CEA timing table. 467 */ 468 params.v_syncoffset = 469 cpu_to_le16(le16_to_cpu(params.v_syncoffset) + 470 1); 471 472 } 473 } 474 475 if (bp_params->flags.HORZ_COUNT_BY_TWO) 476 params.modemiscinfo = 477 cpu_to_le16(le16_to_cpu(params.modemiscinfo) | 478 0x100); /* ATOM_DOUBLE_CLOCK_MODE */ 479 480 if (EXEC_BIOS_CMD_TABLE(setcrtc_usingdtdtiming, params)) 481 result = BP_RESULT_OK; 482 483 return result; 484 } 485 486 /****************************************************************************** 487 ****************************************************************************** 488 ** 489 ** SELECT CRTC SOURCE 490 ** 491 ****************************************************************************** 492 *****************************************************************************/ 493 494 495 static enum bp_result select_crtc_source_v3( 496 struct bios_parser *bp, 497 struct bp_crtc_source_select *bp_params); 498 499 static void init_select_crtc_source(struct bios_parser *bp) 500 { 501 switch (BIOS_CMD_TABLE_PARA_REVISION(selectcrtc_source)) { 502 case 3: 503 bp->cmd_tbl.select_crtc_source = select_crtc_source_v3; 504 break; 505 default: 506 dm_output_to_console("Don't select_crtc_source enable_crtc for v%d\n", 507 BIOS_CMD_TABLE_PARA_REVISION(selectcrtc_source)); 508 bp->cmd_tbl.select_crtc_source = NULL; 509 break; 510 } 511 } 512 513 514 static enum bp_result select_crtc_source_v3( 515 struct bios_parser *bp, 516 struct bp_crtc_source_select *bp_params) 517 { 518 bool result = BP_RESULT_FAILURE; 519 struct select_crtc_source_parameters_v2_3 params; 520 uint8_t atom_controller_id; 521 uint32_t atom_engine_id; 522 enum signal_type s = bp_params->signal; 523 524 memset(¶ms, 0, sizeof(params)); 525 526 if (bp->cmd_helper->controller_id_to_atom(bp_params->controller_id, 527 &atom_controller_id)) 528 params.crtc_id = atom_controller_id; 529 else 530 return result; 531 532 if (bp->cmd_helper->engine_bp_to_atom(bp_params->engine_id, 533 &atom_engine_id)) 534 params.encoder_id = (uint8_t)atom_engine_id; 535 else 536 return result; 537 538 if (s == SIGNAL_TYPE_EDP || 539 (s == SIGNAL_TYPE_DISPLAY_PORT && bp_params->sink_signal == 540 SIGNAL_TYPE_LVDS)) 541 s = SIGNAL_TYPE_LVDS; 542 543 params.encode_mode = 544 bp->cmd_helper->encoder_mode_bp_to_atom( 545 s, bp_params->enable_dp_audio); 546 /* Needed for VBIOS Random Spatial Dithering feature */ 547 params.dst_bpc = (uint8_t)(bp_params->display_output_bit_depth); 548 549 if (EXEC_BIOS_CMD_TABLE(selectcrtc_source, params)) 550 result = BP_RESULT_OK; 551 552 return result; 553 } 554 555 /****************************************************************************** 556 ****************************************************************************** 557 ** 558 ** ENABLE CRTC 559 ** 560 ****************************************************************************** 561 *****************************************************************************/ 562 563 static enum bp_result enable_crtc_v1( 564 struct bios_parser *bp, 565 enum controller_id controller_id, 566 bool enable); 567 568 static void init_enable_crtc(struct bios_parser *bp) 569 { 570 switch (BIOS_CMD_TABLE_PARA_REVISION(enablecrtc)) { 571 case 1: 572 bp->cmd_tbl.enable_crtc = enable_crtc_v1; 573 break; 574 default: 575 dm_output_to_console("Don't have enable_crtc for v%d\n", 576 BIOS_CMD_TABLE_PARA_REVISION(enablecrtc)); 577 bp->cmd_tbl.enable_crtc = NULL; 578 break; 579 } 580 } 581 582 static enum bp_result enable_crtc_v1( 583 struct bios_parser *bp, 584 enum controller_id controller_id, 585 bool enable) 586 { 587 bool result = BP_RESULT_FAILURE; 588 struct enable_crtc_parameters params = {0}; 589 uint8_t id; 590 591 if (bp->cmd_helper->controller_id_to_atom(controller_id, &id)) 592 params.crtc_id = id; 593 else 594 return BP_RESULT_BADINPUT; 595 596 if (enable) 597 params.enable = ATOM_ENABLE; 598 else 599 params.enable = ATOM_DISABLE; 600 601 if (EXEC_BIOS_CMD_TABLE(enablecrtc, params)) 602 result = BP_RESULT_OK; 603 604 return result; 605 } 606 607 /****************************************************************************** 608 ****************************************************************************** 609 ** 610 ** DISPLAY PLL 611 ** 612 ****************************************************************************** 613 *****************************************************************************/ 614 615 616 617 /****************************************************************************** 618 ****************************************************************************** 619 ** 620 ** EXTERNAL ENCODER CONTROL 621 ** 622 ****************************************************************************** 623 *****************************************************************************/ 624 625 static enum bp_result external_encoder_control_v3( 626 struct bios_parser *bp, 627 struct bp_external_encoder_control *cntl); 628 629 static void init_external_encoder_control( 630 struct bios_parser *bp) 631 { 632 switch (BIOS_CMD_TABLE_PARA_REVISION(externalencodercontrol)) { 633 case 3: 634 bp->cmd_tbl.external_encoder_control = 635 external_encoder_control_v3; 636 break; 637 default: 638 bp->cmd_tbl.external_encoder_control = NULL; 639 break; 640 } 641 } 642 643 static enum bp_result external_encoder_control_v3( 644 struct bios_parser *bp, 645 struct bp_external_encoder_control *cntl) 646 { 647 /* TODO */ 648 return BP_RESULT_OK; 649 } 650 651 /****************************************************************************** 652 ****************************************************************************** 653 ** 654 ** ENABLE DISPLAY POWER GATING 655 ** 656 ****************************************************************************** 657 *****************************************************************************/ 658 659 static enum bp_result enable_disp_power_gating_v2_1( 660 struct bios_parser *bp, 661 enum controller_id crtc_id, 662 enum bp_pipe_control_action action); 663 664 static void init_enable_disp_power_gating( 665 struct bios_parser *bp) 666 { 667 switch (BIOS_CMD_TABLE_PARA_REVISION(enabledisppowergating)) { 668 case 1: 669 bp->cmd_tbl.enable_disp_power_gating = 670 enable_disp_power_gating_v2_1; 671 break; 672 default: 673 dm_output_to_console("Don't enable_disp_power_gating enable_crtc for v%d\n", 674 BIOS_CMD_TABLE_PARA_REVISION(enabledisppowergating)); 675 bp->cmd_tbl.enable_disp_power_gating = NULL; 676 break; 677 } 678 } 679 680 static enum bp_result enable_disp_power_gating_v2_1( 681 struct bios_parser *bp, 682 enum controller_id crtc_id, 683 enum bp_pipe_control_action action) 684 { 685 enum bp_result result = BP_RESULT_FAILURE; 686 687 688 struct enable_disp_power_gating_ps_allocation ps = { { 0 } }; 689 uint8_t atom_crtc_id; 690 691 if (bp->cmd_helper->controller_id_to_atom(crtc_id, &atom_crtc_id)) 692 ps.param.disp_pipe_id = atom_crtc_id; 693 else 694 return BP_RESULT_BADINPUT; 695 696 ps.param.enable = 697 bp->cmd_helper->disp_power_gating_action_to_atom(action); 698 699 if (EXEC_BIOS_CMD_TABLE(enabledisppowergating, ps.param)) 700 result = BP_RESULT_OK; 701 702 return result; 703 } 704 705 /****************************************************************************** 706 ******************************************************************************* 707 ** 708 ** SET DCE CLOCK 709 ** 710 ******************************************************************************* 711 *******************************************************************************/ 712 713 static enum bp_result set_dce_clock_v2_1( 714 struct bios_parser *bp, 715 struct bp_set_dce_clock_parameters *bp_params); 716 717 static void init_set_dce_clock(struct bios_parser *bp) 718 { 719 switch (BIOS_CMD_TABLE_PARA_REVISION(setdceclock)) { 720 case 1: 721 bp->cmd_tbl.set_dce_clock = set_dce_clock_v2_1; 722 break; 723 default: 724 dm_output_to_console("Don't have set_dce_clock for v%d\n", 725 BIOS_CMD_TABLE_PARA_REVISION(setdceclock)); 726 bp->cmd_tbl.set_dce_clock = NULL; 727 break; 728 } 729 } 730 731 static enum bp_result set_dce_clock_v2_1( 732 struct bios_parser *bp, 733 struct bp_set_dce_clock_parameters *bp_params) 734 { 735 enum bp_result result = BP_RESULT_FAILURE; 736 737 struct set_dce_clock_ps_allocation_v2_1 params; 738 uint32_t atom_pll_id; 739 uint32_t atom_clock_type; 740 const struct command_table_helper *cmd = bp->cmd_helper; 741 742 memset(¶ms, 0, sizeof(params)); 743 744 if (!cmd->clock_source_id_to_atom(bp_params->pll_id, &atom_pll_id) || 745 !cmd->dc_clock_type_to_atom(bp_params->clock_type, 746 &atom_clock_type)) 747 return BP_RESULT_BADINPUT; 748 749 params.param.dceclksrc = atom_pll_id; 750 params.param.dceclktype = atom_clock_type; 751 752 if (bp_params->clock_type == DCECLOCK_TYPE_DPREFCLK) { 753 if (bp_params->flags.USE_GENLOCK_AS_SOURCE_FOR_DPREFCLK) 754 params.param.dceclkflag |= 755 DCE_CLOCK_FLAG_PLL_REFCLK_SRC_GENLK; 756 757 if (bp_params->flags.USE_PCIE_AS_SOURCE_FOR_DPREFCLK) 758 params.param.dceclkflag |= 759 DCE_CLOCK_FLAG_PLL_REFCLK_SRC_PCIE; 760 761 if (bp_params->flags.USE_XTALIN_AS_SOURCE_FOR_DPREFCLK) 762 params.param.dceclkflag |= 763 DCE_CLOCK_FLAG_PLL_REFCLK_SRC_XTALIN; 764 765 if (bp_params->flags.USE_GENERICA_AS_SOURCE_FOR_DPREFCLK) 766 params.param.dceclkflag |= 767 DCE_CLOCK_FLAG_PLL_REFCLK_SRC_GENERICA; 768 } else 769 /* only program clock frequency if display clock is used; 770 * VBIOS will program DPREFCLK 771 * We need to convert from KHz units into 10KHz units 772 */ 773 params.param.dceclk_10khz = cpu_to_le32( 774 bp_params->target_clock_frequency / 10); 775 dm_logger_write(bp->base.ctx->logger, LOG_BIOS, 776 "%s:target_clock_frequency = %d"\ 777 "clock_type = %d \n", __func__,\ 778 bp_params->target_clock_frequency,\ 779 bp_params->clock_type); 780 781 if (EXEC_BIOS_CMD_TABLE(setdceclock, params)) { 782 /* Convert from 10KHz units back to KHz */ 783 bp_params->target_clock_frequency = le32_to_cpu( 784 params.param.dceclk_10khz) * 10; 785 result = BP_RESULT_OK; 786 } 787 788 return result; 789 } 790 791 792 /****************************************************************************** 793 ****************************************************************************** 794 ** 795 ** GET SMU CLOCK INFO 796 ** 797 ****************************************************************************** 798 *****************************************************************************/ 799 800 static unsigned int get_smu_clock_info_v3_1(struct bios_parser *bp); 801 802 static void init_get_smu_clock_info(struct bios_parser *bp) 803 { 804 /* TODO add switch for table vrsion */ 805 bp->cmd_tbl.get_smu_clock_info = get_smu_clock_info_v3_1; 806 807 } 808 809 static unsigned int get_smu_clock_info_v3_1(struct bios_parser *bp) 810 { 811 struct atom_get_smu_clock_info_parameters_v3_1 smu_input = {0}; 812 struct atom_get_smu_clock_info_output_parameters_v3_1 smu_output; 813 814 smu_input.command = GET_SMU_CLOCK_INFO_V3_1_GET_PLLVCO_FREQ; 815 816 /* Get Specific Clock */ 817 if (EXEC_BIOS_CMD_TABLE(getsmuclockinfo, smu_input)) { 818 memmove(&smu_output, &smu_input, sizeof( 819 struct atom_get_smu_clock_info_parameters_v3_1)); 820 return smu_output.atom_smu_outputclkfreq.syspllvcofreq_10khz; 821 } 822 823 return 0; 824 } 825 826